IEEE International Workshop on Defect Based Testing, April 2001.Los Angeles, CA, USA

23

IDDT Testing: An Efficient Method for Detecting Delay Faults and Open Defects*

Masahiro Ishida1, Dong Sam Ha2, Takahiro Yamaguchi1,Yoshihiro Hashimoto3, and Tadahiro Ohmi4

1Advantest Laboratories Co., Ltd. Sendai, Miyagi, Japan2Virginia Polytechnic Institute and State University, Blacksburg, VA

3Advantest Corporation, Ohra, Gunma, Japan4Tohoku University, Sendai, Miyagi, Japan

ishida@atl.advantest.co.jp

* The VLSI chip in this study has been fabricated in the chip fabricationprogram of VLSI Design and Education Center (VDEC), the University ofTokyo with the collaboration by Rohm Corporation and Toppan PrintingCorporation.

AbstractSome open defects in VLSI circuits may cause delay faults,and testing of open defects and delay faults remain difficultproblem. In this paper, we show that i) some open defectscause delay faults and ii) those open defects and delayfaults cause variations in IDDT waveforms. We propose anew IDDT testing method for detection of open defects anddelay faults. Our method exploits the phenomenon that anopen defect generates a local maximum in the IDDT

waveform. We present experimental results performed ontwo test chips.

1. INTRODUCTION

IDDQ testing monitors quiescent power supply current.It has been an effective method for testing short faults[1]-[4]. Since open defects often do not lead to abnormallyhigh quiescent current, IDDQ testing may be ineffective fordetecting open defects. IDDT testing methods, whichobserve instantaneous or mean values of transient powersupply current, have been proposed to replace orcomplement IDDQ testing [5]-[8]. Sachdev et al. proposedan IDDT testing method, which employs a current probe tomonitor transient current [7]. Min and Li proposed an IDDT

testing method based on measuring the mean value oftransient currents [8]. They showed that their proposedmethod can detect open faults which cannot possibly bedetected by stuck-at fault testing or IDDQ testing methods.Different approaches for detecting open and short defects

were studied in [9]-[11]. Germida et al. and Plusquellic etal. investigated monitoring transient voltages to detectthose types of faults [9], [10]. Kim et al. suggested the useenergy consumption ratio to cover such faults [11]. In thispaper, we investigate the capability of IDDT testing indetecting opens and delay faults.

The paper is organized as follows. Section 2 givespreliminaries necessary to understand our proposedmethod. Section 3 describes relationships between opendefects, delay faults, and IDDT. We also propose our method,which exploits the relationships. In Section 4 we presentexperimental results performed on two test chips. Section 5summarizes the paper.

2. PRELIMINARIES

IDDT is a transient power supply current which flowsinto a circuit through VDD pin in the transient state of theCUT. It is the sum of transient currents of individual gatesof the circuit. Transient currents of a CMOS inverter fortwo different slopes of the input are shown in Figure 1. Thefigure shows that as the slope of the input signal becomesless steep, the transient current is delayed longer, i.e., thestarting point, the peak point, and the stopping points of the

Vin, Iint

00 Time

Vin2

Vin1

Iint1 Iint

2

Figure 1: Transient current of a CMOS inverter.

24

transient current are delayed in time.Some open defects make the defective node voltages

to rise slowly, and the slow rise of a node voltage delays thewaveform of the transient current. This suggests that IDDT

testing may be used to detect some open defects. Moreover,since delay of an input signal due to a delay fault alsodelays the transient current of the gate, IDDT testing canpossibly be used to test such delay faults. We examine therelationship between open defects, delay faults and IDDT inSection 3.

Let us consider a path P = g0, g1, g2, ... , gm of aCMOS circuit, where g0 is the input node of the path P, andg1, g2, ... , gm are the output of the logic gate G1, G2, ... , Gm

on the path, respectively. Suppose that a test vector pair T =<V1, V2> activates the path P. Let τ0, τ1, ... , τm as the signaltransition timing of node g0, g1, ... , gm, respectively. Theoverall transient current of the path is superposition oftransient currents of individual gates. Since the short circuitcurrent of gate Gi is peak at τi, local maximums may occurat τ0, τ1, ... , τm provided individual gate delays arereasonably large. The IDDT waveform of the path underslow gate delays is shown in Figure 2, which shows m localmaximums at the transition points. However, it is importantto note that the number of local maximums m depends onseveral factors such as delay, type, and size of gates on the

path. Figure 3 shows the simulation result of a cascade offour 2-input NAND gates, in which an input of each gate istied to VDD, and all NAND gates are designed to be slow.The figure shows four local maximums and a ringing noise.

3. RELATIOSHIPS BETWEEN OPENS,DELAY FAULTS, AND IDDT

We investigated relationships between open defects,delay faults, and IDDT through simulation and present theresults in this section. Based on the simulation results, wepropose an IDDT testing method, which can be used to detectsome open defects and delay faults. So our method cancomplement existing methods for detection of open defectsand delay faults. The circuit considered for the simulationis a cascade of four identical CMOS inverters as shown inFigure 4. It contains an open defect modeled as a resistorRopen between two nodes, IN2 and IN2*. The underlyingtechnology of the circuit is 0.6 µm n-well process. Allresults presented in this section were obtained throughSPICE simulation.

3.1. Opens and delay faults

First experiment is to investigate the relationshipbetween open defects and delay faults. We varied theresistance Ropen of the open defect from 0 Ω to 10 MΩ andmeasured the low-to-high (i.e., rising transition) andhigh-to-low (i.e., falling transition) propagation delays.The results are shown in Figure 5 (a). Delay fault size in thefigure is the deference between the propagation delays ofthe defect-free circuit and of the defective circuits. Figure 5shows that i) the open defect causes a delay fault for thecircuit, and ii) the delay fault size is roughly proportional tothe severity (equivalently resistance) of the open defect forboth rising and falling transitions. The input and outputvoltage waveforms for four different values (0 Ω, 200kΩ, 500 kΩ, and 1 MΩ) of open resistance Ropen are shownin Figure 5 (b). The delay of the defect-free circuit is lessthan 1 ns, but the delay increases to over 10 ns for Ropen = 1MΩ. We tried open defects at several other locations and

G1 G2 Gm

g0 g1 g2 gm-1 gm

ττττ0 ττττ1 ττττ2 ττττm-1 ττττm

. . .

. . .

IDDT

00 Time

. . .

ττττ0 ττττ1 ττττm-1ττττm-2

(b)

(a)

Figure 2: Transition timing and the transientcurrent. (a) Timing diagram. (b) Transient current.

4 5 6 7 8 9 10

0

0.1

0.2

0.3

Time [ns]

I DD

T[m

A]

Figure 3: Transient current of a cascade of four2-input NAND gates.

IN1 OUT

GND

VDD

G1 G2 G3 G4

IDDT = ΣΣΣΣ IGn

IG1 IG2 IG3 IG4

IN2 IN3 IN4

Ropen

IN2*

Figure 4: A CMOS inverter chain withan open defect.

25

noticed the same trend, i.e., the severity of the open defectincreases, the delay fault size increases. Based on ourobservations from the experiment, we claim that some opendefects in CMOS circuits cause delay faults.

3.2. Opens and IDDT

Next, we investigated the relationship between opendefects and the transient current IDDT. Figure 6 shows thesimulation result for four different values (0 Ω, 200kΩ, 500 kΩ, and 1 MΩ) of the resistance Ropen. The opendefect causes the input signal of the gate G2 to rise slowlydue to the increased RC delay (Refer to Figure 6 (a)). Therise time of the input signal is roughly proportional to theresistance Ropen. The waveforms of the transient currentsare shown in Figure 6 (b). As the resistance Ropen increases,the peak of the transient current is delayed, and the durationof the current increases. Note that the peak of a transientcurrent occurs roughly at the midpoint of the inputtransition. The above trend is true for open defects at some

other locations. Based on the experiment, we claim thatsome open defect delays the peak point of the transientcurrent.

3.3. Proposed IDDT testing method

Our simulation results show that some open defectscause delay faults and some delay faults delay thewaveform of IDDT. Suppose that a test vector pair T = <V1,V2> activates a path P under test, and the test pattern V2 isapplied at time 0. Let us suppose that the output of the lastgate Gm on the path switches at tm and the delay of the gateis δm Then the path delay tpd is equal to tm and the input ofgate Gm switches at (tm-δm). If the propagation delay is tpd >TMAX, a delay fault occurred on the path. Equivalently, thepath is fault free if

( )mMAXmm Tt δδ −<− )( (1)

The proposed method is to observe the IDDT

waveform of the CUT to decide if the above condition ismet or not for the test circuit. We explain our method usingFigure 7. (Note that the figure is not in proportion forconvenience.) Assume that a local maximum exists at(tm-δm) in the IDDT waveform for a time being. We observethe IDDT waveform from time (TMAX-δm) to a predeterminedtime tf. The observation window is denoted as TOBSERV inthe figure. If there is one or more local maximums in theobservation window, the last local maximum correspondsto the switching of gate Gm. Hence, gate Gm switches after(TMAX -δm) to indicate occurrence of a delay fault on thepath. In fact, upon detection of the first local maximum inthe observation window, we can declare existence of adelay fault. It may be interesting to note that the delay faultsize can be obtained from the timing of the last localmaximum.

If there is no local maximum in the observationwindow, i.e., gate Gm switches before (TMAX-δm), there mayor may not be a delay fault. It is inclusive for our method. A

Time

IDDT

∆∆∆∆

TMAX - δδδδm

TOBSERV

0 tm - δδδδm tf

Figure 7: Proposed IDDT testing method.

10 100 1 k 10 k 100 k 1 meg 10 Meg1 p

10 p

100 p

1 n

10 n

100 n

Ropen [ΩΩΩΩ]

Del

ayFa

ult

Siz

e[s

ec]

Falling Transition

Rising Transition

(b)

0 5 10 15 20 25 30

0

2

4

6

Time [ns]

OU

T[V

] Defect FreeRopen = 200k ΩΩΩΩRopen = 500k ΩΩΩΩRopen = 1meg ΩΩΩΩ

IN1

(a)

Figure 5: Delay fault size for various Ropen.(a) Delay fault size. (b) Output waveforms.

0 5 10 15 20 25 30

0

2

4

6

Time [ns]

IN2*

[V]

0 5 10 15 20 25 30

0

1

2

3

Time [ns]

I DD

T[m

A]

Defect FreeRopen = 200k ΩΩΩΩRopen = 500k ΩΩΩΩRopen = 1meg ΩΩΩΩ

(a)

(b)

DefectFree 200k ΩΩΩΩ 500k ΩΩΩΩ

1meg ΩΩΩΩ

Figure 6: Transient responses of the circuit forvarious Ropen. (a) Input waveforms of the loading

gate G2. (b) IDDT waveforms.

26

possible scenario is that multiple gates switch in proximityin a continuous manner between (TMAX-δm) and (tm-δm) inthe observation window. When a test pattern is applied totest a path, other paths may be activated accidentally.According to our experiment performed on test chips (to bereported in Section 4), distinctive local maximums exist inthe observation window under the presence of open defects(equivalently delay faults).

We discuss several practical issues regarding theproposed IDDT method. First, the height of a local maximumshould be above a certain threshold value (i.e. ∆ in Figure7) to immune the noise. Second, when the proposedmethod is used in conjunction with a delay testing methodbased on logic monitoring, it is a good idea to make thestopping time tf of the observation window and thesampling time of logic values (for the delay testingmethod) identical. Hence, any delay fault that causes alocal maximum to fall beyond the observation window willbe detected by the delay testing method based on logicmonitoring. Third, the gate delay δm varies depending onthe path under test. Hence, it is necessary to set a smallfixed value. Finally, an ATE system does not need to storethe defect free IDDT waveform, rather a threshold current inthe observation current.

4. EXPERIMENTAL RESULTS OF TWOTEST CHIPS

We applied the proposed method on two test chips, anISCAS85 benchmark circuit c6288 and a Viterbi decoder.The benchmark circuit c6288 is a combinational circuitwith about 2400 gates, while the Viterbi decoder is asequential circuit with about 2500 standard cells. CMOStransmission gates were used to introduce open defects intothe test chips. Both of the circuits were synthesized, laidout, and then fabricated in the chip fabrication program ofVDEC, the University of Tokyo in Japan. The technologyof the test circuits is 0.6 µm n-well process.

The setup for IDDT measurements is illustrated inFigure 8. The setup includes the CUT, a decoupling

capacitor (CL), a current probe (Tektronix CT-1), a digitalsampling oscilloscope (Tektronix TDS754C), and an ATEsystem (Advantest T6671E). The ATE supplies the powerand test patterns to a CUT. The oscilloscope monitors thewaveform of the supply current through the current probe.4.1. ISCAS85 benchmark circuit

Ten single open defects were inserted at arbitrarylocations into c6288 (Refer to Figure 9.) The test circuitwas measured to obtain critical path delays and IDDT

waveforms for two test vector pairs, T1 = < all 0, all 1> andT2 = < all 0, “00110011...0011”>.

We created a faulty circuit by introducing an open

T6671ECUT

GND

IDDTTestpatterns

CL

Trig. Ch.

TEK CT-1

TEK TDS754C

VDD

Performance Board

PPS

Figure 8: Setup for IDDT measurements.

Figure 9: Locations of defects in c6288benchmark

(a)

(b)

-50 0 50 100 150 200 250-2

0

2

4

6

8

Time [ns]

n42

41g

at[V

]

Defect O1c, T2 = < "00000000...", "00110011..." >

-50 0 50 100 150 200 250

-50

0

50

100

150

Time [ns]

I DD

T[m

A] Defect Free

Defective

Defect FreeDefective

Figure 10: Experimental results for an opendefect O1c. (a) Primary output signals. (b) IDDT

waveforms.

-50 0 50 100 150 200 250

Defect O2c, T1 = < "00000000...", "11111111..." >

-50 0 50 100 150 200 250

-2

0

2

4

6

8

Time [ns]

n61

60g

at[V

]

-50

0

50

100

150

Time [ns]

I DD

T[m

A]

(a)

(b)

Defect FreeDefective

Defective

Defect Free

Figure 11: Experimental results for an open defectO2c. (a) Primary output signals. (b) IDDT

waveforms.

27

defect named O1c. Figure 10 shows the delay of a criticalpath and IDDT waveforms of defect-free and defectivecircuits for the test pattern pair T2 in which the second testpattern was applied at 0 ns. The critical delay of thedefective circuit is about 130 ns, while that of thedefect-free circuit is about 45 ns (Refer to Figure 10 (a)).Therefore, the open defect causes a delay fault. On theother hand, the IDDT waveform in Figure 10 (b) shows thatthe IDDT of the defect free circuit settles down around 80 ns,while the IDDT for the defective circuit has a largesecondary pulse (i.e., a local maximum) starting at around120 ns. Hence, the proposed method detects the opendefect O1c provided the secondary pulse falls in theobservation window. In addition, the delay fault size can becalculated, if necessary, by measuring the timing of thesecondary pulse. Note that the open defect does not causeexcessive IDDQ, and hence an IDDQ testing method wouldnot detect the fault.

We experimented another faulty circuit with an opendefect named O2c. Figure 11 shows the critical delay andIDDT waveforms of defect-free and defective circuits for atest pattern pair T1, in which the second test pattern wasapplied at 0 ns. The open defect O2c also causes a delayfault and a variation in IDDT. Like the previous case, a largesecondary pulse with peak at around 190 ns appears in theIDDT waveform of the defective circuit, so our methoddetects the fault.

Due to unavailability of a test pattern generator, wewere unable to experiment the remaining eight faults. So itis inclusive if our method would detect these faults.

4.2. Viterbi decoder

We inserted two single open defects at arbitrary blockinto the Viterbi decoder (which is highly sequential) andmeasured output signals and IDDT waveforms using a set offunctional test vectors. Figure 12 shows the voltagewaveforms of a primary output eop[1] and IDDT waveforms

of the defect-free circuit and a defective circuit with anopen defect named O1s. The test pattern was applied at 0 ns.The output signal waveform in Figure 12 (a) shows that theprimary output eop[1] of the defect-free circuit has nosignal transition, while that of the defective circuit has ahazard switching back to the fault-free value “1” at around220 ns. Like the combinational benchmark circuit, the IDDT

waveform of a faulty circuit has a secondary pulse ataround 220 ns. So the proposed method detects the opendefect. Note that the open defect causes a logic fault if it issampled before 220 ns. So a stuck-at testing or a delaytesting based logic monitoring will also detect the faultprovided the value is sampled at a right time. However thisfault is a redundant fault for both a stuck-at testing and adelay testing.

Experimental results with another open defect namedO2s are shown in Figure 13 and 14. The open defect has noimpact on all primary outputs. Output transition timings ofthe defect-free circuit and of the defective circuit areidentical for every primary outputs (Refer to Figure 13).

-50 0 50 100 150 200 250 300 350 400 450-2

0

2

4

6

Time [ns]

v(eo

p[1

])[V

]

Defect O1s

-50 0 50 100 150 200 250 300 350 400 450-40-20

020406080

Time [ns]

I DD

T[m

A] Defect Free

Defective

Defect FreeDefective

(a)

(b)

Figure 12: Experimental results for an opendefect O1s. (a) Primary output signals. (b) IDDT

waveforms.

0 2 4 6 8 10 12 14 16 18-20246

v(eo

p[2

])[V

]

0 2 4 6 8 10 12 14 16 18-20246

v(eo

p[1

])[V

]

0 2 4 6 8 10 12 14 16 18-20246

Time [µµµµs]

v(eo

p[0

])[V

]

Circuit Initializing Defect FreeDefectiveDefect O2s

Figure 13: Primary output signals of defect-freeand defective circuit for defect O2s.

(a)

(b)

(c)

7.0 7.1 7.2 7.3 7.4

V(e

op

[2])

[V]

7.0 7.1 7.2 7.3 7.4

I DD

T[m

A]

7.0 7.1 7.2 7.3 7.4

Mag

nifi

edI D

DT

[mA

]

Defect O2s

-20246

-20

0

20

40

-1

0

1

2

Defect FreeDefective

Defect FreeDefective

Defect FreeDefective

Time [µµµµs]

Time [µµµµs]

Time [µµµµs]

7.4

Figure 14: Experimental results for an opendefect O2s. (a) Output signals. (b) IDDT waveforms.

(c) Magnified IDDT waveforms.

28

This is because that the effect of the delay does notpropagate to any primary output. However, the open defectcauses a secondary pulse in IDDT as shown in Figure 14 (c).This implies that the open defect can be detected by theproposed method but not by any testing method based onlogic monitoring.

In summary, the experimental results performed ontwo test chips demonstrate the practicality of our methodfor some open defects. As we argued in the previoussection, a delay fault caused by an open defect indeedgenerates a distinctive local maximum.

5. CONCLUSION

Shorts and opens are the major type of defects inVLSI circuits. IDDQ testing has been effective for detectingshort defects. Testing of open defects and delay faultsremain a difficult and challenging problem. Traditional testmethods based on logic monitoring are ineffective fortesting open defects and/or delay faults.

In this paper, we showed, through SPICE simulations,that i) some open defects cause delay faults and ii) thoseopen defects and delay faults cause variations in IDDT

waveforms. We proposed a new IDDT testing method fordetection of open defects and delay faults. Our methodexploits the phenomenon that an open defect generates alocal maximum in the IDDT waveform. We demonstratedfeasibility of our method through experiments performedon the two test chips. Hence, our method can be useful tocomplement exiting methods for detection of open defectsand delay faults.

Several problems should be addressed to apply theproposed method in practice. Many factors such as processvariation, drift, and the severity and location of an opendefect affect the amount of abnormal current and the size ofthe delay defect. To make a local maximum present, a smallnumber of paths should be activated at a time, which maynecessitate logic partition. Finally, detection of localmaximums for high-speed circuits may pose a technicalproblem.

ACKNOWLEDGEMENTS

We would like to thank Mr. J. Nishiura, Director ofATE Division of Advantest Corp., Mr. N. Kotani, GeneralManager of SoC Tester Technology Division of AdvantestCorp., Dr. Y. Maeda, Director of Advantest LaboratoriesLtd., and Mr. M. Kamiya, President of AdvantestLaboratories Ltd. for their encouragement and support tothis research.

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