iec 61850-9-2 conformance test and the required network bandwidth
DESCRIPTION
IEC 61850-9-2 conformance test and the required network bandwidth. Smart Grid Testing department Woohyun Seo. Contents. Merging Unit Introduction, Advantages, Standards Tripping in Process Bus Conformance test Network Bandwidth for Process Bus Conclusion. 1. Merging Unit - Introduction. - PowerPoint PPT PresentationTRANSCRIPT
IEC 61850-9-2 conformance test and the required net-
work bandwidth
Smart Grid Testing depart-ment
Woohyun Seo
1. Merging Unit• Introduction, Advantages, Standards
2. Tripping in Process Bus
3. Conformance test
4. Network Bandwidth for Process Bus
5. Conclusion
Contents
1. Merging Unit - IntroductionBusbar
- Analog Input Transformers
- Analog Measurement
- A/D conversion
are moved away from the IEDs and “are placed” into the merging
unit
Conven-tional CTs/VTs
- Advantage . Good saturation curve- Disadvantage . Signal level output . Noise influence
Non-Conventional CTs/VTs
Merging Unit
Propri-etary Link
Propri-etary Link
Controlled Ethernet Ports
Line protec-tion
PIOC, PTOV, …
Bay controllerCSWI, CSYN, …
Device control inter-face
Process Bus
Time synchConfigura-
tion
1. Merging Unit - Advantages
• Advantage of process bus with MERGING UNIT– Reduce wiring cables and # of CTs/VTs
• In conventional scheme, every IED needs CT(s) and/or VT(s) for processing
– Improved measuring accuracy• Short distance between CTs/VTs and signal processor
– Adopting high-performance eCT/eVT• Small, Light, Broad dynamic range, Isolation between
primary & secondary circuits, etc – Unified platform for information sharing
• Merging unit broadcast the digitized measured data based on IEC 61850 standard
1. Merging Unit - StandardsMerging
UnitSignal processing interface
Digital interface(Communication)
IEC TC38 WG37
IEC TC57 WG10IEC 61869-7, ADDITIONAL REQUIRE-
MENTS FOR ELECTRONIC VOLTAGE TRANS-FORMERS
IEC 61869-8, ADDITIONAL REQUIRE-MENTS FOR ELECTRONIC CURRENT RANS-FORMERS
IEC 61869-9, DIGITAL INTERFACE FOR INSTRUMENT TRANSFORMERS
IEC 61869-13, Stand Alone Merging Unit
…
Not published
IEC 61850-9-1, Specific Communication Service Map-ping (SCSM) – Sampled values over serial unidirec-tional multidrop point to point link
IEC 61850-9-2, Specific communication service map-ping (SCSM) – Sampled values over ISO/IEC 8802-3
Withdrawn
Implementa-tionImplementation Guideline for Digital Interface to Instru-ment Transformers using IEC 61850-9-2
Conformance test procedure
Test procedures for Sampled Values Publishers according to the "Implementation Guideline for Digital Interface to In-strument Transformers using IEC 61850-9-2" (9-2LE)
GOOSE OUT
2. Tripping in Process Bus
GOOSE IN GOOSE OUT
SAMPLED VALUES
Time require-ment is more critical!!!
2. Tripping in Process Bus
• A/D signal processing time delay– Primary condition for available protection
• Guideline : 3 ms (IEC 60044-8)
• Packet jitter and latency control– Part of performance test
• Only the total number of packets in 1 sec existed
• Standard based syntax– Following IEC 61850-9-2 and IEC 61869 series
• Network bandwidth– Lack of bandwidth makes packet loss
• Out of range from conformance test
2. Tripping in Process Bus
3. Conformance test
• Conformance test procedure– Documentation : 2 test cases– Configuration : 9 test cases– Communication services : 17 test cases
• 50/60 Hz, 80/256 samples
According to “Guideline”, Time master is based on “PPS”
3. Conformance test
• SV conformance test– Verify conformity and performance
• Performance is very important for MU• Accuracy test is not included
• Conformity– Connecter and Link layer format verification
• 100Base-FX full duplex with ST, MT-RJ, LC fibers or Rj45
– APDU or ASDU format verification– Quality and Test bit verification
3. Conformance test
• Performance test– SV maximum delay criterion : ~3 ms(3.3 ms)
– Verification # of messages per cycle
PPS pulse SV with
Sm-pCnt=0
SV de-lay
Publisher(MU)
Subscriber
288000 messages for 80 samples of 60 Hz
… … …
PPS pulse
PPS pulse
Jitter and latency control are required!
3. Conformance test
• Limitation of SV conformance test– Not verifying focusing on packet treatment
• What if MU makes the signal processing delay?
PPS pulse
SV with Sm-pCnt=0
SV de-lay
Vo, Io
Vo, Io
Real tripping time may be de-layed
CT/VT or eCT/eVT
Signal process-ing delay
4. Network Bandwidth for Process Bus• Background from IEC 61850-9-1
– Telegram length : 888bit(packet) + 96bit(interFrame)
– BW : 80samples*60Hz*984bits < 5Mbps (per stream)Reliable?
4. Network Bandwidth for Process Bus
• Simple test– Merging Unit
• 100Mbps, Max 2 streams, 80samples/Hz– Time Synch
• 1 PPS from GPS– Switch
• Separate network only for process bus with MU• Switching latency : 7 micro second• Switching bandwidth : 9.2 Gbps
– Testing tool• Smart bit applications• Packet size : 140 bytes(SMV packet : 128 bytes)
4. Network Bandwidth for Process Bus• 1 stream
Rate Tested(%)(01,01,01) to
(01,01,02) (us)-CT
70.00 18.0
75.00 18.6
80.00 17.4
85.00 17.7
90.00 17.7
95.00 1512529.4
100.00 1502608.9
Rate Tested(%) (01,01,01) to (01,01,02) (%)
70.00 0.000
75.00 0.000
80.00 0.000
85.00 0.000
90.00 0.000
95.00 1.080
100.00 5.789
Passed Rate(%)(01,01,01) to
(01,01,02) (pks/sec)
94.12 73529
Through-put
La-tency
Packet Loss
Network load : 5.88 Mbps
• Switching bandwidth(9 Gbps) is enough to handle this amount of traffic load
(9,000 / 5.88 = 1,530 ports can be supported)
4. Network Bandwidth for Process Bus• 2 streams
Rate Tested(%)(01,01,01) to
(01,01,02) (us)-CT
70.00 18.9
75.00 17.0
80.00 19.0
85.00 23.0
90.00 2649.6
95.00 1508004.1
100.00 1499575.3
Rate Tested(%) (01,01,01) to (01,01,02) (%)
70.00 0.000
75.00 0.000
80.00 0.000
85.00 0.000
90.00 1.906
95.00 7.156
100.00 11.577
Passed Rate(%)(01,01,01) to
(01,01,02) (pks/sec)
88.40 69061
Through-put
La-tency
Packet Loss
Network load : 11.6 Mbps= 2*5.8 Mbps
• Network load for 2 streams is similar to twice one for 1 stream
5. Conclusion
• Expectation– Network Bandwidth measurement in the
real (simulated) process bus network• Theoretically, 100 Mbps based network can handle
more than 10 MUs • But, need to check if how many MUs can imple-
mented
– For more stable process bus implementa-tion, the critical points will be• Actual A/D signal processing time delay in device• Packet jitter and latency delay from device