• 2004 IEEE International Solid-State Circuits Conference 0-7803-8267-6/04 ©2004 IEEE

ISSCC 2004 / SESSION 20 / DIGITAL-TO-ANALOG CONVERTERS / 20.4

20.4 A 2GS/s 3b ∆Σ-Modulated DAC with a Tunable Switched-Capacitor Bandpass DAC Mismatch Shaper

Todd S. Kaplan1,2, Joseph F. Jensen2, Charles H. Fields2, M. Frank Chang1

1University of California, Los Angeles, CA2HRL Laboratories, LLC, Malibu, CA

Linearized multibit DACs that can generate IF or RF signalshave many applications in direct digital synthesis and multibit∆Σ modulation. Mismatch shapers are attractive for lineariza-tion because they can shape static and dynamic DAC mismatcherrors away from a frequency of interest, for a wide variety ofDAC architectures, technologies, and types of mismatches.However, mismatch-shaping circuitry to date has been too slowto linearize direct-IF generating DACs. Due to the algorithmiccomplexity and resultant critical path delays, the fastest pub-lished mismatch shaped DACs directly generate signals at orbelow 2MHz [1].

We present a 3b mismatch-shaped ∆Σ-modulated DAC that candirectly generate narrowband signals between 250MHz and750MHz, with less than –80dBc intermodulation distortion overthe entire frequency range.

The DAC architecture is shown in Fig. 20.4.1. A decoder con-verts a 3b input into a thermometer code. Each bit is then rout-ed to an individual DAC using a tree-structured routing architec-ture [2]. Pipelining is employed between each router stage toeliminate the dependence of the delay on the number of bits. Anexternal control voltage tunes the routers so as to shape the DACerrors away from a desired frequency band. The final routersthen feed the data into eight one-bit differential current-steeringDACs. Since eight DACs are used where only seven levels arerequired, the decoder introduces an additional signal which isalways low. Each DAC has an individual current control. Thesecurrent controls are used to artificially introduce DAC mis-matches and hence easily test the effectiveness of the mismatchshaping operation.

The router architecture is shown in Fig. 20.4.2. A 2n-bit ther-mometer-coded word is subdivided into two n-bit thermometer-coded words. An exor block determines if the input signals of thetwo branches are different, which then determines if the outputsto the two branches change when the router switches. The shapeof the DAC errors is then determined by an internal bandpass ∆Σmodulator.

While the input and output words are both digital, this ∆Σ mod-ulator is implemented with tunable switched-capacitor circuitryto increase the flexibility, while reducing the power dissipationand transistor count. Linear transconductors ai and DACs bi per-form the multiplication functions. Addition is performed bymerging transconductor currents and converting the output intoa voltage with a resistor. Two simple track-and-hold amplifierscreate the analog delay [3]. The resonant frequency of the modu-lator, and hence the position of the notch in the DAC errors, istuned by simultaneously adjusting the gains of b1 and a1.Feedback coefficient b1 is proportional to the resonant frequencyset by a1. Consequently, a single external voltage source can beused to tune the DAC mismatch shaper between Fs/8 and 3Fs/8.The Q of the switched-capacitor resonator can be slightly tunedby adjusting the gain of Delay 2. In a digital implementation,the select signal would nominally be the MSB of the output of

Delay 1. However, to increase the speed of the switched-capaci-tor modulator, and decrease the possibility of metastability inthe switch control signal, the sign function is computed in paral-lel with the output of Delay 1 using a series of three latches.

Figure 20.4.3 shows the circuit implementation of the ai and bi

cells. If the exor output E to DAC ai is high, the DAC feeds backthe signal from quantizer C. When the exor output is low, theDAC is simply turned off, and a zero is fed back into the system.Effectively, this causes each ∆Σ modulator to have 1.5 bits. TheGilbert cell at the top of the DAC is used to adjust the gain, andhence the feedback coefficients, in the ∆Σ modulator. TheGilbert cell adds base-collector capacitances to the load at x. Forthis reason, the gain tuning is separated from this node andmoved into Delay 2. The linear transconductor bi uses voltagefeedback to the input transistors in order to reduce the depend-ence of the output on Vbe and Vce.

The chip was fabricated in HRL’s InP HBT G2 process [4]. Totest the performance of this 3b DAC shaper, a repeating 3b 6th-order bandpass ∆Σ-modulated pattern is fed in from a patterngenerator. Because a true ∆Σ-modulated pattern does notrepeat, the repeating pattern introduces a substantial amount ofnoise that limits the SNR to 78dB in a 1MHz BW. Additionally,the spectrum analyzer’s noise floor is 1-2dB below the signal’snoise floor. This is reflected in Fig. 20.4.4, which shows the out-put pattern into a spectrum analyzer, alongside the noise floor ofa 50Ω source. The SNR is > 68dB in a 1 MHz bandwidth up to750MHz, and is clearly measurement-limited. When the DACsare deliberately mismatched, as is shown in Fig. 20.4.5, theeffect of mismatch shaping becomes evident. With approximate-ly +/-10% current mismatches between the DAC elements, tun-ing the mismatch shaper improves the SNR improves the SNR10-20dB for frequencies between 250-750MHz.

The intermodulation is measured using two -6dBFS signals from200MHz to 800MHz. The resultant output spectrum at 750MHzIF is shown in Fig. 20.4.6. The 3rd harmonic is -62dBc when themismatch shaper is untuned, and is -84.3dBc when the mis-match shaper is tuned to 750MHz. The intermodulation for theuntuned shaper rapidly increases with increasing IF, from–72dBc to –61dBc. This suggests that dynamic errors are caus-ing intermodulation at higher IF’s. However, the intermodula-tion is consistently lower than –80dBc when the mismatchshaper is tuned. This shows that the DAC mismatch shaper canalso shape these dynamic errors. The SFDR is more than 74dBcin a 100MHz bandwidth in the same frequency range. The diephoto is shown in Fig. 20.4.7.

Acknowledgements:This work was supported by the Office of Naval Research under ContractNo. N00014-99-C-0144. The authors thank Al Cosand, Don Hitko,Mehran Mokhtari and Alireza Razzaghi for their valuable insight andadvice, as well as Doug McLaughlin for his help in testing the die.

References:[1] K. Vleugels, S. Rabii, and B. Wooley, “A 2.5-V Sigma-Delta Modulatorfor Broadband Communications Applications,” IEEE J. Solid-StateCircuits, vol. 36, no. 12, pp. 1887-1899, Dec. 2001.[2] I. Galton, “Spectral Shaping of Circuit Errors in Digital-to-AnalogConverters,” IEEE Trans. Circuits and Systems II, vol. 44, no. 10, pp. 808-817, Oct. 1997.[3] P. Vorenkamp et al., “Fully Bipolar, 130-Msample/s 10-b Track-and-Hold Circuit,” IEEE J. Solid-State Circuits, vol. 27, no. 7, pp. 988-992, Jul.1992.[4] M. Sokolich et al., “A Low-Power 72.8-GHz Static Frequency Divider inAlInAs/InGaAs HBT Technology,” IEEE J. Solid-State Circuits, vol. 36,no. 9, pp. 1328-1334, Sep. 2001.

• 2004 IEEE International Solid-State Circuits Conference 0-7803-8267-6/04 ©2004 IEEE

ISSCC 2004 / February 18, 2004 / Salon 8 / 10:15 AM

Figure 20.4.1: Architecture of mismatch-shaped DAC. Figure 20.4.2: Block diagram of individual router.

Figure 20.4.3: Schematics of ai and bi cells.

Figure 20.4.6: Measured intermodulation distortion.

Figure 20.4.4: Measured SNR vs. output frequency.

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Figure 20.4.5: Measured SNR improvement with +/-10% DAC mis-matches.

Figure 20.4.7: Die photo.

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• 2004 IEEE International Solid-State Circuits Conference 0-7803-8267-6/04 ©2004 IEEE

• 2004 IEEE International Solid-State Circuits Conference 0-7803-8267-6/04 ©2004 IEEE

Figure 20.4.1: Architecture of mismatch-shaped DAC.

• 2004 IEEE International Solid-State Circuits Conference 0-7803-8267-6/04 ©2004 IEEE

Figure 20.4.2: Block diagram of individual router.

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Figure 20.4.3: Schematics of ai and bi cells.

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• 2004 IEEE International Solid-State Circuits Conference 0-7803-8267-6/04 ©2004 IEEE

Figure 20.4.4: Measured SNR vs. output frequency.

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Figure 20.4.5: Measured SNR improvement with +/-10% DAC mismatches.

• 2004 IEEE International Solid-State Circuits Conference 0-7803-8267-6/04 ©2004 IEEE

Figure 20.4.6: Measured intermodulation distortion.

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Figure 20.4.7: Die photo.

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