13-1

A 0.98 to 6.6 Hz Tunable Wideband VCOI** . .,.

in a nmn Tec nology

for econfurae a Transceiver

Yusaku Ito, Hirotaka Sugawara, Kenichi Okada, and Kazuya Masu

Integrated Research Institute, Tokyo Institute of Technology4259-R2-17 Nagatsuta, Midori-ku, Yokohama 226-8503 Japan.

Tel: +81 -45-924-5031, Fax +81-45-924-5166, E-mail: paper@lsi.pi.titech.acjp

Abstract- This paper proposes a novel wideband voltage-controlled oscillator (VCO) for multi-band transceivers. The pro-posed VCO has a core VCO and a tuning-range extension circuit,which consists of switches, a mixer, dividers, and variable gaincombiners with a spurious rejection technique. The experimentalresults exhibit 0 98-to-6 6 GHz continuous frequency tuning with-206dBc/Hz of FoMT, which is fabricated by using a 0.18,pmCMOS process. The frequency tuning range (FTR) is 149 %,and the chip area is 800,pm x 540pm.

I. INTRODUCTION

Recently, dozens of wireless communication standards havebeen used for small mobile terminals, e.g. GSM, UMTS,WLAN, Bluetooth, GPS, DTV, and RFID, and the standardsuse several frequency bands spreading in a quite wide rangesuch as 800MHz to 6GHz The mobile terminals have beenobtaining multi-standard operations, smaller size, and lowerpower operation [1] However, the present multi-standardRF front-end consists of several LNAs, VCOs, Mixers, andPAs for each frequency band. A multi-standard RF front-endimplemented in a single chip is required for smaller size, lowerpower, and more flexible wireless communication terminalssuch as 800MHz to 6 GHz. The software defined radio (SDR)has been studied 12] [3] and the multi standard RF frontend is also needed to realize the SDR with feasible powerconsumption. Several multi-standard RF front-ends have beenproposed. Digital-assist architectures are suitable for Si CMOSchips As one of the multi-standard RF front-end we have pro-posed a reconfigurable RF circuit architecture [4], [5], whichaims to realize dynamic reconfiguration for multi functionsand self compensation of PVT with variable bias tuning andswitches as shown in Fig. 1. The digital radio processor (DRP)for Bluetooth and GSM/EDGE [6] and the software-definedradio receiver [3] have been reported, which are promisingas a multi-band down-converter. All of these RF front-endsrequire a wideband-tunable VCO, which is an indispensablecomponent for the multi-band radio. This paper proposes suchthe wideband VCO as 800MHz to 6 GHz.VCO using switched capacitors is a well-known topology to

extend the tuning range [7], [8], and a switched inductor anda variable active inductor are also utilized [9], [10]. However,these circuits have a trade-off between the phase noise and the

wide7tuning range wI sIo psn------oisePLL characterIstv ~~~~~~~~~~__iRReenwideabl AndVOoRrC Mrcui O U Digital Circuit

aandard tansiver [18] h DAC

oontro ircui

Fig I. Concept of the Reconfigurable RF circuit design.

tuning range. VCO using a variable MEMS inductor achieveswide-tuning range wathsuperhor phase nrose charactertstgcswit Ho eers it isdifficHlt for thesei re CMOS VCOs to

cosmpin Alhog VCO in Ref [1][8pseolun

obtain wide-tuning range with adequate phase noise.Recently widelband VCOs for MB-OFDM UWB [lL2]-[lL7]

anLd multi-standard transceiver [18] have lbeenL reported, whichuse a tuninlg-range extension technique using QVCO, dividersanldsngle-spdenangontexer perm).T nese vs Isachievequptewidetuninpg-ra nge aend high spurious rejection using SSBMwith I/Q signlals. Htowever, VCOs inl Ref. [12], L 3] usetWOOin anors at laveparge sayoul la a arger powerconsumption. Althouh VCOsTin Refp ari6t-c8useonlzoneaVCOi these VCOs alsohgae larter fhse noise andl reerpowi m laynsupio li lower

Various topologies for tuning-range extension can be uti-lized dependinlg on the required performnances. In this paper,we propose a nrovel extensioln architecture to achieve widertuning range with lower power, sraller layout area, and lowerphase noise, which achieves ±71% of tunring range from a±20 %-range core VCO. The proposed architecture utilizesa diflferenLtial VCO to genrerate the fundamental frequencywith smaller layout area, lower power consumption, and lowerphase-noise characteristics than quadrature VCOs. A varialblegain comlbiner is employed to reject spur instead of SSBM.

II. WIDEBAND VCO ARCHITECTURE

Fig. 2 shows the proposed VCO architecture, which consistsof a core VCO, two dividers, a switch, a mixer, a high-

0-7803-9735-5/06/$20.00 ©2006 IEEE 359

switch urrs to (B)gair B is controled to zero.

SVin VVariable GainSvi c- bier

Svout = ASvin , +BSvin 2

ASv i 1 A2BVSt0

100 1800111112f 3/2f 112fo 312fo

GoMMMbiner, Divider

~~ ~~~~~N3/2f9A 1/-2-]/fDiv

Fig. 4. Schematics of core VCO using switched capacitors.Bias Switch and Gain Control

Fig. 2. The proposed wideband VCO architecture.

2 fo3/2 fo

3/4 0:1/2 fo

.5 2 .25 3 .5 5 6 GHz

Vdd VdddVdd Vdd

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(a) wxideband mixer (b) variable gain combiner

1 to 6 GHz

Fig. 3. Frequency plan from 1 GHz to 6 GHz.

pass filter, and a combiner. The proposed architecture aims toachieve wider tuning-range with lower power and lower phasenoise, so a differential VCO and a novel compact frequency-extension circuit are introduced. Fig. 3 hows frequency planof the proposed architecture, and 2 fo, 3/2 fo, 3/4 fo, and 1/2 foare generated from the fundamental frequency fo of the coreVCO 2 Jo is generated by the mixer and 1/2 Jo is dividedfrom the fundamental frequency Jo 3/2 Jo is generated fromfo and 1/2 fo, and 1/2 fo is also generated as a spurious signal.3/4 Jo is divided from 3/2Jo The core VCO is required to havefrequency tuning range of ±20 %, and the total tuning range of±71 % can be realized by the frequency-extension circuit. Forexample tuning range of 2 3 GHz can be extended to 1 6 GHzas shown in Fig. 3.A differential VCO is employed as the core VCO. Fig. 4

shows the schematic of the core VCO, and switched capacitorsare utilized for coarse tuning. The differential VCO hasbetter phase-noise characteristic than the quadrature VCO, andsmaller layout area and lower power consumption can also beachieved. The core VCO has frequency tuning range of morethan ±20%. At higher frequencies, it is difficult to achievewide tuning range due to parasitic capacitances, so the lowerfundamental frequency is chosen and up-converted to higherfrequencies by the mixer.A CML divider is used as a wideband frequency divider to

obtain 1/2 of input frequency, and a wideband mixer shownin Fig. 5(a) is used as a frequency multiplier. The mixer is

Fig. 5. Circuit Schematics used in the proposed wideband VCO.

shared to generate 2 fo and 3/2 Jof and input signal of mixer is

switched as shown in Fig. 2. In the case (A) shown in Fig. 2,mixer input signals are fJ and 1/2fo, and 3/2fo and 1/2fo are

generated. In the case (B) shown in Fig. 2, both mixer inputsignals are Jo and DC and 2 o are generated

In the case (A), 3/2fo is desired frequency, and 1/2 Jo iSspurious frequeincy The tuning-range extension usiing SSBMrequires I/Q phases to reject the spurious frequency. In theproposed architecture, output of the first divider has the same

frequency as 1/2 fo of spur, and it can be used for thespurious rejection instead of the SSBM technique. Therefore,

the proposed architecture does not need QVCO and SSBMand small-size synthesizer can be realized. First, the spuriousfrequency is relected by the high pass filter shown in Fig 2Second, the remaining spur in the output of filter is rejectedby a variable gain combiner shown in Fig 5(b). The gainsof combiner are adjusted by bias voltages Gainl1 and Gain2.The high-pass filter is also used for phase adjustment, and thefilter should be carefully designed to reduce phase mismatchin wide frequency range.

In the case (B), 2 fo is desired frequency, and DC signal isspurious. The DC signal can be suppressed by the high-passfilter. In the proposed architecture, distance to spur is large,which is desirable feature for spurious rejection in both thecases (A) and (B). The proposed architecture is also expectedto be robust for LO leak,

III. MEASUREMENT RESULT

Fig. 6 shows a chip micrograph of the proposed widebandVCO, which is fabricated by using a 0.18jim CMOS process.

360

_n

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Fig. 6. Chip micrograph of fabricated wideband VCO. Core size is 540,mx 8000Pm.

Core size is 800,um x 540,rm. Depicted in Fig. 6, the corearea is dominated by the spiral inductor for LC-VCO. SignalSource Analyzer (Agilent E5052A) and Spectrum Analyzer(Agilent 8563EC) were used for measurement GSG probeswere also used to obtain on-chip signals. Fig. 7 shows the tun-ing characteristics of the VCO which exhibits from 0 98 GHzto 6.6 GHz oscillation. The tuning range is found to be 149 %Table I summarizes the measured results.

Fig. 8 shows spectrum of the combiner output, whichcontains 3/2 fo and 1/2 fo of frequency. In this case, 3/2 fois 2*93 GHz The spurious frequency of 1/2 Jo is rejected byboth the high-pass filter and the variable gain combiner. Thetotal image-reject-ratio (IMRR) is 20.2 dB.

Fig. 9 shows measured phase-noises characteristics for fo asthe fundamental frequency and 3/4 fo as the final output. The3/4 fo signal is generated through all the circuit blocks shownin Fig. 2. This result shows that the proposed wideband VCOoperate with the wideband and the low phase noise. Table IIsummarizes the measured phase noise and FoM The proposedVCO achieves -183 dBc/Hz of FoM for 2.50GHz oscillation.In this paper FoMT is also employed to evaluate tuning rangein addition to the phase noise [19] FoMT is defined as thefollowing equation.

F--L{foffst 20o fo FTR o PDC (1\ J oftset 10 / m

where L{foffset is phase noise, fofset is certain frequency offset,fo is center frequency, PDC is power consumption. FTR isfrequency tuaning range, which is defined as (fmax- fmin)/fOTable II also shows FoMT, and the proposed VCO achieves-206dBc/Hz of FoMT for 2.50GHz oscillation.

Fig. 10 plots performances of wideband LC-VCO reportedin literature [7]-[11], [17]-[23], which includes low phase-noise VCOs using SOI [19], [20] and BiCMOS processes [21],and CMOS VCOs using phase-noise improvement techniques[22], [23]. The proposed VCO achieves the widest tuningrange and the best FoMT simultaneously.

IV. CONCLUSION

This paper has proposed a novel wideband LC-VCO formulti-band applications. The VCO has the core VCO andthe tuning-range extension circuit. A differential LC-VCO and

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Fig 7 Measured tuning characteristics of the proposed VCO which exhibitsfronm 0.98GHz to 6.6G:lHz oscillation (149%).

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3/2f = 2 93 GHz

-35.5 dBm(l.36 V)Rejection 365 11 V)

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Fig 8 Spectrum of combiner output including 3/2 Jo and 1/2 f( frequenciesThe spurious rejection is performed by the high-pass filter and the variablegain combiner.

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Fig. 9. Phase noise at f (2.50GHz) and 3/4fo(1.85GHz).

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TABLE I

VCO PERFORMANCE SUMMARY.

Technology TSMC 0.18pm CMOS processwith RF option

Supply voltage VII 1.8 VVCO core current 2.45 14.9 mAPower consumption 441 26.9 mWCenter frequenc 81 6HzTuning range 0.98GHz 6.64 GHz

149%Chip area 800m x540gm

TABLE 11

PHASE NOISE PERFORM[ANCES

Oscillation Phase noise FoM FoMTrfrequency @1 MHz offset

2.50 GHz (fg) -125 dBc/Hz -18 dBc/Hz -206 dBc/Hz1.856GHz (3/4Jf,,) -l128 dBc/Hz - l80 dBc/Hz 203dBcHz

I

11

0U-

80

Fig. 10. VCO performance comparison using FoM and frequency tuningrange (FTR) [7]_[I1], [17]r 23].

a double-balanced mixer are utilized instead of a quadratureVCO and a single-sideband mixer for the spurious rejection.In measurement results, the proposed VCO performs 0.98-to-6.6 GHz continuous frequency tuning with -206 dBc/Hz ofFOM1T, which is fabricated by using a 0. 18pm CMOS process.The frequency tuning range (FTR) is 149 %c and the chip areais 800pm x 540pm. The proposed VCO achieves the widesttuning range and the best FoMT.

ACKNOWLEDGMENT

This work was partially supported by JSPS.KAKENHI,STARC, MIC.SCOPE, and VDEC in collaboration with Ca-dence Design Systems, Inc.

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