A 21.2 μA -Based Interface ASIC for aCapacitive 3-Axis Micro-Accelerometer

Matti Paavola , Mika Kämäräinen , Erkka Laulainen , Mikko Saukoski , , Lauri Koskinen ,Marko Kosunen , and Kari Halonen

SMARAD-2/Electronic Circuit Design Laboratory, Helsinki University of Technology, Espoo, FinlandEmail: mhpaavol@ecdl.tkk.fi

Abstract—In this paper, a micropower interface IC for acapacitive 3-axis micro-accelerometer implemented in a 0.25 -μmCMOS process is presented. The fully-integrated sensor interfaceconsists of a sensor front-end that converts the accelerationsignal into the digital domain, a decimator, a frequency reference,a clock generator for the front-end, a voltage and currentreference, the required reference buffers, and low-dropout reg-ulators (LDOs) needed for system-on-chip power management.The interface IC provides operating modes for 1 and 25Hzsignal bandwidths. The chip with a 1.72mm2 active area draws21.2 μA in 1Hz mode, and 97.6 μA in 25Hz mode, from a1.2 2.75V supply. In 1Hz mode with a 2 -g capacitive 3-axis accelerometer, the measured noise floors in the x-, y-, andz-directions are 1080, 1165 and 930 μg/ Hz, respectively.

I. INTRODUCTION

Micro-accelerometers have a wide range of different appli-cations, such as automotive safety and stability control sys-tems, navigation, and movement detection and user interfacesin hand-held mobile terminals and in game controllers. Theuse of microsensors in battery-powered equipment requiresthe sensor interface to exhibit low power dissipation andto be able to operate from supply voltages varying over awide range. In order to realize a low-power, high-performanceaccelerometer with a small silicon area, the readout electronicshas to be integrated together with the sensor element at chipor packaging level, forming a microelectromechanical system(MEMS).

The advantages of capacitive accelerometers [1], such aszero static bias current, the capability of achieving high sensi-tivity, and excellent thermal stability, are emphasized in ultra-low-power applications. In this paper, a fully-integrated low-voltage low-power sensor interface IC for a capacitive 3-axismicro-accelerometer will be presented. The system is based onthe front-end circuit presented earlier by the authors in [2], andincludes additionally a decimator, all the required referencecircuits, and on-chip power management circuitry. The 2nd-order sensor front-end operates in open-loop configurationand performs inherent capacitance-to-digital conversion andcharge balancing. The reasons for using an open-loop configu-ration are simple implementation that reduces both silicon areaand power dissipation, and a limited voltage range availablefor electrostatic feedback.

The authors wish to thank VTI Technologies and the Finnish FundingAgency for Technology and Innovation (TEKES) for financial support.

2Starting from the year 2008, M. Saukoski has been with ELMOS Semi-conductor AG, Dortmund, Germany.

V/IREF

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DECIMATOR

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Fig. 1. Block diagram of the implemented interface IC for a capacitive 3-axismicro-accelerometer.

To make an operation over wide range of supply voltages( . . V ) required by the battery-powered system pos-sible, low-dropout regulators (LDOs) were implemented forsystem-on-chip power management. LDOs have significantadvantages, such as fast transient response, low-noise char-acteristic, low complexity, and no need for inductors. Theimplemented sensor interface provides operating modes forand Hz signal bandwidths. The former makes it possible todetect accelerations while maintaining low power dissipation,and the latter can be used to measure accelerations over awider bandwidth.

The paper is organized as follows. The system architectureof the implemented sensor interface is briefly described inSection II. Different circuit blocks are presented in SectionIII and the measurement results of the implemented prototypeare presented in Section IV. Finally, conclusions are drawn inSection V.

II. SYSTEM DESCRIPTION

A block diagram of the implemented sensor interface systemis shown in Fig. 1. The -type sensor front-end [2] convertsthe capacitive acceleration information from each of the threeproof masses first to charge and then subsequently to a bitstream. The decimator, based on the implementation presentedin [3], filters and decimates the single-bit outputs to thefinal desired bandwidth and accuracy. The frequency referencecircuit (FREF) [4] provides the master clock signal for boththe clock generator of the front-end (CLKG) and for thedecimator. The CLKG then generates all the clock signalsrequired by the front-end.

The voltage and current reference circuit (V/IREF) providesthe main reference voltage and current, together with the biasvoltages and currents required by the other circuit blocks. The

101978-1-4244-2605-8/08/$25.00 ©2008 IEEE

IEEE Asian Solid-State Circuits ConferenceNovember 3-5, 2008 / Fukuoka, Japan

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Fig. 2. Schematic of the sensor front-end with an SEM photograph of a capacitive 3-axis micro-accelerometer. (SEM image courtesy of VTI Technologies,Vantaa, Finland).

reference voltage buffers (REFBUFs) are used to scale andbuffer the reference voltage, and they provide the positive ref-erence (REFP) and the common-mode output (CM_OUT) andinput (CM_IN) voltages required by the front-end circuit. Twoseparate buffers were designed to optimize power dissipationin both and Hz operating modes.

Two LDOs were implemented to provide separate . Vregulated supply voltages for the sensor front-end and forthe FREF and the CLKG. Additionally, the decimator had to beprovided with an LDO of its own with programmable outputvoltage from . to . V , as the standard cell library usedin the design was specified only for supply voltages down to. V . To avoid the use of impractical off-chip load capacitors

and to guarantee the maximum tolerable output voltage dropof . V , the LDOs were equipped with programmable on-chip load capacitors up to nF . Because of the low-powercharacteristic of the sensor interface, the LDOs must remainstable with zero load currents.

In order to reach a sufficient (> dB) mechanical attenu-ation of folding out-of-band interferers and low enough noiselevel for 12-bit resolution for a -g dc acceleration signal in

Hz mode, a sampling frequency of . kHz per mass waschosen. With a full-scale input signal, the maximum signal-to-noise ratio of the sensor front-end would then be limited bythermal noise to 16 bits. However, the limited signal availablefrom the -g accelerometer limits the achievable dynamicrange to 12 bits. In the Hz mode, a sampling frequencyof . kHz is required for the same resolution. The 16-bitaccuracy is demanded also from the reference buffers. This hasan adverse effect on the current consumption of the REFBUFs.

The attenuation of the used sinc3 decimation filters is notallowed to be greater than dB at the edge of the passband.Thus, the output data rate of the decimator was chosen tobe and Hz in the and Hz modes, respectively.Because of the absence of analog gain control before theA/D conversion, the decimator is equipped with shifters forgain control and 16-bit wide serial outputs to maintain theresolution even at the presence of uncompensated offsets.

III. CIRCUIT DESCRIPTION

A. Sensor Front-End

The schematic of the sensor front-end with the sensorelement is shown in Fig. 2. The front-end balances charge,

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Fig. 3. Simplified block diagram of the decimator.

in other words it ensures an equal average charge in bothpositive and negative detection capacitances, and thus reducesthe distorting effects of the nonlinear electrostatic forces. Theresulting transfer function from acceleration to bit stream isof the form CDP CDN / CDP CDN , which cancelsthe nonlinearity of the displacement-to-capacitance transducerto the first order. Chopper stabilization (CS) and correlateddouble sampling (CDS) are implemented in order to reducethe offset voltage and noise of the front-end.

The operation principle of the front-end is described indetail in [2]. The positive and negative reference voltages areequal to the supply and ground. Because of the low supplyvoltage of . V , the input and output common-mode levelsof the operational amplifiers are separated to . and . V ,respectively. To minimize power dissipation, a tail-current-boosted Class-AB operational amplifier [5] with enhanced dcgain [2] is used in the 1st integrator. The operational amplifierused in the 2nd integrators is a basic current mirror OTA,whose dc gain is enhanced with the same technique. Thesimulated dc gains of the two amplifiers are approximately

and dB, respectively. A dynamic latch with zero staticpower dissipation is used as a comparator.

The programmable capacitor matrix CCB can be used tosink charge from the sensor middle electrode DMID. It makespossible both boosting the available signal and compensatingthe offsets of the sensor capacitors [2]. Because of the lowsupply voltage, the gate voltage of an NMOS device in afloating transmission gate is increased to VDD using chargepumps [2]. The symbol 2x is used to indicate the gate-voltage-boosted switches in Fig. 2. As the node DMID isespecially sensitive to leakage currents, a special ultra-low-leakage switch [2] denoted by ULL in Fig. 2 was developed.

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Fig. 4. Schematics of: (a) a frequency reference; (b) a voltage and current reference; (c) a reference voltage buffer, and (d) an LDO.

B. Decimator

The simplified block diagram of the designed decimatorbased on three parallel sinc3 filters [3], one for each proofmass, is shown in Fig. 3. Three-stage cascaded integrator-comb (CIC) filters with one sample delays and selectablerate change factor are used. Each of the filters has two 1-bit inputs and a 16-bit wide output. When CS is not used,the filters use only one input. In the case of CS enabled, thedemodulation is performed by subtracting the two input bits.After possible demodulations the signals can be scaled withshifters. The decimation ratio can be selected between 16 and512, with each control step doubling the ratio. The outputsfrom the three filters are fed to a parallel-to-serial converterthat outputs the 48 ( ) bits. Based on the measurementresults [3], the decimator operates nominally from a . Vsupply in Hz mode, and from a . V supply in Hz mode.The decimation ratios used are 512 and 256, respectively.

C. Reference Circuits and LDOs

The master clock frequency is . kHz in Hz modeand . kHz in Hz mode. The frequency reference thatprovides the master clock signal and which consists of twoparallel source-coupled CMOS multivibrator-based structuresis shown in Fig. 4 (a) [4]. Both modes require an independentfrequency reference circuit because, due to the low supply volt-age of . V , floating switches cannot be used, and therefore asufficient frequency tuning range cannot be achieved by usingcapacitor matrices. Coarse tuning is implemented by usingPMOS transistor matrices in the biasing circuits and in themultivibrators, while fine tuning is implemented with resistormatrix Rm (matrices marked with dashed boxes in Fig. 4).The devices Rm, MS, and Cs are common for the two fre-quency references. The used biasing circuits are proportional-to-absolute-temperature (PTAT) current generators. Two-stagedifferential comparators are used to magnify the oscillationamplitudes rail-to-rail, and tri-state buffers are used to interfacethe parallel frequency references to the divider consisting oftwo cascaded gated SR latches. The divide-by-two operation

is enabled when CS is disabled.The designed V/IREF shown in Fig. 4 (b) is based on

the bandgap reference topology presented in [6], and it issuitable to be implemented with a standard CMOS process. AMiller-compensated operational amplifier with a PMOS inputpair is used as the feedback amplifier. To allow the use ofsupply voltages down to . V , the input voltage levels ofthe operational amplifier are lowered with resistive voltagedividers. The effects of process variations on the output voltagelevel (VREF nominally . V ) can be eliminated by trimmingR1. To achieve a sufficient noise performance, the bandwidthof the bandgap reference is limited aggressively by usingthe compensation capacitor Cc of pF . As a result, thebandwidths of the negative feedback loop and the closed loopare nominally . and . kHz, respectively. The NMOSswitches S1 and S2 were included to provide a power-on-resetthat can be used to force the bandgap reference to the rightoperating point, if needed. Programmable biasing currentsIBIAS1 and IBIAS2 are used to bias the amplifiers of the

sensor front-end.The two REFBUFs have identical schematics shown in

Fig. 4 (c), but different device parameters. Time constantsformed by the resistances of the resistive networks and theload capacitances from the front-end and the sensor elementdetermine the settling accuracies.

The LDO shown in Fig. 4 (d) is based on the structurepresented in [7]. It uses a Q-reduction technique to minimizeboth the required on-chip capacitance and the minimum outputcurrent. Nominally, the current of . μA flows through thefeedback resistive network. The requirement for stability atzero load current (RL ) results in a small bandwidth of

. kHz for the loop response. To minimize the silicon arearequired by the programmable nF load capacitors metal-insulator-metal (MIM) capacitors were stacked above standardMOS capacitors.

IV. MEASUREMENT RESULTS

The prototype chip with a . mm active core area shownin Fig. 5 was fabricated in a . -μm CMOS technology.

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TABLE ISUMMARY OF MEASURED PERFORMANCE.

Process . -μm CMOS with MIM capacitors and high-resistivity polysilicon resistors

Supply . . VTwo . V and one . . V regulated on chip

Configuration With CS and CDSWithout signal boosting and offset compensation

Active area . mm2

Mode 1Hz 25Hzfs per mass 4.096 51.2 kHzCurrent consumptionILDO1

a 14.5 84.3 μAILDO2

b 3.5 5.2 μAILDO3

c 3.2 8.1 μATotal 21.2 97.6 μANoise floorx-axis 1080 340 μg/ Hz

y-axis 1165 325 μg/ Hz

z-axis 930 275 μg/ Hz

aLDO1, V/IREF, REFBUFs, and sensor front-endbLDO2, FREF, and CLKGcLDO3 and decimator

For the measurements, the chip was encapsulated into aplastic quad flat package (QFP) with 64 pins and solderedonto a printed circuit board (PCB). The chip was combinedwith an external -g capacitive 3-axis accelerometer on thePCB. The results presented below were measured for thecomplete system shown in Fig. 1, while the prior results ofthe sensor front-end published in [2] were obtained usingboth off-chip decimator, and off-chip references and powermanagement.

The performance measured for both modes using a . Vsupply voltage and . nF load capacitors at the outputs ofthe LDOs is summarized in Table I. All the results weremeasured by using both CS and CDS, but without using signalboosting or offset compensation. The core circuit consumes

. μA in Hz mode and . μA in Hz mode. The noiseresults yield dynamic ranges of and dB for dc inputsignals in and Hz modes, respectively. FFTs measuredfrom the output of the sensor front-end, for the x-directionaldata in Hz mode and the z-directional data in Hz mode,are shown in Figs. 6 (a)-(b). The root Allan variance forthe y-directional data and the -g acceleration ramps, bothmeasured from the decimator output in Hz mode, are shownin Figs. 6 (c)-(d). The ramps were measured using a rotating

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Nonlinearity(% from full−scale range)x: +0.72 / −0.66%y: +0.28 / −0.19%z: +0.94 / −0.79%

Fig. 6. FFTs of measured (a) x-directional data in Hz mode and (b) z-directional data in Hz mode, and measured (c) root Allan variance fory-directional data and (d) -g acceleration ramps in Hz mode.

rate table. The results are expected to improve when theinterface IC is bonded directly to the sensor.

V. CONCLUSION

In this paper, a micropower -based interface IC fora capacitive 3-axis micro-accelerometer implemented in a. -μm CMOS process was presented. In Hz mode, the

chip with a . mm active area draws . μA from a. . V supply while sampling three proof masses, each

at . kHz. With a -g capacitive 3-axis accelerometer,the measured noise floors in the x-, y-, and z-directions are

, and μg/ Hz, respectively. Compared to theopen-loop sensor interface of [1] which includes separatecapacitance-to-voltage and voltage-to-digital conversions, thepresented measurement results prove that by using both open-loop configuration and inherent capacitance-to-digital conver-sion, an alternative low-voltage low-power sensor interface canbe implemented.

REFERENCES

[1] M. Paavola, M. Kämäräinen, J. Järvinen, M. Saukoski, M. Laiho, andK. Halonen, “A micropower interface ASIC for a capacitive 3-axis micro-accelerometer,” IEEE J. Solid-State Circuits, vol. 42, no. 12, pp. 2651–2665, Dec. 2007.

[2] M. Kämäräinen, M. Paavola, E. Laulainen, M. Saukoski, L. Koskinen,M. Kosunen, and K. Halonen, “A 1.5μW 1V 2nd-order sensor front-end with signal boosting and offset compensation for a capacitive 3-axismicro-accelerometer,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech.Papers, San Francisco, CA, USA, Feb. 2008, pp. 578–579.

[3] E. Laulainen, M. Kosunen, L. Koskinen, M. Paavola, and K. Halonen,“Decimation filter for a low-power sensor-interface system,” in Proc.IEEE Norchip Conf., Aalborg, Denmark, Nov. 2007.

[4] M. Paavola, M. Saukoski, M. Laiho, and K. Halonen, “A nanopowerdouble-mode 1-V frequency reference for an ultra-low-power capacitivesensor interface,” in Proc. IEEE Eur. Conf. Circuit Theory and Design,Sevilla, Spain, Aug. 2007, pp. 104–107.

[5] R. Harjani, R. Heineke, and F. Wang, “An integrated low-voltage class ABCMOS OTA,” IEEE J. Solid-State Circuits, vol. 34, no. 2, pp. 134–142,Feb. 1999.

[6] K. N. Leung and P. K. T. Mok, “A sub-1-V 15-ppm/oC CMOS bandgapvoltage reference without requiring low threshold voltage device,” IEEEJ. Solid-State Circuits, vol. 37, no. 4, pp. 526–530, Apr. 2002.

[7] S. K. Lau, P. K. T. Mok, and K. N. Leung, “A low-dropout regulator forSoC with Q-reduction,” IEEE J. Solid-State Circuits, vol. 42, no. 3, pp.658–664, Mar. 2007.

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