Ultrafine-Pitch C2 Flip Chip Interconnections with Solder-Capped Cu Pillar Bumps

Yasumitsu Orii*, Kazushige Toriyama, Hirokazu Noma, Yukifumi Oyama, Hidetoshi Nishiwaki, Mitsuya Ishida, Toshihiko Nishio

IBM Microelectronics Japan, 338, Enpukuji-cho, Muromachi-dori, Nakagyo-ku, Kyoto-city, 604-8175, Japan *Email : orii@jp.ibm.com

Nancy C.LaBianca, Claudius Feger

IBM T. J. Watson Research Center, 1101 Kitchawan Road, Yorktown Heights, New York 10598, U.S.A.

Abstract PoP structures have been used widely in digital consumer

electronics products such as digital still cameras and mobile phones. However, the final stack height from the top to the bottom package for these structures is higher than that of the current stacked die packages. To reduce the height of the package, a flip chip technology is used. Since the logic chips of mobile applications use a pad pitch of less than 80 μm or less, an ultra-fine-pitch flip chip interconnection technique is required. C4 flip chip technology is widely used in area array flip chip packages, but it is not suitable in the ultrafine-pitch flip chips because the C4 solder bumps melt and collapse on the wide opening Cu pads. Although the industry uses ultrafine-pitch interconnections between Au stud bumps on a chip and Sn/Ag pre-solder on a carrier, this flip chip technique has two major problems. One is that the need for bumps on both die and carrier drives up material costs. The other is that the long bonding process time required in the individual flip chip bonding process with associated heating and cooling steps demands large investments in equipment. To address these problems, we developed the mount and reflow with no-clean flux processes, and new interconnection techniques were developed with Cu pillars and Sn/Ag solder bumps on Al pads for wirebonding, were developed. It is very easy to control the gap between die and substrate by adjusting the Cu pillar height. Since it is unnecessary to control the collapse of the solder bumps, we call this the C2 process for direct Chip Connection (C2). The C2 bumps are connected to Cu substrate pads, which are a surface treated with OSP (Organic Solder Preservative), with reflow and no-clean processes. This technology creates the SMT/Flip Chip hybrid assembly for SoP (System on Package) use. We have produced 50 μm-pitch C2 interconnections and tested their reliability. The interconnection resistance increase caused by the reliability testing is quite small. It is clear that C2 flip chip technology provides robust solder connections at low cost. Also the C2 structure with a low-k device was evaluated and no failures were observed at 1,500 cycles in the thermal cycle test. This indicates that low-k C2 structures seem robust. For finer pitch flip chip interconnections, a wafer-level underfill process is needed to overcome the limitations of the standard capillary underfill process for ultra-narrow spaces. To date, a wafer- level underfill process exists for the C2 process with an 80-μm pitch. In addition to fine pitch interconnections, a die thickness of 70 μm is required to reduce the final stack height. Such thin die cannot be processed by the C2 process because such dies slip too easily during the reflow process. To resolve this issue, a Post-Encapsulation Grinding (PEG)

method was developed. In this method the die is ground to less than 70 μm after joining and underfilling. This report presents the PEG method and reliability test results for die thicknesses 20 μm, 70 μm and 150 μm.

Introduction PoP (Package on Package) [1] is an emerging technology

intended to replace the wire-bonding stacked die technology [2], now used in digital consumer electronics products such as digital still cameras and mobile phones. A disadvantage of PoP is that the final stack up height from the top to bottom of the packages is greater than with stacked die packages. To address this problem, Flip Chip PoP, in which flip chip technology is used for the bottom package, is increasingly popular. Since the die of the bottom package in PoP is designed for wirebonding technology, the I/O pads are located on the periphery with a very fine pitch, such as 80 μm or less.

Many kinds of flip chip interconnection are available in the industry, but there are only a few technologies for ultrafine-pitch flip chips on organic substrates. The technology widely used in Japan for digital still cameras and mobile phones is Au stud bumps to solder interconnections [3]. However, there are three problems in the Au Stud bump to solder interconnection. One is that pre-solder is required on an organic substrates. Sn/Ag solder is pre-formed on the Cu pads of the substrates. This increases costs and the solder height varies depending on the Cu pad width. The second is that the bonding process time is long to allow for the individual thermal compression bonding. This means lots of expensive equipment investment is required. The third is the narrow process margin due to the creation of complicated intermetallic, which increases the interconnection resistance. These problems inhibit the expanded use of flip chip infrastructures. A new technology is needed to extend the standard C4 technology that IBM introduced in the early 1960s for its SLT (Solid Logic Technology). This C4 technology is still widely used for CPUs in PCs and games. The standard C4 technology is normally used with bumps having pitches greater than 150 μm, and can’t be used at pitches of 80 μm pitch or less because of the underfill difficulty due to the small gap and solder shorts.

At fine pitches the gap between the die and the substrate becomes too small. Fig. 1 shows a solder resist opening for flip chip pads. The individual window design helps control the collapse of the solder bumps during reflow, but this design cannot be used for fine pitches of 80 μm or less because of alignment limitations in PCB (Printed Circuit Board) manufacturing. Since the slit window design in a PCB

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must be used for fine-pitch flip chip interconnections, it is very difficult to control the collapse of the standard C4 solder bumps. As the space between bumps narrows, the possibility of solder shorts increases. To address these problems we developed, a new interconnection method, C2 (Chip Connection) [4, 5]. Fig. 2 shows a C2 bump structure. This structure is based on electroplating the Cu pillar bumps and Sn/2.5Ag solder. The bump processing cleans the Al pads with back-sputtering and sputtering of a plating base of Ti and Cu as the UBM (Under Bump Metal). The photoresist is applied, exposed, and developed. Next, Cu is electroplated, followed by Sn/Ag solder electroplating, and then the photo-resist is removed. Finally the plated base is selectively removed. The Cu pillars do not melt during reflow, so the gap between the die and the substrate is maintained. This structure solves the problems and allows us to implement interconnections with ultrafine pitches of 80 μm or less. The C2 process with Cu pillars needs less control to avoid collapse in comparison with the C4 process so that the C2 is suitable for ultrafine-pitch flip chip interconnections. The process flow is very simple. First, a special flux that does not need to be cleaned away afterwards is applied to the die or the substrate. Then the die with the Solder-Capped Cu pillar bumps is aligned with the substrate, and the solder joints are all formed simultaneously using reflow, similar to the standard C4 and SMT process. This means that the flip chip

die and SMT component joints are formed in a single reflow step. After a flip chip bonding, a flux cleaning process is not required. And then underfill is applied by capillary action. No additional pre-soldering of the substrate is required and the process is SMT compatible, so this C2 approach is less expensive than existing methods. The process time is less than 2 seconds, which is for the alignment and mounting. This is much shorter than for Au stud bump to solder method and reduces the equipment costs. Table 1 shows the pros and cons of each process, the C2 and Au stud to solder interconnection.

Results and Discussion

1. C2 for 50 μm pitch Flip Chip Interconnection 1-1. Reliability Test Results with Non low-k devices

The TEG (Test Element Group) carriers for the evaluation are 20-mm square size and 310 μm thickness (4 layers of laminated prepreg). A flip chip can be mounted in the center, and PoP pads (0.5 mm pitch) are located around a flip chip. There are two types of TEG carriers, one type for TC (Thermal Cycle) tests, and another type for for THB (Thermal Humidity Bias) tests. There are also two types of TEG chips with 80-μm or 50-μm pitches. The numbers of bumps are 328 and 544, respectively and both dies are 7.3 x 7.3 mm. The die has one Al metal and SiO/SiN passivation and PI coated with non low-k insulator. A series of reliability test conditions are shown in Table 2. Before performing these tests, pre-conditioning tests for JEDEC Level-3 were performed (125°C bake for 24 hours, 30°C at 60%RH for 192hours, and 3 times at 260°C peak reflow). First, all of the tests were done with

Individual Window

Slit Window

Area Array Type

Peripheral Type(fine pitch)

Sn/Ag Solder

Individual Window

Slit Window

Area Array Type

Peripheral Type(fine pitch)

Sn/Ag Solder

Fig. 1 : Solder Resist opening designs for flip chip pads

SiO2

Si Wafer

PI

Cu Post

Sn/Ag

Al

UBM

PassivationSiO2

Si Wafer

PI

Cu Post

Sn/Ag

Al

UBM

Passivation

Fig. 2 : C2 Bump Structure

Table 1 : Comparison of Fine-Pitch Flip Chip Interconnections

Thermal Compression Bonding: more than 15 sec

(Individual Bonding)

Mount : less than 2 sec(Mass Reflow)

Productivity

Non necessity of Wafer Bump ProcessDiced Chip can be handled.

Wafer Level OperationOne time reflow for Flip Chip & SMD

Less capital investmentLow Resistance Interconnection

High Reliability

Features

Flip Chip BondingMount & ReflowFlip Chip

Interconnection Method

Required(Sn/3.5Ag Solder)NonePre-solder on Carrier

Au Stud BumpSn-2.5Ag Solder Capped Cu Pillar

By Wafer PlatingBump on Die

Au Stud – Pre solderC2 Bump

Thermal Compression Bonding: more than 15 sec

(Individual Bonding)

Mount : less than 2 sec(Mass Reflow)

Productivity

Non necessity of Wafer Bump ProcessDiced Chip can be handled.

Wafer Level OperationOne time reflow for Flip Chip & SMD

Less capital investmentLow Resistance Interconnection

High Reliability

Features

Flip Chip BondingMount & ReflowFlip Chip

Interconnection Method

Required(Sn/3.5Ag Solder)NonePre-solder on Carrier

Au Stud BumpSn-2.5Ag Solder Capped Cu Pillar

By Wafer PlatingBump on Die

Au Stud – Pre solderC2 Bump

Au Stud Bump - Solder 50um pitch interconnectionTC -40'C/115'C,2cph

100 1000 10000

Cycles : t

Cum

Fai

l Rat

io F

(t)

: %

0.001

99.999

50403020

10

5

10.5

0.1

0.01

607080

9095

9999.5

99.9

99.99

Log-Normal

Median Rank Method

Al pad

Au Stud Bump

Sn-3.5Ag solder

Cu pad

Au stud bump – Solder Interconnection

Au Stud Bump - Solder 50um pitch interconnectionTC -40'C/115'C,2cph

100 1000 10000

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Al pad

Au Stud Bump

Sn-3.5Ag solder

Cu pad

Au stud bump – Solder Interconnection

Al pad

Au Stud Bump

Sn-3.5Ag solder

Cu pad

Au stud bump – Solder Interconnection

Fig. 3 : Lognormal Plot of Au Stud-solder Interconnection

Table 2 : C2 Reliability Test Results Lot-1 Lot-2 Lot-3

TC -40/+115℃, 2cph0/10 NG

@2,250 cyc0/10 NG

@2,500 cyc0/20 NG

@2,500 cyc

THB 85℃/85%RF/5.5V0/25 NG

@1,500 hr0/10 NG

@1,500 hr0/20 NG

@1,500 hr

HTS 150℃0/5 NG

@1,500 hr0/25 NG

@1,500 hr

TC -40/+115℃, 2cph0/10 NG

@2,000 cyc0/15 NG

@2,250 cyc0/50 NG

@2,500 cyc

THB 85℃/85%RF/3.7V0/10 NG

@1,500 hr0/15 NG

@1,500 hr0/50 NG

@1,500 hr

HTS 150℃0/10 NG

@1,000 hr0/15 NG

@1,500 hr0/35 NG

@1,500 hr

80 μmpitch

50 μmpitch

Test Condition

949 2009 Electronic Components and Technology Conference

the samples of a bare die with a thickness of 725 μm (with no back grinding) is mounted on the one side. Later we will discuss the reliability test with ultrathin die. All of the C2 samples passed TC for 2,500 cycles, THB for 1,500 hours and HTC for 1,500 hours, as shown in Table 2 and none of the samples were visually abnormal, such as showing cracked dies or cracked underfills. We also compared the performance during the very long thermal cycle test between C2 and the Au stud to solder. No failures of the C2 interconnections were confirmed until 4,000 cycles of TC (-55/+125°C, 2 CPH), when that test was stopped. However, the Au stud-solder (Sn-3.5Ag) technology started to fail at 1,250 cycles of TC (-40/+115°C, 2 CPH) and many failures were confirmed until 5,000 cycles as shown in the lognormal plot (Fig. 3). Most of

the failures were cracks at the boundaries between Au and Sn-3.5Ag solder. For a more detailed analysis, the ratio of resistance increase after TC and HTS reliability testing was carefully monitored. The ratio of resistance increase for the C2 interconnection was quite stable at less than 2% after the reliability tests, which is much better than for Au stud-solder interconnections, as shown in Fig. 4. For the Au stud-solder interconnections, many complicated intermetallic layers were found and they increased the resistance. Especially in HTS test, many kirkendall voids were observed at the boundary between Al and Au as shown in Fig.5. In contrast, the robust solder joint in the C2 structure was confirmed with 2,000 hours in a high temperature (150°C) storage test (Fig. 5). The C2 flip chip technology provides very robust low-cost solder connections.

1-2. Reliability Test Results with low-k devices

As CMOS devices shrink, low-k dielectric materials are being used to reduce RC delay. However, mechanically such dielectric materials have lower modulus values, and are brittle with lower adhesion. The combined effects of large die size, finer bump pitch, Pb free solder-capped Cu pillar structures on low-k die are expected to be more challenging, and hence it is imperative to study the chip-package interaction more closely to improve the overall robustness of low-k packages. In this section, a C2 structure was evaluated for a low-k device. The low-k device test die is 6.1 x 6.1 mm with C2 bumps. Each C2 bump consists of a Cu pillar (25 μm height) and Sn-2.5Ag solder (20 μm height) with 560 staggered bumps in a 60-μm pitch peripheral layout. The TEG carrier for the evaluation is 12.8 x 12.8 mm and 330 μm thickness (4 layers of laminated prepreg). JEDEC Level-3 pre-conditioning(125°C bake for 24 hours, 30°C at 60%RH for 192 hours, and 3 times at 260°C peak reflow) and TC testing (-55°C to +125°C, 2 CPH) were performed. No failures were observed at 1,500 cycles and a cross section at 1,000 cycles is shown in Fig.6. This indicates that low-k C2 structures seem robust for die sizes of 6 mm or less. Our next tests will evaluate C2 bump structures on a larger die.

2. PEG for Ultrathin-Die Flip Chip Interconnection 2-1. Current Ultrathin-Die Flip Chip Technology

Improved wafer thinning is making semiconductor packages thinner. In recent years, the use of wafer back side grinding process and better WSS (Wafer Support Systems) have thinned the wafers for semiconductor packages to 100

-5%

0%

5%

10%

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20%

Initial AfterPrecon

250 500 750 1000 1250 1500 1750 2000 2250 2500

Cycles

Res

ista

nce

Incr

ease

Rat

io(%

)

Au Stud-Solder

C2

Thermal Cycle(80um pitch) -40℃~+115℃,2cph

-5%

0%

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Initial AfterPrecon

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ease

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io(%

)

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C2

Thermal Cycle(80um pitch) -40℃~+115℃,2cph

-10%

0%

10%

20%

30%

40%

50%

60%

70%

Initial AfterPrecon

250 500 750 1000 1250 1500 1750 2000 2250 2500

Time

High Temp Storage(80um pitch) + 150℃

C2

Au Stud-Solder

Res

ista

nce

Incr

ease

Rat

io(%

)

Fig. 4 : Reliability Data Comparison

Au Stud to Solder Sample@1,750 hours

Cu

Cu

Solder

HTS 150℃@2,000hrs

Organic Substrate

Cu6Sn5 ()

Cu3Sn ()

C2 Sample@Time-0

Cu

Cu

Solder

HTS 150℃@2,000hrs

Organic Substrate

Cu6Sn5 ()

Cu3Sn ()

C2 Sample@Time-0

Fig. 5 : Au Stud to Solder/C2 HTS Results

Fig. 6 : 60um-pitch C2 Flip Chip interconnection with low-k device

950 2009 Electronic Components and Technology Conference

μm or less. The main problem of thin wafers is brittleness. To reduce the breakage of silicon wafers, the various stress relief methods can be used, such as dry polish, plasma treatment, and CMP (Chemical Mechanical Polishing). Stress relief and a WSS are needed for any ultrathin-die flip chip technology. However, very thin die are fragile and easily cracked. To avoid broken die, our method is to grind the die after the flip chip bonding, as shown in Fig. 7. This is the PEG (Post Encapsulation Grinding) method [6], which was developed for ultrathin-die flip chip assembly.

2-2. PEG technology

PEG involves grinding the bare die bonded to an organic substrate with underfill. This reduces the number of dies cracked in handling. In addition, no backside grinding of the wafers are needed. The flip chip assembled modules with underfill are fixed on a tape that is used for back side grinding as shown in Fig. 8. and Fig. 9 shows 90 modules attached to a tape. The tape is placed on the platform of the grinding machine in a vacuum, and then thinned. Stress relief is used as needed, using the techniques mentioned earlier. Then the modules are detached from the tape. Table 3 shows the silicon thicknesses after PEG processing. The results shows large variations in the thickness. Since the grinding tool is accurate, the thickness variations may be caused by the substrate thickness variations and tape deformations due to the pressure of the grinder during the thinning. This method is strongly dependent on the substrate thickness variation. Normally the substrate thickness variation is ±10% of the total thickness. For a 300-μm-thick substrate, the variation is ±30 μm. It is clear that this method will not work for ultrathin die of 100

μm or less. To improve the PEG process, the products can be fixed to

a glass plate with a liquid type adhesive, as shown in Fig. 10. Since the variation of the substrate thickness can be absorbed by this liquid adhesive, the distance between the glass top and the die top surface of each product can be kept at the same value. Therefore, the die thickness can be controlled very precisely. Also, this method can mask not only the variations of substrate thickness but also the variations of joint height.

The results of this improved method results appear in Table 3. As shown in the table, the span of the silicon thickness differences of 29 μm in the first experiment was reduced to 5.4 μm with this improved method. Fig. 11 shows a cross section of the 20-μm-thick silicon die flip chip interconnections. This technique was patented in Japan [7].

2-3. Structural Analysis by FEM

FEM structural analysis was performed to investigate the influence on the warpage of a substrate and the solder strain of the interconnections due to changes in the silicon thickness over the temperature range from 25°C to 250°C [8]. In addition, the influence was compared to the results of reliability tests for a sample of thin dies. Fig. 12 shows the maximum displacement is 101 μm for a thickness of 725 μm and 375 μm for a silicon thickness of 50 μm. When the silicon is thick, the hard silicon limits the warpage of the substrate.

Thinning before Assembly

Industry standard

Thinning after Assembly

PEG

Thinning before Assembly

Industry standard

Thinning before Assembly

Industry standard

Thinning after Assembly

PEG

Fig. 7 : PEG Method

(a)

(b)TapeProduct

Fig. 8 : Schematic illustration of PEG process

(a) before thinning and (b) after thinning

Fig. 9 : Photograph of experimental sample after being attached to grinding tape

Table 3 : Result of silicon thickness after PEG

(*2) : After process improvement

(*1) : Before process improvement

1.75.467.272.669.470µm(*2)

3.729.070.099.083.970µm(*1)

2.68.1145.2153.3149.4150µm(*2)

1.54.517.622.119.920µm(*2)

SigmaRangeMin.Max.AverageTarget

(*2) : After process improvement

(*1) : Before process improvement

1.75.467.272.669.470µm(*2)

3.729.070.099.083.970µm(*1)

2.68.1145.2153.3149.4150µm(*2)

1.54.517.622.119.920µm(*2)

SigmaRangeMin.Max.AverageTarget

Unit : µm

(a)

(b) Glass plateProduct

Fig. 10 : Schematic illustration of variation of the

silicon thickness improvement (a) before thinning and (b) after thinning

Die Thickness : 15-20μm

Cu Post Height : 50μm

Solder Height : 15-20μm

Fig. 11 : Cross-Section of 20-μm-thick silicon thickness flip chip interconnections

951 2009 Electronic Components and Technology Conference

Conversely, when the silicon is thin, it cannot resist warping of the substrate and the warpage is large. At the same time, the strain on the solder joints is reduced when the die is thin. The strain is 9.64×10-3 for a silicon thickness of 725 μm, and 4.93×10-3 for 50 μm. Since this is in inverse proportion to the 1.9th power of a strain ratio based on the assumption of n=1.9) in a modified Coffin-Manson Equation [9], the structural analysis indicates that the solder joint life at a silicon thickness of 50 μm is 3.58 times longer than for a thickness of 725 μm.

2-4. Reliability Test Results with ultra thin die

The same TEG kits in Section 1-1 section were used for this evaluation. Only thermal cycle tests were done with the thin dies. Four different thicknesses of silicon die, 20 μm, 70 μm, 150 μm and 725 μm , were joined on a substrate with the C2 technology. The 20-μm, 70-μm and 150-μm samples were thinned with the improved PEG process. One 725-μm sample out of eight failed at 4,000 cycles. Though the other seven 725-μm samples passed the test, their resistance increased somewhat. The resistance of the other die thicknesses were very stable and the ratio of increased resistance was less than 2% over 8,500 cycles (Fig.13). The main concern was for cracked die, but there were no failures of that type. This reliability test results confirm that "when a die is thin, the strain on its joints is small".

3. OBAR WLUF with Fine Pitch C2 Flip Chip 3-1. Background

OBAR WLUF [10] is Over-Bump Applied Resign Wafer-Level UnderFill developed for large die and high I/O counts in high performance computer systems, thus avoiding low-k layer delamination in the semiconductors. This technology

can also be used for digital consumer products where an ultrafine-pitch flip chip technology is used for miniaturization. In a digital consumer products, the die size shrinks every year driven by cost pressures, but the I/O counts are increasing as the the functions increase. A peripheral I/O layout for the die is advantageous for the organic substrate to reduce the costs. If an area array I/O layout is used, the substrate must have more layers. This drives smaller I/O pitches currently pushing below 40 µm. Though C2 technology is introduced for these extremely fine-pitch flip chip interconnections, underfill voids can cause problems, and OBAR WLUF can help by making the underfill fillet much smaller compared to the conventional capillary action underfill process. The smaller fillet length is helpful in increasing the density of the components on each substrate. 3-2. Reliability Test Results with C2 80 μm pitch

The same TEG kits as in Section 1-1 were also used for this evaluation. The C2 bump pitch is 80 μm. The WLUF material was spun onto a C2-bumped 8-inch non low-k TEG wafer. The B-staged wafer was diced and each die was bonded to a substrate using a flip chip bonder. After aligning a die and a substrate, the die was tacked by heating it to above the Tg of the b-staged underfill. The bumps were pressed through the underfill to touch the pads on the substrate. The assembly was then heated to temperatures above the meting point of the Sn-2.5Ag solder. Post-curing was used to harden the underfill completely. Fig. 14 shows a cross-section of the C2 interconnection with the OBAR WLUF. Good wettability was confirmed between the Sn-2.5Ag solder on Cu pillars and the Cu OSP pads on a substrates. Then a JEDEC Level-3 pre-conditioning test (125°C bake for 24 hours, 60°C at 70%RH for 40 hours, and 3 times at 260°C peak reflow) and a TC test(-55°C to +125°C, 2CPH) was done. No failures were observed at 500 cycles. The C2 process with 50-μm pitch will be evaluated next.

Conclusions C2 is a flip chip interconnection method for the wire-

bonded die designed with a pitch of 50 µm or larger. Since the process is SMT compatible, it is an inexpensive method and we can utilize the current C4 and SMT infrastructures. The C2 interconnection resistance change after the thermal cycles and high temperature storage is quite small compared to Au stud-solder interconnections. Also the C2 structure was evaluated for a low-k device and no failures were observed at

0.0000.0500.1000.1500.2000.2500.3000.3500.4000.4500.500

0 100 200 300 400 500 600 700

0.0%

0.2%

0.4%

0.6%

0.8%

1.0%

1.2%

Maximum Displacement (mm) Von Mises strain (%)

Max

imum

Dis

plac

emen

t (m

m)

Von

Mis

esst

rain

(%

)

Die thickness (μm)

Fig. 12 : Analysis result for chip thickness vs. Maximum

Displacement and Von Mises Strain

-2.0%

-1.0%

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1.0%

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ta-R

rat

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itial

(%)

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AfterSoaking

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differ significantly

725μm

20μm

70μm

150μm

1 of 8pcs OPEN

Del

ta-R

rat

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Ini

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(%

)

Fig. 13 : Result of thermal cycling test

Fig. 14 : C2 80-μm pitch FC Interconnection with OBAR WLUF

952 2009 Electronic Components and Technology Conference

1,500 cycles in the thermal cycle test. This indicates that low-k C2 structures seem robust. However, a disadvantage of this method is the difficulty of handling a very thin dies below 100 µm, because such thin die tend to slip during the reflow process. PEG is the best solution for flip chip interconnections with ultrathin die in the C2 process. This process involves grinding each die while bonded to an organic substrate with underfill. Prototype showed that the die could be ground to 20 µm with the PEG method and the ratio of its interconnection resistance increased by less than 2% in the thermal cycle test was confirmed. For the extremely fine-pitch flip chip interconnections, OBAR WLUF is good solution to avoid the underfill voids in the ultra-narrow spaces between a silicon die and an organic substrate. An 80-µm pitch C2 interconnection on an organics substrate with OBAR WLUF was successfully created.

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Mounting Process by STAMP”, Journal of Japan Institute of Electronics Packaging, No.3(2005)

2. K.Fujita,et al, ”Three-Dimensional System in Packaging Technology”, Sharp Technology Report, No.83(2002)

3. Y.Yoneda, et al, “A Novel Flip Chip Bonding Technology Using Au Stud Bump and Lead-Free Solder”, Pan-Pacific Conference, 1999

4. Y.Orii, K.Toriyama, Y.Oyama, and T.Nishio, “Ultrathin SiP/PoP Technologies using 50µm pitch C4 interconnections”, Proceedings of the International Conference on Electronics Packaging, Apr. 2007, pp.66-71

5. K.Toriyama et al., “Development of Fine Pitch Flip Chip Interconnection Using Solder Bumps”, Proceedings of the Microelectronics Symposium, Oct. 2007, pp.143-146.

6. Y.Orii, K.Toriyama, Y.Oyama, and T.Nishio, “Post Encapsulation Grinding for MPS-C2 Ultrafine Pitch Flip Chip Technology”, Proceedings of the International Conference on Electronics Packaging, Jun. 2008

7. Y. Oyama, Y.Orii, T.Nishio, JP patent 3,980,624 8. Y.Orii, et al, “Development of Solder Interconnection in

Ultra Thin SiP/PoP “, National Convention of I.E.E. Japan, Vol3,3-S16(21)-(24)

9. I.Shoji, Y.Orii, et al, “Solder Joint Reliability Evaluation of Chip Scale Package using a modified Coffin-Manson Equation”, Microelectronics Reliability 44, 2004

10. C.Feger, N.C.LaBianca, G.Hougham, H.K.Shobha, S.L.Buchwalter, "A Wafer-level Underfill Process for Flip-chip Packaging", IMAPS Topical Workshop and Exhibition on Flip Chip Technology, Jun. 2003.

953 2009 Electronic Components and Technology Conference