Analysis of Fractional Spur Reduction using ΣΔ-noise Cancellation in Digital-PLL

Kameswaran Vengattaramane1, 2, Jan Craninckx1 and Michiel Steyaert2

1SSET, IMEC Leuven, Belgium

2 Dept of ESAT-MICAS, K.U. Leuven Leuven, Belgium

Abstract— In Digital Phase-Locked Loop based fractional-N RF-frequency synthesizers, the use of a Time-to-Digital Converter (TDC) as a quantized phase detector brings spurious emissions when synthesizing near-integer channel frequencies. The location of these fractional spurs is dependant on the resolution of the phase detector and the channel frequency being synthesized. In addition, spurs are also generated due to the non-uniform TDC quantization steps. This paper discusses a fast PLL simulation platform and a simulative analysis of the impact of ΣΔ-noise cancellation on the fractional spurs.

I. INTRODUCTION Digital PLL (DPLL) used as a fractional-N frequency

synthesizer is shown in Fig. 1. This architecture is a digital emulation of a conventional charge-pump based PLL [1],[2]. In such a DPLL, the phase comparison between a stable reference clock and a divided Digitally Controlled Oscillator (DCO) clock is performed by a Time-to-Digital Converter (TDC). The phase difference is quantized with the resolution of the TDC. The quantized phase error is then processed by a digital loop filter. The DCO which is equivalent to a Digital-to-Analog Converter (DAC) driving a Voltage-Controlled Oscillator (VCO) is modulated by the filtered phase error. The loop locks to a fractional multiple given by the channel select word, of the reference clock frequency due to sigma-delta dithering of the divide modulus.

The digitally-intensive PLL architecture is suited for integration in deep-submicron digital-CMOS technology. Apart from reduced area penalty due to the elimination of the passive loop filter components in the analog implementation, the digital loop filter also offers better reconfigurability and wide bandwidth programmability options. Digital architecture aids the calibration of TDC and DCO allowing the possibility of wide-bandwidth phase modulation [3]. Further, digital signal processing techniques can be employed to enhance the phase-noise performance as the loop signals are in the digital format.

The introduction of the quantizers in the architecture through the finite time resolution [psec/LSB] of the TDC and the frequency resolution [MHz/LSB] of the DCO significantly impacts the spectral purity of the synthesizer. Impact on the in-band phase noise due to the quantizations in a DPLL is presented in [4] assuming white quantization noise models. A pure white quantization model for the TDC predicts only the phase-noise impact. In reality, the inclusion of a quantized phase detector in the loop brings in spurs when synthesizing

close-to-integer frequencies [5]. In a conventional analog ΣΔ-PLL, the channel frequency dependent spurs are attributed to the insufficient scrambling of the ΣΔ output and a non-linear charge pump. Addition of a random-dither input to the ΣΔ and charge-pump linearization techniques are typically used to combat these spurs. However, in a DPLL, as is highlighted in this paper, the spurious behavior is observed even when the ΣΔ-output is sufficiently scrambled. The spur location is dependent on the fractional-channel being synthesized and the TDC resolution. In a single-standard radio, a typical solution is to avoid using such channels by using larger fractional offset channels. This solution is however not elegant in a multi-standard radio covering many standards with a single frequency synthesizer. This paper investigates the impact of the ΣΔ-noise cancellation scheme, which exploits the digital nature of DPLL architecture and results in a significant fractional spur reduction. This technique is used in [6] for phase noise plateau improvement with fractional channel offsets of 1 MHz, and in [7], a fractional-spur reduction is reported with 400 KHz offset, without further elaboration. In this paper we motivate this technique for fractional spur reduction considering the low fractional channels. The rest of the paper is as follows - Section 2 describes a fast PLL simulation platform with accurate modeling of the quantization phenomena. Focusing on the TDC quantization with near-integer channels, Sec. 3 investigates the fractional spur generation. ΣΔ-noise cancellation as a technique for spur reduction is then discussed and finally the impact of the noise cancellation with a non-ideal TDC i.e. non-uniform quantization is highlighted.

Figure 1. DPLL based Fractional-N Synthesizer [1].

978-1-4244-3828-0/09/$25.00 ©2009 IEEE 2397

Figure 2. Simulink model of fractional-N DPLL.

II. SIMULATION PLATFORM A Simulink-based DPLL model for fast and accurate

analysis of the phase-noise incorporating the quantizations is shown in Fig. 2. This model evaluates the state-variables only at the time instances of an ideal clock Tref. That is, the reference clock input is not modeled as voltage but as a variable tREF[k], which represents the deviation in time due to jitter tj,REF[k], of the kth reference edge from the ideal edge instance of a clock kTref .The PSD characteristic of the reference jitter block is programmed to exhibit a white noise floor, 1/f2 and1/f3 sloped regions. The reference frequency Fref used in this model is 40 MHz. Similarly, the variable tDIV[k] represents the deviation in time of the kth divider edge from the edge of an ideal clock at time kTref. The dynamics governing the model are as follows

( ) .][][][ QDIVREF ktktkE −= (1)

‘Q’ indicates a rounding operation w.r.t to the TDC resolution TTDC. The error E[k] represents the quantized time error between the arrival instances of the kth ref. clock and divider clock edges. E[k] is then filtered with appropriately scaled loop-filter transfer function Hloop[z]. The result is quantized (emulating DAC quantization) with a 14-bit resolution quantizer and applied as a control variable Vtune[k] to the VCO block. Once again, without computing the oscillator waveform as a function of time, the phase P[k] of the VCO is simply evaluated at the kth edge of an ideal clock as

refVCOtunecenter TKkVkPkP ××+Ω+=+ )][(][]1[ (2)

Where Ωcenter=2πfcenter , the center frequency is taken as 3.9 GHz and sensitivity KVCO of 50 MHz/V. With long simulations, the phase variable can overflow and thus we perform a modulo operation by subtracting the desired phase, Ωdesired=2πfdesired where fdesired=NfracFref. ].[]1[]1[ , kPTkPkP VCOnrefdesired +×Ω−+=+ (3)

Also, the phase-noise of the VCO Pn,VCO is added. The noise PSD is programmed to exhibit a noise floor, 1/f2 and1/f3 sloped regions. Ideally, in a frequency synthesizer, the number of DCO clock edges NDCO in any cycle of ideal clock Tref should be Nfrac Where Nfrac being a fractional number expressed as sum of an integer- N and a fractional offset - frac. The arrival times of

the ideal divider edge would be kTref i.e. the ideal P[k] = 2πkNfrac. Since we have performed a modulo operation in the VCO, this operation is compensated in the divider block as

.2

]1[][][π

−−+=

kPkPNkN fracDCO (4)

The second term in (4) is used to account for the impact of added jitter. In addition to this offset, the ΣΔ−dithering action on the divider modulus perturbs the time of divider-edges from ideal instances kTref. The input to the ΣΔ is a fractional number Nfrac, and the output is stream of integers N[k] such that Nfrac = mean (N). Due to this mechanism, instead of dividing the DCO clock by Nfrac, the instantaneous divide ratio is N[k]. Expressed in terms of the number of DCO periods this results in an offset in the kth cycle of the divider clock as ].[][][ kNkNkN DCOoffset −= (5)

The number of DCO periods the kth divider time edge is offset from the ideal reference time stamps is simply an accumulation effect, as the time of arrival of the current edge is the sum of previous edge arrival instance and the number of DCO edges added by the current divide modulus. Thus, ].[]1[][ kNkNkN offsetdivdiv +−= (6)

This is translated into a divider time stamp tDIV[k] with added divider jitter as

],[][][ , ktf

kNkt DIVjdesired

divDIV += (7)

thus closing the loop. Divider jitter has a white-noise PSD. This model processes only the excess phase without simulating the carrier and permits fast and accurate simulations with realistic noise sources. The model emulates a type-II PLL with a third-order loop filter. MASH 1-1-1 ΣΔ, is used to dither the divide modulus. In this model, the quantizers and the noise sources can be selectively activated. Fig. 3 shows the generated contributions of the reference, divider, ΣΔ and VCO noise blocks to the output phase noise P[k], shaped by the loop dynamics without activation of the quantizers.

Figure 3. PLL Phase Noise Contributions.

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Figure 4. Origin of the spurious tones due to TDC quantization. Input to the

TDC is a ΣΔ noise shaped jitter. The TDC output exhibits spurs.

III. FRACTIONAL SPUR GENERATION AND REDUCTION

A. Spurious Tones due to the Quantization of ΣΔ Divide Modulus Dither Induced Jitter If we assume that the TDC has a uniform step-size of

TTDC, then the input referred phase-noise due to the finite quantization resolution assuming a white quantization model can be estimated as

HzdBcTT

STDCref

TDC /12

)2(log10 2

2

10 ⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

⎟⎟⎠

⎞⎜⎜⎝

⎛

×××=

π (8)

This white noise is shaped by the loop transfer function

which is of low-pass nature as seen from the TDC. For frequencies within the bandwidth, the gain is approximately N2

frac. This scaled noise would then be added to the in-band noise plateau in Fig. 3. However, simulations show that the pure white noise model considered is not valid always and we observe spurious emissions when synthesizing close-to-integer channel frequencies. Fig. 4, (a) shows the closed-loop output phase noise with all active quantizers and noise sources, with a TDC resolution of 21 psec, Nfrac = 100 + 0.003 and a bandwidth setting of 150 KHz. As is seen, the output spectrum exhibits spurs. The concurrent phenomena here are – the TDC, DCO quantizations and the loop filtering, acting on the noise from all the sources. Setting the loop to an open-loop condition and by using a fine resolution DCO (3 KHz/LSB), we isolate the TDC quantization impact. The input to the TDC then is a combination of jitter from the reference, divider and the ΣΔ-divide modulus dither (VCO jitter is not considered as the loop is open and in closed-loop, it is high-pass filtered by the loop action not affecting the in-band noise). The phase noise of the ΣΔ divide modulus dither induced jitter at the TDC input is shown in (c). The ΣΔ dither induced jitter is seen to be sufficiently scrambled. However, when this is quantized by the TDC as shown in (b), instead of a clean white-noise predicted by (8), we see spurious behavior. When the loop is closed, this noise shown in (a) is simply raised by the loop-gain. To be noted that the jitter induced by the reference and

the divider are not strong enough to scramble out these spurs in the closed-loop condition. We then consider fractional offsets < 0.0025 i.e. a channel frequency that is [0-100 KHz] offset from an integer channel of 4 GHz.

Table I shows the position and strength of the dominant spur as a function of the channel frequency and the TDC resolution. A bandwidth setting of 150 KHz is used. Dominant spur location is seen to be at a multiple of the fractional offset frequency (frac x Fref).

TABLE I. DOMINANT SPUR POWER AND LOCATION

Channel Offset from 4.00 GHz TDC Resolution

[psec] 20 KHz 40 KHz 80 KHz 100 KHz

11

-44 dBc 460 KHz

-70 dBc 1.38 MHz

-75 dBc 1.84 MHz -

21 -25 dBc 240 KHz

-34 dBc 480 KHz

-47 dBc 960 KHz

-52 dBc 1.2 MHz

30 -25 dBc 160 KHz

-33 dBc 320 KHz

-46 dBc 640 KHz

-52 dBc 800 KHz

Spurs also appear at multiples of the dominant spur

frequency. From the table we see that for a given TDC resolution, the dominant spur locations move from in-band to out-of-band as we use higher fractional offsets. Also, higher the resolution, faster these spurs move across offset frequencies. The spur-level can be controlled by reducing the bandwidth or by using slightly higher fractional offsets. From experiments it is also observed that by using single-loop ΣΔ architecture, similar spurious behavior is observed at the TDC output. Thus the quantization of the TDC driven by ΣΔ-divide modulus dither due to a low fractional input causes the spurious phenomenon.

B. ΣΔ-Noise Cancellation and its Impact on Fractional Spur Reduction The input to ΣΔ is a fraction - Nfrac and the output is a

stream of integers N[k]. The instantaneous error Nfrac-N[k] represents a deviation from the mean. The error in the time-stamps of divider clock due to this deviation then accumulates

∑ −×

])[(1 kNNFN frac

reffrac

(9)

This is then subject to TDC quantization. Output from the ΣΔ, N[k] is readily available as a digital stream. If the quantization step-size of TDC is calibrated then we can predict the dithering induced quantized phase noise by (9) and subtract it out from the TDC digital output as shown in Fig. 5.

Out

N

Ref

ChannelSelect

Phase DetectorTime-to-Digital

Converter

DigitalLoop Filter

VCO

DCO

DAC

Noise Estimator

TDC Quantization Q

Figure 5. ΣΔ-noise cancellation with a quantizer.

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In a conventional analog fractional-N PLL, a similar technique is used to enable wide-bandwidth modulation by cancelling the ΣΔ-quantization noise [8]. The difference here lies in quantizing the accumulated error before subtraction. This also predicts the fractional spurs and due to the cancellation, this technique results in significant spur reduction when synthesizing near-integer channel frequencies in an ADPLL as shown in Table II.

TABLE II. SPUR REDUCTION DUE TO ΣΔ-NOISE CANCELLATION

Channel Offset from 4.00 GHz TDC Resolution

[psec] 20 KHz 40 KHz 80 KHz 100 KHz

11

- - - < -80 dBc

21 -40 dBc 240 KHz

-60 dBc 500 KHz

- < -70 dBc

30 -50 dBc 500 KHz

< -75 dBc < - 80 dBc < -80 dBc

The loop-bandwidth is set at 150 KHz and the RBW of the PSD is 150 Hz. In most cases we observe spur removal or remarkable reduction in spur-level demonstrating the effectiveness of this technique. For coarse resolutions like 20-30 psec and a channel frequency offset of 10-40 KHz from an integer channel, the spur cancellation is not complete. Spur location in such cases tend to be in-band or in the transition-band. The algorithm estimates the induced phase error due to ΣΔ dithering induced jitter accurately. In reality, there is noise imposed by the reference and the divider jitter which are not strong enough to scramble out the quantization noise. Thus the TDC output after cancellation still has a residue with spurious content. Since this residue is low-pass filtered by the loop-dynamics, Loop bandwidth then needs be adjusted to aid the cancellation scheme. From simulations, the -40 dBc spur-level with 21 psec resolution and a 20 KHz fractional offset channel, drops to -60 dBc with 75 KHz bandwidth, and disappears with a 50 KHz bandwidth setting. Although increasing the reference noise could help in scrambling the spurious residue, it would result in severe spectral impurity at the output.

C. Spurs due to the TDC mismatch In reality the TDC implementation introduces mismatch

between the quantization levels making it a non-uniform quantizer. In our model, we simulate this behavior by varying the TDC thresholds. In this case, with low fractional offsets (< 0.01), we observe spurs at all multiples of the fractional offset (frac x Fref). Fig. 6 shows the phase-noise spectrum with a TDC resolution of 15 psec, a maximum DNL (absolute) of 3.3 psec, and a synthesized channel of 4 GHz + 40 KHz. We see spurs at multiples of 40 KHz due to the non-uniform TDC quantization. The spur level is dependant on the Differential Non-Linearity (DNL) of the TDC. Simulations indicate that to contain the spurs below -40 dBc, the max. DNL should not be more than 3 psec. Assuming we calibrate the resolution of the TDC, the ΣΔ-noise removal technique can be still be utilized. Also, superposed in Fig. 6 is the impact of the ΣΔ-noise cancellation. We observe that only the spur at 640 KHz is reduced, thus affecting only the out-of-band spur ,while the other TDC non-ideality induced ones remain. If the TDC non-

linearity could be calibrated [9], the other non-linearity induced spurs could be controlled as well.

Figure 6. TDC mismatch induced Spurs and the impact of ΣΔ noise

cancellation superposed.

IV. CONCLUSIONS A fast simulation platform has been developed for the

accurate characterization of the impact of quantizations on the synthesized spectral purity in a Digital PLL. Spur generation due to the TDC quantization and near-integer fractional channels has been motivated. ΣΔ-noise cancellation as a remedial measure for the fractional spurs is demonstrated. Simulations indicate that for a range of near-integer channel frequencies, this technique improves the spectral purity, with the spur reduction depending on the TDC quantization.

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