1W 3.3V-to-16.3V Boosting Wireless Power Transfer Circuits with Vector Summing Power Controller

Kazutoshi Tomita, Ryota Shinoda, Tadahiro Kuroda, and Hiroki Ishikuro Department of Electronics and Electrical Engineering, Keio University,

Yokohama, Kanagawa, Japan kazutoshi@kuro.elec.keio.ac.jp

Abstract— This paper presents SD card size wireless power transfer system for large volume contactless memory cards. Voltage is boosted simultaneously with power transfer, which eliminates the DC-DC converter or charge-pump circuit for data write operation into the flash memory chip. The proposed approach reduces the number of components and BOM cost and improve the total power efficiency. Vector summing technique is proposed to control the transmitting power and secondary side voltage. The transmitter and rectifier have been designed and fabricated using 0.18um-CMOS with high voltage option. Voltage boost from 3.3V to 16.3V and 1W power transfer with 50% total efficiency have been successfully demonstrated.

I. INTRODUCTION Recently large volume non-volatile memory devices such

as solid-state-drive (SSD) or SD card play more and more important role. Such devices are connected with the host by wireline to transfer the data and power. If the power and data can be transferred by wireless, the connector and cable can be eliminated (Fig.1(a)). This brings dependability to the system because it can become waterproof and free from contact failure. It also brings flexibility to the system design.

Many researches on the wireless power transfer which used inductive coupling[1][2]or magnetic resonance[3] have been reported. Wireless power transfer standard such as “Qi”[4] has been established and several products have already been in commercial use. In such application, secondary side (receiver side) contains battery and it acts as a buffer which hides rapid secondary side load change from primary side and fast power control is not required.

However, for the application of the wireless memory card, it becomes difficult to contain a battery in the card. Therefore, the rapid load change in the card may disturb the voltage (Fig.1(b)) and degrade the circuit operation or device reliability. Shunt regulator (voltage limiter) cannot be used in the future contactless terra-byte memory card because the card consumes watt class power and the heat generated in the regulator degrades system reliability. To avoid such problem, high speed power control is inevitable. Considering to the quick response of power control, MHz band frequency is suitable. However the frequency modulation cannot be used because the allowed frequency band is discrete (Fig.2)[5].

Another requirement in the contactless memory card is a voltage boost for data write operation. In the flash memory chip, charge-pump circuit is embedded to generate a high voltage. However, charge pump consumes about 60% of power during write operation in NAND flash memory chip[6].

Fig.1. Concept of contactless memory card

Frequency(MHz)

dBμA

/m a

t 10m

1 10 100 1000

80

60

40

20

0~135kHz

13.56MHz

433.92MHz869MHz

2.45GHz5.8GHz

6.78MHz 27.12MHz40.68MHz

915MHz

Fig.2. ISM Band frequency

To improve the efficiency, DC-DC converter can be used. However, the additional components are required which limits the size and cost of the card.

In this work, SD card size simultaneous voltage boosting with wireless power transfer are realized choosing large turn number ratio between the primary and secondary coils. To control the transmitting power and secondary side voltage, vector summing technique using two half-bridge circuits are proposed. The voltage boosting and power control have been demonstrated by the test chips.

II. ARCHITECTURE OF VOLTAGE BOOSTING Flash memory needs high voltage during write operation.

Fig.3(a) shows one approach to boost the secondary side voltage. At primary side, DC-DC converter is placed to control the transmitting power. The driver circuit (TX) converts the DC to AC current. At secondary side, rectifier converts AC current to DC voltage again, and DC-DC converter or charge pump circuit boosts the voltage to required level for data write operation. Total efficiency can be expressed as, ηtotal = ηDC-DC Conv × ηTX × ηCoil × ηRect × ηBoost. (1) IEEE Asian Solid-State Circuits Conference

November 14-16, 2011 / Jeju, Korea

978-1-4577-1785-7/11/$26.00 ©2011 IEEE

IEEE Asian Solid-State Circuits ConferenceNovember 14-16, 2011 / Jeju, Korea

978-1-4577-1785-7/11/$26.00 ©2011 IEEE

TX RectifierVoltage Boost

ηTX ηCoil ηRectifier

M

LTX LRX

CS

CP

3.3V 20V

DC-DCConverter TX Rectifier DC-DC

Boost CP

ηDC-DC Converter ηTX ηCoil ηRectifier ηBoost Circuit

M

LTX LRX

CS5V 3.3V 3.3V DC 20V DC

(a)One example of architecture

(b)Proposal architecture Fig.3. Voltage boosting wireless power transfer system

If each component has some power loss, the total efficiency becomes low. Furthermore, the DC-DC converter or charge pump increases the number of discrete components and cost.

Fig.3(b) shows a proposed architecture. Instead of voltage boosting by DC-DC converter or charge pump, the secondary side voltage is boosted by using coils with large turn number ratio between the primary and secondary coils. The advantages of this approach are the reduced number of components which brings an improved efficiency and therefore, reduced size and cost. The total efficiency can be given as ηtotal = ηTX × ηCoil × ηRect. (2)

The issue of this proposed approach is that the way to control the transmitting power. The second issue is that the efficiency of the coils, (ηcoil) could be decreased when the large ratio of the turn numbers are chosen.

III. POWER CONTROL BY VECTOR SUMMING TECHNIQUE Fig.4 shows a concept of the proposed vector summing

power control. The transmitter consists of two inverter type drivers and coils which forms two half-bridge configuration. The phase difference between the switching clocks to each driver introduces the phase difference between the current in each coils. The induced magnetic fields are summed in the secondary coil. The power contribution from each primary coils (LTX1 and LTX2) are PO and POejθ, and secondary power can be expressed as

Power = PO × (1+cosθ). (3) Previous reported works in [7] adopts multiple primary

coils to deal with the problem of position gap between the transmitter and receiver. In the ref [7], the primary coils are placed in array and the nearest coil from receiver is chosen for power transfer. They cannot be used for power control. On the other hand, primary coils of this research are stacked in the same place and the magnetic fields are effectively summed at secondary coil.

For the power control, one of the conventional approach is to use a full-bridge structure[8] as shown in Fig.5. By controlling the phase of the switching clocks (S1 and S2), the duty ratio when the current flow through the transmitting coil can be changed and the transmitting power can be controlled.

Fig.4. Principle of proposed vector summing power control

VDD

S1 Vi+

-S2

S1

S2

Vi

φ

Fig.5. Conventional full-bridge inverter

However, the current flows through both PMOS and NMOS at a time. Since the voltage is boosted by using large turn number ratio, the primary coil for this application has only one turn. Therefore the parasitic resistance of MOSFETs becomes severe power loss. In the half-bridge configuration current flow through only PMOS or NMOS at a time, which reduces the power loss.

Furthermore, using two half-bridge configuration reduces the required current to half in one transistor. In standard CMOS LSI, it is difficult to transfer high power because large current becomes a stress for MOSFET and degrades the characteristics. Therefore current reduction in one transistor becomes advantage.

IV. CIRCUIT IMPLEMENTATION Fig.6 shows coil design. Considering the SD card size,

external diameters of the coils are about 20mm. The metal layers in the PCB are used for coil patterns. The turn number of primary and secondary coils are one and eight, respectively, and each self-inductance LTX = 41nH and LRX = 2.58uH. Even though the distance between the primary and secondary coils are several millimeter, it is difficult to keep the magnetic flux coupling between the coils high. To increase the coupling coefficient, the center line of the metal wire pattern of primary coil is aligned with the center wire of the secondary coil.

Fig.7 shows block diagram of the developed power transfer system. Phase difference between the switching clocks for primary coils LTX1 and LTX2 is controlled by Delay Locked Loop (DLL). Then dead time generator inserts the non-overlap phase between the switching clocks for PMOS and NMOS to prevent VDD and GND from being shorted. A level shifter levels up the clock signal from 1.8V to 3.3V and put into the driver MOSFET. The resonant frequency of the primary coils is tuned by series LC connection.

In the secondary side, parallel LC connection is adopted to tune the resonant frequency. Since the parallel connected LC circuit acts as current source at resonant frequency, the high

Fig.6. Coil design

re

ctifi

er

Vref

DLL

Buf

fer

Vcomp

CLK

On Chipprimary

On Chipsecondary

Dea

d_tim

e

Leve

l_sh

ift

LTX1

LTX2

LRX

Off ChipPhase select circuit

Dea

d_tim

e

Leve

l_sh

ift

Fig.7. Proposal circuit

voltage can be obtained and it is suitable for voltage boosting. The gate cross-coupled rectifier is used to convert from AC to DC voltage. The generated DC voltage is compared with the reference voltage and fed back to the DLL for power control.

A. DLL Circuit Fig.8 shows DLL circuit. VCDL produces multi phase by

dividing one cycle into 32 phases, and MUX chooses necessary phase. Fig.9 shows Bias circuit of DLL. Delay time of VCDL is controlled by current source M2 and M3, and Vctrl. IT – i > 0 by adjusting aspect ratio of M2 and M3, thereby, circuit operates continually within a wide range of Vctrl = 0 ~ 1.8V.

B. Rectifier In this work, gate cross-coupled rectifier[9] is adopted.

Fig.10 shows rectifier circuit. Thick oxide MOSFETs whose maximum available voltage is 32V are used. At secondary side, induced voltage between the coil terminals is high because of voltage boosting, VGS of gate-cross coupled NMOS becomes large and on resistance of NMOS is low. As a result, VDS of NMOS is also low that it thinks parasitic diode in NMOS doesn’t turn on. Therefore, no additional dynamic bulk regulation transistors are necessary at switch NMOS, and this results in improvement of rectifier efficiency.

V. MEASUREMENT RESULTS As explained in Fig.2, several frequencies can be used for

wireless power delivery as ISM band. Considering that the tradeoff between the response speed, components size, and power transfer efficiency, the switching frequency of

PFD CP LF

VCDL

Start control_circuitStart Control Signal

MUX5

Vin VPFD ICP Vvtrl

iIT − i

Vout

Vsignal

Bias_circuit

Fig.8. DLL circuit

VDD

Vctrl

VDD

ITi

i

i

M1 M2 M3

Vin

Voutm=4 m=8m=6

IT − i

IT2

Bias circuit Delay cell in VCDL

Fig.9. Bias circuit and delay cell

Diode PMOS Switch NMOS

LRX CRX

Fig.10. Gate cross-coupled rectifier circuit

6.78MHz or 13.56MHz becomes a candidate for this application. If the higher switching frequency is chosen, the response speed for power control can be improved and component size can be decreased. However the power transfer efficiency degrades by the parasitic resistance of MOSFET and coils. If lower frequency is chosen, the power efficiency can be increased. In this work, placing the emphasis on the efficiency, the resonant frequency of primary and secondary coils is tuned to 6.78MHz.

Fig.11 shows power dependence on switching frequency at various phase difference. The distance between the primary and secondary coils is 1mm. The peak power split into two at this distance. The maximum power efficiency is obtained at 6.78MHz. The figure shows that the power can be controlled by changing clock phase. Fig.12 shows relation between the power and clock phase. 50% efficiency and 1W power delivery at 266Ω load is achieved. And power control is achieved at keeping the efficiency about 40% across the range of max-to-half power. Fig.13 shows output voltage with and without power control when the secondary side load is changed. By controlling the transmitting power, the secondary side voltage can be kept at constant.

0

0.2

0.4

0.6

0.8

1

1.2

1.4

0 5 10 15

phase=0°phase=45°phase=60°

Frequency(MHz)

Pow

er(W

)

Fig.11. Power dependence on frequency of each phase

0

10

20

30

40

50

60

0

0.2

0.4

0.6

0.8

1

1.2

0 50 100 150 200

Power

Efficiency

Condition: Load Steady

Phase(°)

Pow

er(W

)

Effic

ienc

y(%

)R=266Ω

Fig.12. Output power and efficiency dependence on phase

0

5

10

15

20

25

0 0.3 0.6 0.9 1.2

no-controlled

controlled

Steady

Power(W)

Out

put v

olta

ge (V

)

Fig.13. Output voltage dependence on power

Even when the distance from the primary coils to the secondary coil is changes from 0 to 7mm, over 1W power can be transferred. And even if the distance is extended to 10 mm, over 0.5W can be transferred. In case study, to transfer power of 1W, the output voltage is 16.3V at 266Ω load. If the required power can be reduced to 0.3W, voltage can be boosted up to 20V without degradation of efficiency.

Fig.14 are chip microphotographs. 0.18um-CMOS with high voltage option are used. Low voltage (1.8V) MOSFETs are used for DLL and other control circuit. Medium voltage (5V) MOSFET are used as switching driver circuit and high voltage (32V) MOSFETs are used in secondary circuit. The chip size of both the transmitter and rectifier are 2.5mm×2.5mm.

TABLE I. compares this work to other wireless power transfer circuit using 0.18μm-CMOS process.

DiodePMOS

DiodePMOS

SwitchNMOS

SwitchNMOS

DLL

Buf

fer

SwitchingPMOS

Buf

fer Switching

NMOS

Non-OverlappingCircuit

(a)Primary Chip (a)Secondary Chip2.5mm 2.5mm

Level Shifter

Fig.14. Chip microphotographs

TABLE I. Performance summary and comparison This Work ISSCC 2011 [1] ASSCC 2007 [2]

Efficiency 50% 17% 10%

Power 1W 6W 36mW

Distance 1mm 0.05~0.32mm 0.015mm*Secondary

Voltage 16.3V ≈1.8V 2.2V

Process 0.18μm CMOS 0.18μm CMOS 0.18μm CMOS

*Feature of proposal circuit

VI. CONCLUSION SD card size, voltage boosting wireless power transfer

circuit with vector summing power controller were proposed for contactless memory card. The test chips fabricated in 0.18um-CMOS achieved a voltage boosting up to 16.3V at 1W power transfer with 50% power efficiency. And boosting up to 20V was achieved at 0.3W power transfer. The vector summing power controller keeps the secondary side voltage at constant. This power control circuit can also be used for variable voltage output for write operation. 1W power can be transferred within the range of 0-to-7mm and 0.5W can be transferred at 10mm.

ACKNOWLEDGMENT This work is supported by CREST/JST.

REFERENCES [1] Andrzej Radecki et al., “6W/25mm2 Inductive Power Transfer for Non-

Contact wafer-Level Testing,” ISSCC, 2011, pp. 230–232 [2] Yuxiang Yuan et al., “Non-Contact 10% Efficient 36mW Power

Delivery Using On-Chip Inductor in 0.18μm CMOS,” ASSCC, 2007, pp. 115–118

[3] Tech Chuan Beh et al., “Basic Study of Improving Efficiency of Wireless Power Transfer via Magnetic Resonance Coupling Based on Impedance Matching,” ISIE, 2010, pp. 2011-2016

[4] “Qi System Description Wireless Power Transfer Volumw I: Low Power Part 1: Interface Definition Version 1.0.2,” April 2011

[5] Klaus Finkenzeller et al., “RFID HANDBOOK Second Edition,” 2003 [6] Koichi Ishuda et al, “1.8 V Low-Transient-Energy Adaptive Program-

Voltage Generator Based on Boost Converter for 3D-Integrated NAND Flash SSD,” JSSC, 2011, pp. 1478-1487

[7] C.L.W. Sonntag et al., “Load Position Detection and Validation on Variable-Phase Contactless Energy Transfer Desktops,” ECCE, 2009, pp. 1818–1825

[8] Takafumi Ishii et al., “Piezoelectric-Transformer Inverter with Full-Bridge Phase-Shift Control Scheme,” IEICE, 1999, pp. 45–51

[9] Maysam Ghovanloo et al., “Fully Integrated Wideband High-Current Rectifiers for Inductively Powered Devices,” JSSC, 2004, pp. 1976–1984