Ultra Low Voltage ∆Σ Modulation Using Biased

Inverters in 130 nm CMOS

Fridolin Michel and Michiel SteyaertK.U.Leuven, Dept. Elektrotechniek ESAT-MICAS

Kasteelpark Arenberg 10

Email: Fridolin.Michel@esat.kuleuven.be

Abstract— The design challenges of an ultra low voltage ∆Σ

modulator are discussed, which encompasses a switched capacitortechnique for efficient biasing of inverter-based integrators,an ultra low voltage comparator as well as efficient on-chipbias current generation and clock boosting for fast switchingtransients. All building blocks run at a supply voltage of only250mV while providing 61 dB SNDR in 10 kHz bandwidth at atotal power consumption of 7.5µW.

I. INTRODUCTION

The agressive device scaling prevalent in modern integrated

circuits enforces lower power supply to counteract the increase

in power consumption due to higher switching speed and

prevent gate breakdown of the shrinking gate oxide. At the

same time the transistor threshold voltage Vth is kept high in

order to avoid excessive leakage current. While device scaling

is in favor of digital high speed and high density circuits

it poses severe challenges for the analog and mixed signal

designer. Functionality has to be guaranteed with much smaller

current drive and limited headroom, which can only be accom-

plished by specialized low voltage circuit topologies. More-

over, low voltage designs are required by energy harvesting

and biomedical applications. For instance, thermo-electrical

generators are only capable of providing several hundreds

of mV output voltage, which needs either efficient voltage

boosting or intrinsic low voltage operation. Therefore, this

work describes a 250mV analog to digital converter (ADC)

[1] including circuit solutions for the major key challenges in

ultra low voltage circuit design.

The paper is organized as follows: Section II describes the

system level architecture. In Section III the building blocks are

introduced on the circuit level and in Section IV measurement

results are presented. Finally Section V ends with a conclusion.

II. SYSTEM LEVEL ARCHITECTURE

The ∆Σ converter consist of a pseudo-differential 3rd order

loop with single bit quantization (Fig. 3). At VDD = 250mV

the linear swing at the integrator outputs is limited to about

±20mV, so that a feed-forward structure is chosen, whichideally limits the integrators to process the noise only. The

3rd order loop allows to use a low over sampling ratio

(OSR) of 70, facilitating the implementation at the low speed

available at VDD = 250mV due to subthreshold operation

(|Vth| ≈ VDD in the given 130 nm technology). In weak

inversion the saturation voltage Vsat is about 100mV, so that

φ1

φ1φ1φ1

φ2

φ2

φ2

φ1D

φ2D

φ1

φ2

φ1D

φ2D

Vin

Vin

VoutVout

Vf

b

Vfb Vbiasn

Vbiasp

VDD

VDD

Vcmc

Vcmc

cls

Fig. 1: Biased inverter based integrator.

V +

out V −out

V +co

V −co

V +

inV −

in

VDD

VcmcVcmc

φlatch

cls cls

(a) φ1 = 1: amplification phase

V +

inV −

in

VDD

clscls

sense

CM

(b) φ2 = 1: calibration of 1st stage

Fig. 2: Ultra low voltage comparator.

all building blocks need to rely on two stack transistor designs.

This comes with a penalty on common mode rejection ratio

(CMRR), which requires special techniques to compensate for.

In order to handle large CM voltage swings properly bulk input

stage are usually required in continuous time applications [2],

which comes with loss in speed and voltage gain. However,

in discrete time systems calibration steps are possible, that

enable efficient CM and offset cancelation. For this reason, a

switched capacitor design is preferred as depicted in Fig. 3.

978-1-4673-0821-2/12/$31.00 ©2012 IEEE

φ1

φ1

φ1φ1

φ2

φ2

φ2

φ2

φ2

φ2

φ1D

φ1D

φ1D

φ1D

φ1D

φ1D

φ1D

φ1Dφ1D

φ1D

φ1D φ2D

φ2D

φ2D

φ2D

φ2Dφ2D

φ2D

φ2D

φ2D

φ2D

φ2D

φlatch

φlatch

φ1

φ1

φ1

φ1

φ1

φ1

φ1

φ2

φ2

φ2

φ2

φ2

φ2

φ2

φ1D

φ1D

φ1D

φ1D

φ1D

φ1D

φ1D

φ2D

φ2D

φ2D

φ2D

φ2D

φ2D

φ2D

V+out

V−

out

V+

in

V−

in

CM

Cff0

Cff0

Cff1

Cff1

Cff2

Cff2

Cff3

Cff3

sense

VDD

Vcmc

+

+

−

−

Fig. 3: Pseudo differential ∆Σ converter loop.

CM charge accumulation is prevented by local CM feedback

loops around all three integrators and large input CM voltages

are canceled before signal integration. This results in a robust

design while still using gate input devices.

III. BUILDING BLOCK DESIGN

A. Integrator

The integrators are implemented by inverter based ampli-

fiers shown in Fig. 1. In order to allow current definition

over process, voltage and temperature variation (PVT), the

inverter gates are biased independently using pre-charged gate

series capacitors [3], [4]. This also allows to set the gate

voltages beyond VDD/2, thereby providing larger overdrive,

which is crucial at 250mV supply voltage. The integrator

operates in two phases. During the first phase (φ1) the gate

series capacitors are pre-charged to bias the NMOS transistor

close to VDD and the PMOS close to ground. At the same time

the offset is cancelled by feedback of the inverter output to the

PMOS gate. Level shifting capacitor cls is used to allow the

inverter output to settle at VDD/2 while still biasing the PMOS

gate close to VDD . While the inverter is being calibrated the

DM input is sampled. Finally during the amplification phase

(φ2) the DM signal is integrated and the level shifting capacitor

pre-charged to make it ready for the calibration phase.

B. Comparator

As the integrator outputs have to be scaled down to the

maximum linear swing of ± 20mV the signal level at thecomparator input is very weak. At the same time, the feed-

forward path can introduce large CM signals at the comparator

input. These challenges are tackled by a gate input preamplifier

with CM cancellation. The preamplifier provides a DM gain

by 28 dB and accomplishes inherent CM stabilization by bulk

cross coupling (Fig. 2). The first comparator stage output is fed

to a bulk input latch stage. Only bulk input is possible, because

the NMOS gate is used for cross-coupling to guarantee reliable

latching and the PMOS bulk is reserved for current definition.

The preamplifier is biased and offset compensated in the same

fashion as the integrators (Fig. 2b) after the latch stage has

converged (Fig. 4)

0 0.2 0.4 0.6

0

20

40

t (µs)

Vco(mV)

amplification latch calibration

(a) Vco

0 0.2 0.4 0.60

100

200

t (µs)

Vcom

p(mV)

(b) Vout

Fig. 4: Simulation of comparator outputs for 1mV DM input.

C. On-chip biasing

Reliable bias current stabilization in ultra low voltage

designs is a challenging and important task, since devices

currents in subthreshold region are exponentially dependent on

voltage variations. A standard constant gm current reference

can provide current definition but in order to stay in saturation

978-1-4673-0821-2/12/$31.00 ©2012 IEEE

it restricts the bias voltages for NMOS and PMOS to

Vbiasn < VDD − Vsat − |∆Vth| (1)

Vbiasp > Vsat + |∆Vth| (2)

Hence, at VDD = 250mV the current drive is limited to the

nA range. In order to eliminate the Vsat limitation in (1) and

(2) the constant gm bias is followed by a level shifting circuit

(Fig. 5). A differential current to voltage amplifier compares

the constant gm current to 6 times the bias current and adjusts

pass transistor Mx. to drive this current. Due to the feedback

gain Mx can be pushed deeply into triode region, so that the

Vsat limitation is overcome. As a result, the bias voltages

are level shifted by 90mV and still track PVT changes until

clipping by the supply rails occurs (Fig. 6).

R

Vbiasp

Wp

Lp

6Wp

Lp

Vbp

Ibiasp

Mx

My

Cc

VDDVDDVDDVDD

constant gm bias differential current tovoltage amp

Fig. 5: Ultra low voltage biasing circuit with level shifter for

Vbp.

−20 0 20 40 60 80 1000

50

100

150

BiasVoltage(V)

T (◦C)

Vbiasp

Vbp

Fig. 6: Simulation of PMOS bias voltages over temperature.

D. Clock boosting

As many switches in this modulator design operate at

VDD/2, they cannot be opened sufficiently for operation at the

switching speed of 1.4MHz. Consequently, a clock booster is

employed [5], that doubles the NMOS and PMOS clock levels

(Fig. 7). Whereas charge pumping at very low voltage is a

challenging task due to the small difference between on and

off current, in this design only the parasitic gate capacitances

of the switches have to be driven while the main circuit

operates intrinsically at 250mV power supply. Therefore, the

charge pump load current is low, making the clock doubler

design feasible at only 250mV. The booster can start up at

VDD > 200mV as implied by the simulation results in Fig. 8,

thus leaving enough margin for operation at 250mV.

clk clkn

clkx clkxn

VDD VDD

Fig. 7: Clock booster.

200 210 220 230 240 2500

1

2

VDD (V)

Vbo

ost/V

DD

Fig. 8: Ultra low voltage biasing circuit.

Fig. 9: Chip micrograph.

IV. MEASUREMENT RESULTS

The ADC was implemented in 130 nm standard CMOS

(Fig. 9) and achieves 61 dB SNDR in 10 kHz bandwidth

(Fig. 10). With a power consumption of 7.5µW (Table I) thisresults in an figure of merit (FOM) of 0.41 pJ/step which is

defined as

FOM =P

2(SNDR−1.76)/6.02 · 2 · BW(3)

978-1-4673-0821-2/12/$31.00 ©2012 IEEE

Due to the overhead needed to reliable enable operation at the

record low voltage of 250mV the FOM is higher than the 0.7V

inverter based modulator in [6] (98 fJ/step) but still lower than

other designs below 0.6V [2](1.46pJ/step), [7](1.33pJ/step).

Due to the on-chip biasing circuit the converter operates

independently up to 100 ◦C (Fig. 11). The lower temperature

range is limited by the increase in |Vth| and can be extended byraising VDD to 300mV. In consequence, there is a fundamen-

tal tradeoff between lower temperature range and minimum

supply voltage. Moreover, the converter has been tested over

a wide supply range from 250mV to 600mV (Fig. 12).

TABLE I: Performance Summary

VDD 250 mV 300 mV

Technology standard CMOS 0.13µm twin well

Threshold voltage Vtn = 270mV, Vtp = -280mV

DM Input range 200 mV 240 mV

CM Input range rail to rail

Total Power consumption 7.5µW 18.3µW

Power consumption analog 4.825µW 9.36µW

Power consumption digital 2.675µW 8.94µW

Sampling Frequency 1.4 MHz 2.8 MHz

Bandwidth 10 kHz 20 kHz

OSR 70 70

Peak SNDR 61 dB 61.4 dB

Die Area 0.3375 mm2

Temperature Range 20 - 100 ◦C 0 - 100 ◦C

101

102

103

104

105

−140

−120

−100

−80

−60

−40

−20

0

PSD(dB)

f (Hz)

Window = HanningN = 140000

(a) f = 500Hz

101

102

103

104

105

−140

−120

−100

−80

−60

−40

−20

0

PSD(dB)

f (Hz)

Window = HanningN = 140000

(b) f = 10 kHz

Fig. 10: Measured power spectral density for a sinusoidal input

with 200mVpp at VDD = 250mV.

−20 0 20 40 60 80 100

0

20

40

60

SNDR(dB)

Temperature (◦C)

VDD = 250 mV

VDD = 300 mV

Fig. 11: SNDR vs. temperature for a 500 Hz sinusoidal input.

0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6

62

64

66

68

70

SNDR(dB)

VDD (V)

input = 200mVppinput = 0.8 · VDD

Fig. 12: SNDR vs. supply voltage for a 500 Hz sinusoidal

input.

V. CONCLUSION

A 250mV ∆Σ converter was designed using a switched

capacitor biasing scheme that allows to bias the inverter gates

independently. Therefore, large overdrive and bias current

stabilization over PVT is accomplished. With an OSR of 70

the converter achieves 61 dB SNDR in 10 kHz BW for a

differential mode input signal of 200mVpp at a supply voltage

of only 250mV. Raising the power supply to 300mV allows

to increase the temperature range and bandwidth.

REFERENCES

[1] F. Michel and M. Steyaert, ”A 250 mV 7.5µW 61 dB SNDR SC ∆Σ

Modulator Using Near-Threshold-Voltage-Biased Inverter Amplifiers in130 nm CMOS ,” IEEE J. Solid-State Circuits, vol.47, no.3, pp. 709-721,Mar., 2012.

[2] K.P. Pun, S. Chatterjee, and P.R. Kinget, ”A 0.5V 74-dB SNDR 25-KHzcontinuous-time delta-sigma modulator with a return-to-open DAC,” IEEEJ. Solid-State Circuits, vol.42, no.3, pp. 496-507, Mar., 2007.

[3] Y. Tang and R. L. Geiger, ”A 0.6 V Ultra Low Voltage OperationalAmplifier,” Proc. IEEE International Symposium on Circuits and Systems,vol. 3, pp. 611-614 , May, 2002.

[4] F. Krummenacher, E. Vittoz and M. Degrauwe, ”Class AB CMOSamplifier for micropower SC filters,” Electronic Letters, vol.17, no. 13,pp. 433-435, June, 1981.

[5] F. Pan, T. Samaddar, ”Charge Pump Circuit Design,” McGraw-Hill, 2006.[6] Y. Chae, I. Lee and G. Han, ”A 0.7V 36µW 85dB-DR Audio ∆Σ

Modulator using class-C inverter,” IEEE ISSCC Dig. Tech. Papers, pp.490-491, Feb., 2008.

[7] Y. Chen, K.P. Pun and P. Kinget, ”A 0.5-V 81.2 dB SNDR audio-bandcontinuous-time Delta-Sigma modulator with SCR feedback,” SpringerAnalog Integrated Circuits and Signal Processing, Jan., 2011.

978-1-4673-0821-2/12/$31.00 ©2012 IEEE