A Process-Scalable RF Transceiver for Short Range Communicationin 90 nm Si CMOS

Atsushi Shirane, Mototada Otsuru, Sang_yeop Lee, Shin Yonezawa,Satoru Tanoi, Hiroyuki Ito, Noboru Ishihara, and Kazuya Masu

Solutions Research Laboratory (SSRL), Tokyo Institute of Technology4259-S2-14 Nagatsuta, Midori-ku, Yokohama 226-8503, Japan

Abstract—This paper presents the RF CMOS transceiver thatpotentially has the process scalability in terms of area and supplyvoltage. The proposed transceiver does not contain any inductorand employs inverter-based topology for attaining scalability andlarge voltage headroom. The prototype transceiver for short-range communication fabricated in 90 nm Si CMOS process hasarea of 0.2mm2 and achieves 500 Mb/s communication at 1 Vsupply voltage. The transmitter with the new linearity compen-sation technique provides EVM of less than −28 dB at −5dBmoutput from 0.5 to 2.5 GHz range. The receiver employs activepeaking and cherry-hooper techniques and realizes sensitivity of−60 dBm and dynamic range of 50 dB at 1 GHz.

Index Terms—CMOS integrated circuit, inductor-less, ra-diofrequency integrated circuits, scalable, transceivers

I. INTRODUCTION

One of the significant issues for an RF CMOS transceiveris that costs, e.g. area and power, of RF CMOS circuitscannot be improved with technology scaling. The first issue islow density integration and large area of RF CMOS circuitsbecause of huge passive components such as an inductor whichis hardly shrunk by scaled CMOS process [1]. Another isvoltage scaling of the power supply. Supply voltage is below1 V in recent CMOS LSIs and must be lowered in finer processand transceivers for ultra-low power applications. However,this degrades voltage headroom and also complicate noisedesign.

Potential solution is inductor-less and inverter-based RFcircuit technologies [2], [3]. The former technique is obviouslynecessary for area saving and scaling, however it woulddegrade voltage headroom. The inverter-based circuit topologycan improve the headroom due to near rail-to-rail output rangeand has possibilities of performance improvement by processscaling [3]. The present paper proposes the inductor-less andinverter-based scalable RF CMOS transceiver for short-rangehigh-speed wireless communication. We also propose thenew linearity compensation technique for the transmitter. Theinverter-based receiver utilizing active-peaking and cherry-hooper techniques is presented. It is shown that the prototypein 90 nm Si CMOS process has area of 0.2mm2 and achieves500 Mb/s communication.

The paper is organized as follows. Section II describes anoverview of the proposed transceiver and design of transmitterand receiver. Measured performances are shown in section III,and this paper is concluded in section IV.

TABLE ISPECIFICATIONS OF TEST WIRELESS SYSTEM

Datarate 500 Mb/sModulation QPSK

Frequency range 0.5 – 2.5 GHzDistance within 1 m

Supply voltage 1 V

II. DESIGN OF THE SCALABLE RF TRANSCEIVER

A. Transceiver overview

Table I shows the specifications of the test wireless systemin the prototype design. The block diagram of the proposedRF transceiver is described in Fig. 1. The receiver employsa direct conversion architecture, consisting of a single-endedLNA, a single to differential conversion circuit and a currentmode passive mixer, which realizes quadrature demodulationand down conversion. The transmitter can be separated intoRF part and a baseband part. The baseband part makes a highspeed QPSK symbol from an input data and a clock signal.Simple baseband filtering is realized by the particular DAC.The output signals of the DAC are input to the RF part directly.The RF part modulates and up-converts to carrier frequencydirectly with quadrature passive mixer, then the driver am-plifier amplifies the modulated signal and matches the outputimpedance to 50Ω. Quadrature local signals are generated byusing an external signal which is twice the desired frequency.The external siganl is converted to a differential signal by thesingle to differential circuit (S2D), then by dividing the signals,the four phase quadrature signals are distributed to the TX andthe RX.

B. Transmitter

In the baseband part, the input clock frequency is 500 MHz.By dividing the clock, the QPSK symbol of 250 Mb/s isgenerated from the datarate of 500 Mb/s. The symbol signalsare shifted by T/4 = 1 ns (T and symbol rate are reciprocal)with the flip-flops to which the 500 MHz clock signal are input.The three phase shifted signals are input to the DAC, so thatthe analog signal as shown in Fig. 2 is obtained to suppressthe non-desired sideband spectrum. The DAC operation is asfollows. When all three signals are low, all p-MOSFETs areon and all n-MOSFETs are off, so the output is equal to thepower supply voltage VDD. When only the first signal ϕ−T/4

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RXInput

TXOutput

RX IQOutput

LOInput

TXDataInput

TXClockInput

LNA S2D OTA QDEM TIA Buffer

DriverAmp

QMOD

DAC

S2D

gm

FFDE-MUX

÷2

÷2

Fig. 1. Block diagram of the proposed transceiver

is high, M1 is off and M2 is on. Then, n-MOSFET "M2"and p-MOSFETs "M3, M4 and M7" are balanced so that thedesired voltage of V1 is realized as shown in Fig. 2. Similarly,p-MOSFET "M7" and n-MOSFETs "M2, M5 and M6" arebalanced in the next step. In the Fig. 2, the bias voltage ofVbias_p and Vbias_n is used for the compensation of the processvariation. In the prototype design, the bias voltage is controledmanually to optimize the sideband suppression. When all threesignals are high, the output voltage is 0 V. By using the DAC,digital signal is converted to analog signal and the high speedbaseband signal spectrum can be limited without DSP andgeneral DAC.

Fig. 3 shows the schematic of the RF part. Each DAC whichis explained above generates differential IQ baseband signals,then the four signals are input to the quadrature modulator(QMOD). The QMOD is composed of four complementaryswitches, which are provided with quadrature local signalsfrom the local divider. Although generally passive mixerconsists of only n-MOSFETs, the complementary switches areemployed in this circuit because the peak-to-peak amplitudeof the baseband signals are rail-to-rail. Large baseband signalscontribute high SNR and enable higher frequency operation ofRF transmitter because of lower gain in the RF part. The driveramplifier is inverter-base topology, to enlarge the dynamicrange without an inductor. In the driver amplifier of Fig. 3, twoinverters add the quadrature signals in current domain. Thelow power supply voltage and inductor-less amplifier makeit difficult to achieve high linearity. Thus, the linearity ofthe driver amplifier is compensated by the circuit as shownin Fig. 3. The linearity of the driver amplifier is degradedaround the peak of the large signal as shown in Fig. 4 (a).The linearity compensation circuit consists of QMOD andonly two transistors, and its operation is as following. First,reverse phase of baseband signals are input to the QMOD inthe compensation circuit in order to match the phase of theinverse signal by the driver amplifier. The output of the QMODin the compensation circuit is biased to power supply voltageand ground, then, two different biased signals are input to M1of n-MOSFET and M2 of p-MOSFET respectively as shown inFig. 3. From Fig. 4 (b), it is found that the gate-source voltage

VDD

to RF

Vbias_p

Vbias_n

1

1

2

M1

M2

M3

M4

M5

M6

M7

M8

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φ+T/4

φ0

0V

VDDφ

T/4

V1

V2

Fig. 2. Schematic of DAC in transmitter

0°

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90°

270°

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Linearity compensationQMOD Driver Amp

M1

M2

TX

_o

ut

Fig. 3. Schematic of RF transmitter

VDD

VSS

ideal

degraded

M1 gate

M2 gate

M1 & M2source

(a) (b)

Fig. 4. Detail of linearity compensation

of M1 is larger around the highest voltage, and the gate-sourcevoltage of M2 is larger around the lowest voltage. This givesrise to pull up and pull down the peak of the output signalof the driver amplifier. The linearity compensation circuitachieves 6 dB third inter modulation (IM3) improvement at−5 dBm output power in the simulaion results.

C. Receiver

Fig. 5 shows the schematic of the proposed receiver. Thesingle-end LNA employs two stage inverter-based topologyand two step gain control to obtain wide dynamic range.

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RXInput

=

0°

0°

180°

90°

90°

270°

TIA+Buffer

OUT_I

OUT_I

OUT_Q

OUT_Q

SW_HG

SW_LGSW_LG

SW_LG

LNA S2D & OTA QDEM

Active peaking loop

Fig. 5. Schematic of the receiver

In addition, the active peaking and cherry-hooper techniquebroadens the bandwidth of the LNA [3]. The two step gain isrealized by switching the feedback resistance of the inverterswith SW_LG of control bit in Fig. 5 and by changing theamount of feedback with SW_HG or SW_LG. The designedLNA gain is 16 dB and 0 dB. Differential signaling is preferredin terms of second-order distortion and power supply andsubstrate noise. In this work, the S2D which consists of onlyinverters is chosen. The S2D of this active type is more suitablefor scalable circuit design than using passive balun because ofthe small occupied area. The inverters which are connected tothe passive mixer are the OTA. In these ineverters, the outputimpedance is enlarged by using large feedback resistancevalue. The current mode passive mixer is driven by the OTA,and the TIA converts to voltage mode signal. The employmentof the current mode passive mixer saves voltage headroom andimproves linearity in the low power supply voltage [4].

III. MEASUREMENT RESULTS

The proposed transceiver was fabricated using a 90 nm SiCMOS process. Fig. 6 shows the micrograph of the circuitwhich occupies an active area of 370µm times 530µm. Thefabricated transceiver was mounted on a glass-epoxy board.

Fig. 7 shows the modulated spectrum by the transmitter at500 Mb/s, and the output power within 500 MHz is −5 dBm.Comparing the spectrums with or without the sideband sup-pression by the DAC, about 10dB improvement was achieved.In the RF part of the transmitter, the measurement and sim-ulation results of two-tone test are shown in Fig. 8. In thisfigure, OIP3 is calculated from an output power and an IM3power at each input voltage of the QMOD. The measurementand the simulation results of OIP3, Pout and IM3 are wellmatched, and the maximum OIP3 is 6 dBm at output powerof −5 dBm. Fig. 9 shows the frequency characteristics of thecarrier leak, the image rejection and the EVM at 500Mb/s,in which 2.5GHz is the maximum operation frequency of thedivider.

370μm

RX RF

LO

IQ Gen.

TX BBTX RF

53

0μ

m

Fig. 6. Micrograph of the fabricated transceiver

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ow

er

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m)

Frequency (GHz)

Ou

tpu

t p

ow

er

(dB

m)

Frequency (GHz)

(a) (b)

Fig. 7. (a) QPSK modulated spectrum without adjustment (b) QPSKmodulated spectrum at 500 Mb/s with adjusted bias in DAC QPSK modulatedspectrum without adjustment

The performance of the receiver at 1 GHz is as follows.The conversion gain is 34 dB and 11 dB, and the IIP3 is−30 dBm and −7 dBm at high and low gain mode respectively.The minimum NF is 6 dB at high gain mode. The receiverfrequency range is 0.5 to 1.5 GHz and is limited by largerpackage inductance than we expected.

The sensitivity and dynamic range of the receiver wasmeasured with the modulated signal by the transmitter. TheRX outputs the baseband IQ signals directly, thus, EVM wasmeasured as a barometer of the modulation and the demod-ulation instead of BER. Fig. 10 depicts the characteristicsof the demodulated signals, IQ and eye diagrams, basebandspectrum and detail of EVM. This Figure indicates that thetransmitter and the receiver realize accurate modulation anddemodulation respectively. Fig. 11 shows EVM versus the RXinput power. This measurement was done by connecting TXto RX with cables with the aid of variable attenuator. If thecommunucation permits EVM of −20 dB, the RX sensitivity is−60dBm, and dynamic range is about 50 dB. The performanceof the proposed transceiver is summarized in the table II.

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Input voltage of QMOD (mVp-p)

IM3 meas.

IM3 sim.

Pout sim.

Pout meas.

OIP3 sim.

OIP3 meas.

10000

Fig. 8. Measurement and simulation results of OIP3 at 1 GHz carrier

EVM (dB)

Image rejection (dBc)

Carrier leak (dBc)

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0 1 2 3LO frequency (GHz)

(dB

, d

Bc)

Fig. 9. EVM, carrier leak and image rejection versus LO frequency intransmitter

Fig. 10. Measurement results of the demodulated signals at high gain mode,−43 dBm input power, 1 GHz carrier, 500 Mb/s datarate and PRBS11. EVMis −28 dB.

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-80 -60 -40 -20 0

EV

M (d

B)

RX input power (dBm)

High gain

Low gain

Fig. 11. EVM versus RX input power at 1 GHz carrier

TABLE IISUMMARY OF MEASUREMENT RESULTS

Supply voltage 1 VDatarate 500 Mb/s

Power consumption TX:11.9 mW, RX:35.3 mWLO and RX Buffer:35mW

Frequency range TX:0.5–2.5 GHz, RX:0.5–1.5 GHzRX sensitivity −60dBm @EVM=−20 dB

RX dynamic range 50 dBTX output power −5 dBm

Active area 0.2mm2

IV. CONCLUSION

This paper proposed the scalable RF transceiver withinductor-less and inverter-based RF circuit techniques. Thenew linearity compensation technique for the transmitter waspresented. The LNA employed active peaking and cherry-hopper techniques for improving bandwidth. The prototypetransceiver was fabricated in 90 nm Si CMOS process. Thetransmitter outputs −5 dBm with EVM of −28 dB. The re-ceiver sensitivity and dynamic range are −60 dBm and 50 dBrespectively at 1 GHz carrier, 500 Mb/s, and 1 V supply volt-age. The active area of the transceiver is 0.2mm2.

ACKNOWLEDGMENTS

This work was partially supported by STARC, MIC.SCOPE,KAKENHI, NEDO, and VDEC in collaboration with AgilentTechnologies Japan, Ltd., Cadence Design Systems, Inc., andMentor Graphics, Inc.

REFERENCES

[1] A. Matsuzawa, “RF-SoC Expectations and Required Conditions,” IEEETrans. Microw. Theory Tech., Jan. 2002.

[2] A. Mirzaei, et al, “A Low-Power Process-Scalable Super-HeterodyneReceiver With Integrated High-Q Filters,” IEEE J. Solid-State Circuits,vol. 46 NO.12, Dec. 2011.

[3] T. Nakajima, et al, “A Scalable Wideband Low Noise Amplifier consist-ing of CMOS Inverter Circuits for Multi-Standard RF Receivers,” SCS2009.

[4] J. Zhan, et al, “A Broadband Low-Cost Direct-Conversion ReceiverFront-End in 90 nm CMOS,” IEEE J. Solid-State Circuits, vol. 43 NO.5,May 2008.

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