An 8Ω, 1.75W, 95% Efficiency, 0.004% THD+N Class-D Amplifier with a Feed-Forward ADC and

Feedback Filters

Xicheng Jiang, Jungwoo Song, Darwin Cheung, Minsheng Wang and Sasi Kumar Arunachalam Broadcom Corporation, Irvine, CA 92617, USA, xicheng@broadcom.com

Abstract— An integrated ultralow EMI Class-D amplifier with a feed-forward ADC and feedback filters is demonstrated in a 180 nm CMOS and wire-bonded package. Circuit and architecture techniques, which enables 1.75W into an 8 Ohm speaker, 105 dB dynamic range, 95% efficiency, 0.004% THD+N, and 15.4 dB margin beyond the EN55022 Class B standard, are discussed.

Keywords—Audio; Class-D; Amplifier; Feed-forward; Feedback; Filter; ADC; EMI; Efficiency; THD+N; Dynamic Range

I. INTRODUCTION Class-D audio amplifiers [1–5] are increasingly needed in

portable devices driven by a lithium battery (2.5V–5.5V). Smartphones and tablets with rich multimedia require speaker drivers to provide high output power, high efficiency, high dynamic range and low distortion. Previously reported Class-D amplifiers [1, 3] can achieve 1.5W peak output power into an 8Ω speaker with a standalone wafer-level chip-scale package [1, 3] and a supply boost [1]. However, the low-cost integrated solutions with wire-bond packages [4, 5] provide only 1W or less peak output power. Moreover, class-D amplifier THD+N performance is limited by the intermodulation distortion and the disturbance caused by the rail-to-rail switching output. The intermodulation can be eliminated by sampling and holding the signal at the output of the loop filter [3]. The input common-mode disturbance can be reduced by a differential-signaling front-end with a complex switching scheme [2]. Nevertheless, the loop filter [1–5] suffers from processing the high-frequency feedback signal. This paper presents an improved Class-D architecture with a feed-forward ADC and feedback filters. The integrated amplifier with a wire-bond package achieves 95% efficiency, 105 dB dynamic range, 0.004% THD+N and 1.75W into an 8Ω speaker without supply boost.

II. CLASS-D AMPLIFIER ARCHITECTURE The Class-D amplifier with direct battery connection,

shown in Figure 1, consists of a feed-forward ADC path, a feedback filter path, analog PWM generation circuits, and an output stage that directly interfaces with an external speaker. The large switching current through the speaker coil coupling

+ –

+–

+–

PWMGEN

LoopFilter

Feed–ForwardADC Path

Feedback Filter Path

Pre–Driver

RFDBK

RIN

Fig. 1. Class-D amplifier architecture

with the parasitic inductance from the wire-bond package tends to induce large overshoots and undershoots at the amplifier output. To make the device operate reliably, conventional designs reduce the output signal swings by an amount equivalent to the overshoot or undershoot. As a result, existing Class-D amplifiers with wire-bond package have very limited output power capability. To overcome this limitation, the overshoots and undershoots are suppressed by controlling the slew rate of the output transition edge in this design. The output-switching edge rate is controlled by adjusting the transition time of the pre-driver output. The pre-drivers in Figure 1 were realized by digital gates with additional source resistance. The slew rate of the pre-driver output is determined by the source resistance and gate capacitance of the power transistor. In addition, the switching edge rate control reduces electromagnetic interference (EMI) and enables the system to meet the EN55022 Class-B standard without any external components. The loop filter output in conventional Class-D amplifiers [1–5] includes signal and other non-idealities such as the supply noise. Consequently, the loop filter can easily saturate before the Class-D output reaches the maximum achievable level. The design described in this paper, in contrast, uses the feed-forward path to process the signal, using the loop filter to integrate only the difference between the input and the feedback signals. The loop filter, therefore, mainly

369978-1-4799-0280-4/13/$31.00 c©2013 IEEE

responds to errors injected into the loop. This design significantly extends the loop filter operation range to support a much larger signal level and, thus, larger output power capability. The loop filter, as shown in Fig.2, consists of a chain of four integrators with a resonant loop. The 4th-order architecture was designed for high loop gain to sufficiently attenuate the subharmonic PWM tones aliased into the audio band. The simulated supply ripple transfer function of the closed-loop amplifier with this loop filter is shown in Fig.3. The loop filter bandwidth is optimized to achieve minimum PWM pulse width at zero input signal and, thus, minimum quiescent power consumption. To avoid PSRR performance degradation due to the feed-forward architecture, the loop filter, feedback and feed-forward paths are powered from an internal LDO.

+-

-+

+-

-+

+-

-+

+-

-+

Fig. 2. Analog loop filter structure

Fig. 3. Supply ripple transfer function

III. FEED-FORWARD ADC PATH The feed-forward path, as shown in Fig. 4, consists of an

ADC, digital PWM and analog ramp generators. The accuracy requirements for the ADC and analog ramp circuits are relaxed because the feedback loop also attenuates any errors introduced

in the feed-forward path. The counter-based ADC requires only one comparator. The DAC elements matching can easily meet the 6–7 bit accuracy requirement. With a 13 MHz clock rate, the ADC has a relatively low latency compared to the Class-D modulation frequency at 722 kHz. The digital PWM generator [6] converts the ADC output to a digital PWM signal. The ramp generators transform the digital PWM pulses into analog ramp signals by charging and discharging capacitors with constant current sources (Fig. 4).

ADC DigitalPWM

Ramp Up/DownGen

VRUP

DPWM UpLogic

VRDN

DPWM DownLogic

DACCounter

VRUP

VRDN

DPWM VRUPVRDN

AIN

DOUT

DOUT

DPWM

AIN 0

0+1

-1

Fig. 4. Feed-Forward ADC path

A ramp-up signal (VRUP) starts ramping up when the digital PWM (DPWM) changes from 0 to 1 or from -1 to 0. A ramp-down signal (VRDN) starts ramping down when DPWM changes from 1 to 0 or from 0 to -1. The feed-forward ramp signals (VRUP and VRDN) are compared against the loop filter output to generate the final Class-D PWM output. The comparators in Fig. 1 detect zero-crossings. The time difference between zero-crossings is converted to a ternary PWM signal by using the timing information of the rising edges of the two comparator outputs. The final PWM pulse is finely adjusted from the feed-forward digital PWM pulse to correct errors from the battery disturbance and other sources.

IV. FEEDBACK FILTERS To reduce the high frequency intermodulation distortion

associated with direct feedback, and to eliminate the loop filter input common-mode disturbance from the Class-D output that has a rail-to-rail common-mode variation, a feedback path, which consists of filters and an active amplifier with output common-mode regulation, is proposed and shown in Fig. 5. The Class-D output is filtered by the linear RC filter formed by

370 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)

R1 and CS. The RC filter bandwidth is set high enough to ensure the loop stability. Shunt resistors (RS) are added to attenuate the filtered Class-D signal to a level that can be easily accommodated by the active feedback amplifier (A). With common-mode feedback to both first and second stage of the amplifier, the common-mode loop bandwidth and stability are both improved. The resistor (R) and capacitor (C) around the active amplifier provide additional filtering. The amplifier differential output with a constant common-mode is then fed to the input of the loop filter. The attenuation factor from the shunt resistor (RS) is compensated by adjusting the value of resistor RFDBK (in Fig. 1).

R1R2

RC

C

RRS CS

A Class–DOutput

VIP VIN

VCMO

VOP VON

Fig. 5. Feedback filter path

V. EXPERIMENTAL RESULTS The Class-D amplifier is measured with an 8Ω resistor in

series with a 68 µH inductor while other power management units are operating. The design supports battery voltages from 2.5V to 5.5V. Figure 6 shows a plot of the A-weighted THD+N with a 1-kHz input signal. Over 105 dB dynamic range is achieved. At -40 dB THD+N, the output power corresponds to 1.75W. Figure 7 shows the measured THD+N vs. output power with different battery voltages. 750mW output power is achieved with 3.6V battery voltage. Figure 8 depicts the measured output spectrum with a 1 kHz input signal and 1.5W output power. Better than 0.01% THD is achieved. The class-D efficiency versus output power is shown in Fig. 9. A peak efficiency of 95% is achieved at 1.75W power output. The radiated electromagnetic emission was measured with a commercial smartphone that uses this Class-D amplifier. The system meets the EN55022 Class B standard up to 1 GHz with a 15.4 dB margin, as shown in Figure 10. Table 1 summarizes the measured performance and compares it to recent publications. Fabricated in a 0.18 µm standard CMOS process, the Class-D amplifier (Fig.11) is packaged in a low-cost wire-bonded package.

−100

−10

−90

−80

−70

−60

−50

−40

−30

−20

10n 31μ 1m 1 2Output Power (W)

100n 10μ 100μ 10m 100m

THD+

N (d

B)

VBAT=5.5V

Fig. 6. Measured THD+N vs. output power with 5.5V battery voltage

Fig. 7. Measured THD+N vs. output power with different battery voltage

2 204 6 8 10 12 14 16 18Frequency (kHz)

0−150

+10

−140−130−120−110−100

−90−80−70−60−50−40−30− 20−10

0

Ampl

itude

(dBV

)

1.5W output power8Ω load<0.01% THD+N

Fig. 8. Measured FFT spectrum with 1.5W output power

2013 IEEE Asian Solid-State Circuits Conference (A-SSCC) 371

Fig. 9. Measured Class-D efficiency

Fig. 10. Measured radiation result in a smartphone system with this Class-D amplifier

TABLE I. PERFORMANCE SUMMARY AND COMPARISON

Fig. 11. Die micrograph

VI. CONCLUSION

In conclusion, this paper presents an audio Class-D amplifier with 105dB dynamic range, 95% peak efficiency, and 1.75W output power into an 8Ω loudspeaker in 0.18μm CMOS. The feed-forward ADC path and the switching edge rate control help to achieve the higest reported output power in a wire-bonded package. The feedback filter path reduces the high frequency intermodulation distortion and eliminates the loop filter input common-mode disturbance. As a result, 0.004% minimum THD+N is achieved. The 4th-orde loop filter with high loop gain enables 96dB PSRR at 217 Hz. Furthermore, the Class-D amplifier meets EN55022 Class B radiation standard with a 15.4dB margin.

ACKNOWLEDGMENT The authors would like to thank their colleagues Todd

Brooks, Jianlong Chen, Felix Cheung, Iuri Mehr, John Platenak and Nir Matalon for their valuable contributions.

REFERENCES

[1] A. Nagari et al., “An 8Ω 2.5W 1%-THD 104 dB(A) dynamic range Class-D audio amplifier with an Ultra-Low EMI system and current sensing for speaker protection,” ISSCC Dig. Tech. Papers, pp. 92–93, Feb. 2012.

[2] ] S. Kwon et al., “A 0.028% THD+N, 91% power-efficiency, 3-level PWM Class-D amplifier with a true differential front-end,” ISSCC Dig. Tech. Papers, pp. 96–97, Feb. 2012.

[3] M. Teplechuk et al., “Filterless integrated Class-D audio amplifier achieving 0.0012% THD+N and 96 dB PSRR when supplying 1.2W,” ISSCC Dig. Tech. Papers, pp. 240–241, Feb. 2011.

[4] S. Samala et al., “45 nm CMOS Class-D audio driver with 79% efficiency and 100 dB SNR,” ISSCC Dig. Tech. Papers, pp. 86–88, Feb. 2010.

[5] S. Ramaswamy et al., “A high-performance digital-input Class-D amplifier with direct battery connection in a 90 nm digital CMOS process,” ISSCC Dig. Tech. Papers, pp. 436–437, Feb. 2008.

[6] M. Wang et al., “A 120 dB Dynamic Range 400 mW Class-D speaker driver with 4th-order PWM modulator,” IEEE Journal of Solid-State Circuits, Vol. 45, pp. 1427–1435, Aug. 2010.

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