A 0.0354mm2 82 W 125KS/s 3-Axis Readout Circuit for Capacitive MEMS Accelerometer

Kelvin Yi-Tse Lai1, Zih-Cheng He, Yu-Tao Yang, Hsie-Chia Chang2 and Chen-Yi Lee3 Department of Electronics Engineering and Institute of Electronics

National Chiao-Tung University Hsinchu, Taiwan

Email: {1kelvin, 2hcchang, 3cylee}@si2lab.org

Abstract—In this paper, we propose a power/area-efficient capacitive readout circuit for the Micro-Electro-Mechanical Systems (MEMS) sensor of 3-axis accelerometer. The proposed architecture is different from other traditional structures by exploiting true capacitive-to-digital converter (CDC) without Analog-to-Digital Converter (ADC). The proposed CDC can differentiate the bidirectional 125KS/s 80-level accelerations between 8g and support the 4-level adjustable resolutions of 0.1g/ 0.2g/ 0.4g/ 0.8g for each axis. The proposed readout circuit with 0.0354mm2 area is fabricated in UMC 0.18um CMOS-MEMS process. Experimental results show power consumption is 50uW with 1.8V supply voltage for 1-axis (FOM=3.84pJ), 82uW for 3-axis (FOM=2.1pJ) under 125KHz of sampling frequency and 0.1g acceleration sensitivity for 0.2fF MEMS capacitance change.

I. INTRODUCTION The accelerometer sensors are very popular in mobile

devices, such as cellular phone and tablet PC. These accelerometers are classified into three kinds: piezoelectric, piezoresistive and capacitive accelerometers [1]. The differential capacitive accelerometer has some advantages such as zero static bias current, the capability of high sensitivity, differential capacitance output which against the common mode influence, excellent thermal stability, and having good ability for low-power applications [2]. Based on the above advantages, a low-power capacitive accelerometers, including capacitance-to-voltage and ADC, have been presented in [3].

In [4], Haluk Kulah et al. improve the dynamic range and sensing resolution by exploiting multi-step architecture. C. Condemine et al. present a capacitive comb accelerometer [5], which combines delta-sigma interface and an 8th-order compensator which includes lead, lag and proportional contributions, to improve process-voltage-temperature (PVT) variation and enhance the conversion linearity. Jiangfeng Wu et al. [6] employ transistor sizing based on capacitance matching between circuit and sensor to minimize sensor noise floor. The PVT variation can be minimized by using the above

technologies but power dissipation and circuit area remain to be reduced, especially for multi-axis and multi-sensor solutions. Matii Paavola et al. employ the algorithmic capacitance ratio-independent ADC and voltage scaling technique to minimize power dissipation under acceptable silicon area [3]. In this paper, we propose a new power/area efficient readout circuit which has the following features: (1) exploiting event driven approach to reduce power consump-tion, (2) hardware sharing to minimize area for multi-axis, and (3) adjustable resolutions for different applications.

The remainder of this paper is organized as follows: Section 2 briefly describes the available CDC techniques. In section 3, the circuit configuration of the proposed CDC is described. Section 4 shows the experimental measurement result and comparison of the CDCs. Finally, the conclusion is drawn in section 5.

II. BACKGROUND

Fig. 1 The structure of traditional MEMS system

Fig. 1 shows the structure of accelerometer in the traditional MEMS system. In this structure, it’s separated into two blocks, MEMS sensor and application platform. With the intermediate mass moving in the MEMS sensor, the parasitic capacitances on both sides of mass will be changed. In order to obtain the difference between these two differential capacitances, we use the sensing circuit to transfer capaci-tances into voltage identification. Then, the ADC converts the generated voltage into the corresponding digital code. Finally, the digital code will be used for digital signal processor (DSP) or other applications in system platforms.

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Fig. 2 The illustration of traditional capacitive readout interfaces

In traditional capacitive readout circuits [1-19], there are some kinds of methods, including capacitance to voltage [1-8, 10, 12-14, 16-19], capacitance to time [9, 11] and capacitance to frequency converters [15]. Furthermore, the capacitance to voltage circuits can be classified into four categories: differential, synchronous detection, switched capacitance and sigma-delta modulator. Finally, the last stage digitalizes the related voltage, time or frequency as the digital codes. These three conversion techniques will be briefly discussed as follows:

1) Sigma-Delta Modulation In Fig. 2 (a), Sigma-Delta Modulation ( ) is a well-

known technique to enhancing high resolution and sampling rate and supplying high SNR due to the compensation from the digital-to-analog converter (DAC). Nevertheless, the high power consumption is always concerned.

2) Pulse-Width Modulation The pulse-width modulation (PWM) converts the

capacitance into the significant time pulse, and employs the voltage comparator to differentiate the discrepancy in the corresponding charging time. The advantages are high resolution or sensitivity for capacitance difference and low power consumption. But the sampling rate and response time are the bottleneck due to the time-consuming RC charging ability, especially for the parasitic capacitance. The illustration of PWM is drawn in Fig. 2 (b).

3) Frequency Modulation Frequency modulation (FM) represents the impact

between the sensed capacitance with the interrelated oscillator frequency. After the frequency comparator for the OSCsens. and the OSCref. in Fig. 2 (c), the frequency difference is readout with the counter or frequency quantizer. Unfortunately, the weak conversion linearity due to the reciprocal cap.-to-freq. relationship, low sampling rate and high power consumption from the always-on oscillators will be usually considered.

In view of those above analyses, we propose a fully differential, low power, high sampling rate, event-driven capacitive readout interface for the 3-axis accelerometer. Different from the traditional CDCs, our proposal: (1) consumes the dominating power only when the differential mode capacitance appears, (2) ignores the parasitic capacitance and only converts the differential mode capacitance, (3) has adjustable resolutions for each axis, (4) achieves multi-axis shared readout architecture.

III. THE PROPOSED FULLY DIFFERENTIAL CAPACITIVE READOUT INTERFACE

In this paper, we demonstrate an accelerometer, employing the proposed MEMS mechanism from industry [9], and propose the fully differential, low power, high sampling rate and adjustable resolutions 3-axis shared CDC. For the specification of the finger-type accelerometer mechanism, the sensing range is 8g of acceleration and the differential mode capacitance ( C) variation is 200af/0.1g. The parasitic capacitance in the steady state, called the common mode capacitance (C0), is around 270ff. With the 0.1g acceleration, the sensed capacitances of (C+, C-) are (270ff+0.1ff, 270ff-0.1ff). Unlike those traditional CDCs, the proposed CDC should only readout the significant differential capacitance, ignore the common capacitance, and just consume the main conversion power in the differential mode. The novel CDC architecture and the corresponding timing diagram are shown in Figs. 3 and 4.

Fig. 3 The architecture of proposed shared CDC

for 3-axis accelerometer.

110 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)

In the front-end of CDC in Fig. 3, we employ the concept of Wheatstone bridges with the corresponding M scale resistances to amplify the Cs into time differences. In the nodes of (a), (b) and (c), the CDC detects the C and disregards the C0. Those amplified time differences of the differential Cs enables the ring oscillator, which has already been calibrated to minimize the PVT variation and generates the high clock-frequency, to starts counting in the final conversion stage. The CDC also employs the phase detection technique to determine the acceleration directionality.

When the MEMS mechanism is accelerated with the force , the finger type electrode results in the differential mode capacitance of C. In Fig. 4, the CDC senses the 3-axis acceleration signal, it starts converting the Cs into the corresponding time pulses, hence the “WAKE” signal triggers the high-frequency clock generator to convert the significant time pulses into the corresponding digital codes. Yet the CDC detects the end edge of the “WAKE” signal, it will turn off the ring oscillator to save much power consumption and enter standby mode. Furthermore, the distinctive output in acceleration and direction makes our proposal more suitable for system-level integration than the other works [1-19].

Fig. 4 The timing diagram of readout illustration

In practical ADC based approaches, the acceleration is defined as the number of Nbias±Nacc and Nacc takes a half ratio in output code, where Nbias & Nacc stand for steady output value and acceleration value. When system extracts the current acceleration from the ADC, the subtraction is requested for acceleration feature extraction.

For parasitic capacitance offset and PVT variation, the effective bandwidth will be reduced due to the Vbias drift. In Fig. 4, the C0 offset and PVT variation influence the time of steady state point and decrease the sampling rate. For the net (a-c), the differential CDC has the good ability to maintain the amplified time pulse and reduces the PVT variation due to the common mode signal rejection. The simulation result of the proposed CDC is shown in Fig. 5.

0

10

20

30

40

50

60

70

80

90

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Out

put C

ode

Differential-Mode Capacitance (fF)

Common-Mode Capacitance Offset(0%, +10%, +20%)

C0=270ff

C0=297ff

C0=324ff

Fig. 5 The conversion result versus parasitic capacitance offset

IV. RESULT AND COMPARISON The layout and die photo of our proposed 3-axis shared

CDC is shown in Fig. 6 and takes 0.0354mm2 in area. Note the common mode capacitance of C0 offset will be regarded for common mode rejection and the few mismatches in differential mode capacitance should be adjusted with the capacitance trimmer.

Fig. 6 The layout & die photo of proposed CDC

In the measurement result, the mismatch of C is around 1.0fF at the steady state. Under the sampling rate of 125KHz, an example in x-axis is shown in Fig. 7. The measurement result is captured by using the Agilent logic analyzer and illustrated that the output code contains the acceleration feature of the C, where C process mismatch has been minimized. In Table 1, the proposed CDC consumes around 50uW in single axis under 1.8V supply voltage. When the 3-axis acceleration readouts simultaneously, it only consumes around 82uW because of the shared ring oscillator. With the equivalent number of bits (ENOB) of 6.7, the figure-of-merit (FOM) result shows that the proposed CDC has low power potential and high sampling rate for multi-axis shared readout interface.

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Table 1. Comparison among Several CDCs

0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39

Accelerometer Digital Codes

Fig. 7 The measurement result of the proposed CDC

V. CONCLUSION In this paper, we propose a 3axis-shared capacitive readout

circuit for the MEMS accelerometer. The proposed CDC can differentiate the bidirectional 125KS/s 80-level accelerations between 8g and support the 4-level adjustable resolutions of 0.1g/ 0.2g/ 0.4g/ 0.8g for different application requirement. The power/area efficient 3-axis readout CDC is fabricated in UMC 0.18um CMOS-MEMS process. Experimental results show the proposed 6.7bit CDC just consumes around 50uW with 1.8V supply voltage for 1-axis (FOM=3.84pJ), 82uW for 3-axis (FOM=2.1pJ) under 125KHz of sampling frequency, implying our proposed CDC can be used to mobile devices very effectively and efficiently.

ACKNOWLEDGMENT The authors thank the SI2 lab members of National Chiao-

Tung University for their fruitful advices. We also thank prof. K.-A. Wen and GSC CO. for the helpful support, CIC for the measurement environment and UMC for advanced IC process.

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