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978-1-4799-0877-6/13/$31.00 ©2013 IEEE
Reduction Method of Number of Electromagnetic Simulation Times for Estimating Output Voltage
at Hard Open TSV in 3D IC
Ei Haraguchi, Masaki Hashizume, Katsuya Manabe,
Hiroyuki Yotsuyanagi Ins. of Tech. and Sci.,
The Univ. of Tokushima Tokushima, 770-8503, Japan [email protected]
Tetsuo Tada Faculty of Science and
Engineering Tokushima Bunri Univ. Shido,769-2193,Japan
Shyue-Kung Lu Dept. of Electrical
Engineering, National Taiwan University of Science and Technology Taipei,106,Taiwan (R.O.C.)
Zvi Roth Dept. of Computer &
Electrical Engineering and Computer Science,
Florida Atlantic Univ. Boca Raton FL,33431,U.S.A.
Abstract—An estimation method of quiescent output voltage of a defective TSV is proposed at which a hard open defect occurs in a 3D IC. The method enables us to reduce the number of times of 3D electromagnetic simulation.
Keywords—3D IC; TSV; open defect
I. INTRODUCTION
3D IC technology will realize size reduction, high performance and low power consumption in portable electronics. Thus, much attention has been paid to 3D IC fabrication[1,2].
Through Silicon Vias(TSVs) are key elements for realizing 3D ICs. There are some kinds of fabrication methods of 3D ICs in which TSVs are used[1,3]. Short defects and open ones can occur independently of the fabrication methods, since there are many TSVs inside a 3D IC[3,4].
Short defects will generate logical errors by providing complement logic values to the defective TSVs. On the other hand, it is not apparent what faulty effects are caused by an open defect in a TSV. Generally, open defects are more difficult to be detected than short ones. Thus, open defects in TSVs are targeted in this paper.
Open defects can be classified into hard open defects and soft ones. In case of a hard open defect, a TSV is divided into two parts completely and they are not connected to each other. The defects can be caused by a crack, a void and so on in fabrication of TSVs.
Open defects may occur inside TSVs and at the edges. Logical errors may be generated by a hard open defect in a TSV[5]. Thus, they should be detected before shipping to a market. However, many TSVs in a 3D IC are adjacent each other at a narrow pitch. Output voltage at a defective TSV depends on logic signals of the neighboring TSV. Thus, hard open defects in TSVs and at the edges are difficult to be detected. We select the hard open defects as our targeted ones in this paper..
Hard open defects may be detected by boundary scan techniques. However, since there are a lot of TSVs in a 3D IC, Design for Testability(DfT) methods and built-in test ones have been proposed so as to shorten the test time[6-10].
In order to detect hard open defects by the test methods, test vectors should be generated. It is required to estimate output voltage of a defective TSV precisely. Also, it is necessary for locating the defective TSV. In order to estimate the voltage precisely, 3D electromagnetic simulation should be performed. However, 3D electromagnetic simulation is time consuming and requires a high computational cost. Thus, it is necessary to develop how to estimate the voltage with a small computational cost.
We show 3D electromagnetic simulation results for output voltage of a defective TSV in which a hard open defect occurs in Section II. We propose an estimation method of output voltage of a hard open TSV based on 3D electromagnetic simulation results in Section III. Since we examined estimation errors of the estimation method, we describe the errors in Section IV.
II. OUTPUT VOLTAGE OF HARD OPEN TSV
An example of a 3D IC is shown in Fig.1. In such an IC, some dies are stacked as shown in Fig.1(a). They are connected with many TSVs as shown in Fig.1(b).
TSVs are neighboring each other. When a hard open defect
(a)side view (b)top view
CoreCircuit
TSV
Fig. 1. 3D IC with TSVs
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occurs inside a TSV, an output signal at the defective TSV may be changed by logic signals of the neighboring TSVs.
We analyzed a layout shown in Fig.2 so as to examine faulty effects caused by an open defect in a TSV that was adjacent to many TSVs. A hard open defect may be caused by a void and a crack in a TSV[4,9]. We inserted a gap whose size was dh at T from the end terminal of TSV5 as a hard open defect.
We derived output voltage of the defective TSV with a 3D electromagnetic simulator, EMPro, and a circuit simulator, ADS that were produced by Agilent technology Co. Ltd. Our analysis circuit is shown in Fig.3. S-parameters of TSVs in Fig.2 are extracted by EMPro. A waveform of TSVout5 is obtained by ADS with the extracted S-parameters.
The derived waveforms of TSVout5 are shown in Fig.4. They are obtained by providing an input vector TV#2 at t=0.5nsec after an input vector TV#1. A High level signal(H) is provided to TSV2, TSV4 and TSV8, and a Low level signal(L) is provided
to other TSVs than them by TV#1. Also, H is provided to TSV2, TSV4, TSV6 and TSV8, and L is provided to other TSVs than them by TV#2.
As shown in Fig.4, TSVout5 depends on logic signals of the TSVs and T. Also, the voltage is greater than 0.5V, when an open defect occurs in TSV5 at T≥20μm. Supply voltage of CMOS inverter gates in Fig.3 is 1.0V and the threshold input voltage is 0.5V. It means that logical error may be caused by logic signals of the neighboring TSVs. Thus, output voltage of a defective TSV5 should be estimated in the test input vector generation process.
TSVout5 when an input vector vT
is provided to the TSVs in Fig.2 can be estimated by (1), since electric filed generated by a logic signal of a neighboring TSV in Fig.2 is superimposed and provided to the defective TSV.
10
15 )(
iiiout VvTTSV
(1)
where αi is a coefficient expressing effects on output voltage of the floating TSV from a logic signal of the i-th TSV. Vi is output voltage of a logic gate whose output terminal is connected to the i-th TSV and is either VL (=0V) or VH (=VDD).
We examined ))(,(5 iSiTSV Lout that was defined by (2) by changing dh and T.
))(,(
))(,())(,(
5
55
iSiTSV
iSiTSViSiTSV
LL
out
LH
outLout
(2)
where SL(i) is a set consisting of the index number of the TSVs except for the i-th TSV, whose input logic signals are L by the application of vT
. ))(,(5 iSiTSV L
Hout and ))(,(5 iSiTSV L
Lout are
quiescent voltages of TSVout5 when an input signal of the i-th TSV is H and L, respectively, under a condition that input signals of all of the TSVs in SL(i) are low level ones.
(e) ))10(,10(5 LH
out STSV
(d) ))9(,9(5 LH
out STSV (c) ))8(,8(5 LH
out STSV
(b) ))6(,6(5 LH
out STSV (a) ))5(,5(5 LH
out STSV
∆T
SV
out
5 [
V]
∆T
SV
out5
[V
]
∆T
SV
out
5 [V
]
∆T
SV
out
5 [V
]
∆T
SV
out
5 [
V]
Fig. 5. ))(,(5 iSiTSV Lout for layout in Fig.2
Fig. 2. Targeted layout(Φ=1.75μm, HT=60μm, S=1.75μm).
Φ
S
S
T
dh
From die#1
To die#2
TSV3
TSV2
TSV1
TSV6
TSV5
TSV4
TSV9
TSV10
TSV8
TSV7
output
input
: barrier metal(Ta) : main metal(Cu)
TSV5
Directionof signaltransmission
HT=60μm
V1 R
TSVout5
S-p
aram
ete
r
R
R
V5
V10
TSVin5
TSVout10
TSVout1TSVin1
TSVin10
Fig. 3. Analysis circuit
Fig. 4. Output voltage of hard open TSV Time [nsec]
T=50μm T=40μm
T=30μmT=20μm
T=10μm
0.5 1.00.0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 1.00.90.0
0.0
-0.2
0.2
0.4
0.6
0.8
1.0
TS
Vou
t5 [
V]
1.0
Test Vector TV#1 TV#2
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Examples of obtained ))(,(5 iSiTSV Lout ’s for SL(i)={1,2,
…,10}-{i} are shown in Fig.5. We denote ))(,(5 iSiTSV Lout as TSVout5 in Fig.5. As shown in Fig.5, they depend on dh and T. Also, they depend on logic values of the neighboring TSVs.
In order to detect it without errors, test vectors should be generated with which a logical error can be generated. Since the test vector generation requires estimation of TSVout5, it is indispensable to estimate TSVout5.
III. ESTIMATION METHOD OF OUTPUT VOLTAGE FROM
HARD OPEN TSV
As shown in Fig.5, TSVout5 depends on logic signals of the neighboring TSVs, the defect size(dh) and the defective position(T). Since the voltage depends on electric field generated by logic signals of the neighboring TSVs, TSVout5 can be derived from an equivalent circuit shown in Fig.6. Ci and Co in Fig.6 are parasitic capacitances between the defective TSV and the i-th TSV and a load capacitance of TSV5, respectively.
TSVout5 is obtained from a circuit shown in Fig.7. When an input signal of the i-th TSV is L, TSVout5 is obtained by (3) from Fig.7(a).
HoiHiLi
HiL
Lout V
CCCC
CiSiTSV
))(,(5 (3)
where
)}({ 0 iSSjjHi
L
CC (4)
)}({ iSj
jLi
L
CC (5)
So is a set consisting of index number of each TSV in Fig.2.
When input signal of the i-th TSV is H, TSVout5 is obtained by (6) from Fig.7(b).
HoiHiLi
iHiL
Hout V
CCCC
CCiSiTSV
))(,(5 (6)
Thus, ))(,(5 iSiTSV Lout defined by (2) is obtained by (7).
HoiHiLi
iLout V
CCCC
CiSiTSV
))(,(5 (7)
From (1) and (2), αi is derived as ))(,(5 iSiTSV Lout . Also, Ci is defined as (8) and (9) according to an electromagnetic theory, approximately.
TS
Cn
i
)/2(
(where i≠5) (8)
hdC
1
42
5
(9)
By substituting (8) and (9) to (7), ))(,(5 iSiTSV Lout is estimated by a function in (10).
Hid
bi
Lout VbTb
TiSiTSV
h
i31
52
))(,(
(where i≠5) (10)
Thus, αi is obtained by (11).
idb
ii
bTb
T
h
i31
2 (where i≠5) (11)
Similarly, in case of TSVin5=H, ))5(,5(5 Lout STSV is obtained by (12).
HoHiLi
Lout VCCCC
CSTSV
5
55 ))5(,5( (12)
From (4), (5), (8) and (9), α5 is estimated by (13) .
3515
1
525 bTb
h
h
db
d
(13)
We derive the coefficients b1i, b2i and b3i (i=1,···,10) in (11) and (13) by fitting a function αi to 3D electromagnetic simulation results, whose number of data used for the fitting is Nsmp. The curve fitting is based on the method of least squares.
Output voltage of TSV5 will depend on test input vectors. In a test input vector generation process, it is examined whether the voltage is greater than the threshold input voltage when H is provided to a TSV. If it is greater, the input vector can be used as a test input vector. Since the voltage depends on dh and T, 3D electromagnetic simulation of many number of time should be done.
However, the voltage can be estimated with a function defined by (11) and (13). )(5 kout vTTSV
is derived by (14) that
appears when the j-th TSV is changed from L to H by providing the k-th test vector kvT
after the (k-1)-th test vector
1kvT
.
Co
TSVin4
TSVin9
TSVin6
C9
C6
C1
C8
C5
TSVout5
TSVin1TSVin3
TSVin7
TSVin5 TSVin2
TSVin8
C3
C7
C2
C4
C10
TSVin10
Fig. 6. Equivalent circuit of layout in Fig.2.
(a)TSVini=L (b)TSVini=H
Fig. 7. Equivalnet circuit for estimating TSVout5
CHi TSVout5VH
CLi Ci Co
TSVout5
Co
Ci
Ci
VH
CHiTSVout5VH CLiCi Co
TSVout5
Co
Ci
Ci
VH
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))(,()()( 5155 jSjTSVvTTSVvTTSV Loutkoutkout
(14)
where )( 15 kout vTTSV
is output voltage of TSV5 when the (k-
1)-th test vector 1kvT
is provided. We estimate )(5 kout vTTSV
with )( 15 kout vTTSV
and the functions defined by (11) and (13).
IV. EVALUATION OF OUR ESTIMATION METHOD
In order to examine feasibility of our estimation, we estimated output voltage of TSV5 in Fig.2 that appeared when H was provided to TSV6 after H was provided to TSV2, TSV4 and TSV8. Inserted open defects are the followings: T=10μm, 20μm, 30μm, 40μm and 50μm, dh=10nm, 20nm, 40nm, 60nm, 80nm, 100nm, 200nm, 400nm, 600nm, 800nm and 1μm. The total number of inserted defects is 55.
3D electromagnetic simulation results are plotted in Fig.8(a) and Fig.8(b) when H is provided to TSV2, TSV4 and TSV8 and when H is provided to TSV2, TSV4, TSV6 and TSV8, respectively. The simulation results of parameters depicted in Fig.9 are used for deriving an estimation function in (11).
Estimated voltages of TSVout5 are depicted in Fig.8(c) which are obtained by the estimation function derived from data of Nsmp=9. The differences between Fig.8(a) and Fig.8(c) are shown in Fig.8(d). It is shown in Fig.8(d) that TSVout5 is estimated within 40mV by our method.
The estimation errors in our examination are summarized in Table I. As shown in Table I, TSVout5 is estimated with an error less than about 38mV. We think that it is enough small to generate test input vectors and locate the defects, since VDD
in Fig.3 is 1.0V. The estimation results can be obtained by our method with a small number of times of 3D electromagnetic simulation. Thus, we think that this estimation method is useful for generating test input vectors.
V. CONCLUSIONS
In this paper, we have proposed an estimation method of quiescent output voltage of a hard open TSV from 3D electromagnetic simulation results. By using the method, output voltage of a defective TSV can be estimated quickly with an error rate of 3.8%. It is a future work to develop a test input generation algorithm for detecting hard open defects at TSVs.
ACKNOWLEDGMENT
This work is accomplished with EMPro and ADS produced by Agilent Technologies. We would like to thank the technical staff in Agilent Technologies, especially, Mr. Noriyoshi Hashimoto for their technical supports.
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[3] E.J.Marinissen and Y.Zorian, “Testing 3D Chips Containing Through-Silicon Vias”, Proc. of IEEE International Test Conference 2009, Paper ET1.1, pp.1-11,2009.
[4] E.J.Marinissen, “Testing TSV-Based Three-Dimensional Stacked ICs”, Proc. of 2010 Design, Automation & Test in Europe Conference & Exhibition, pp.1689 – 1694,2010
[5] M.Hashizume, S.Kondo and H.Yotsuyanagi, “Possibility of Logical Error Caused by Open Defects in TSVs,” Proc. of 2010 International Technical Conference on Circuits, Computers and Communications, pp.907-910,2010.
[6] P.Y.Chen, C.W.Wu and D.M.Kwai, “On-Chip Testing of Blind and Open-Sleeve TSVs for 3D IC before Bonding”, Proc. of 2010 28th IEEE VLSI Test Symposium, pp.263-268,2010.
[7] C.W.Chou, J.F.Li, J.J.Chen, D.M.Kwai, Y.F.Chou and C.W.Wu, “A Test Integration Methodology for 3D Integrated Circuits”, Proc. of 2010 19th IEEE Asian Test, pp.377-382,2010.
[8] B.Noia, K.Chakrabarty and E.J.Marinissen, “Optimization Methods for Post-Bond Die-Internal/External Testing in 3D Stacked ICs”, Proc. of 2010 IEEE International Test Conference, pp.1-9,2010.
[9] M.Gulbins, F.Hopsch, P.Schneider, B.Straube and W.Vermeiren, “Developing digital test sequences for through-silicon vias within 3D structures”, Proc. of 2010 IEEE International 3D Systems Integration Conference, pp.1-6,2010.
[10] Y.J.Huang, J.F.Li, J.J.Chen, D.M.Kwai, Y.F.Chou and C.W.Wu : “A Built-In Self-Test Scheme for the Post-Bond Test of TSV s in 3D ICs”, Proc. of 2011 29th IEEE VLSI Test Symposium, pp.20-25,2011.
Max. Min. Ave.4 35.76 0.10 10.52
6_T 32.39 0.46 9.996_dh 38.06 0.16 10.82
9 38.06 0.16 10.8255 24.09 0.03 9.78
NsmpEstimation error [mV]
TABLE I. ESTIMATION ERRORS
Nsmp sampled data4
6_T6_dh
955
++++ + +
all0
10
100
1000
10 20 30 40 50T [μm]
dh
[nm
]
(a) sample data (b)sample data Fig. 9. Sampled data for estimation
(c)estimation results (d)estimation errors
(a) simulation results of (b) simulation results TSVin2=TSVin4=TSVin8=H TSVin2=TSVin4= TSVin6=TSVin8=H
Fig.8. Equivalnet circuit for estimating TSVout5