Figure 1. 6T-SRAM cell showing PG-PD read stack voltage conditions for Iread measurement.

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Model - Iread Model - Idsat,PG Sim - Iread Sim - Idsat,PG

Figure 2. Negative feedback of Vread on the read stack variability gives rise to a lower σIread than the constituting PG device variability at the same gate overdrive condition.

SRAM Read Current Variability and its Dependence on Transistor Statistics

Sriramkumar Venugopalan1, Vivek Joshi2, Luis Zamudio2, Matthias Goldbach3, Gert Burbach3, Ralf VanBentum3, Sriram Balasubramanian2

1Dept&of&EECS,&University&of&California,&Berkeley,&Email1:&sriram@eecs.berkeley.edu&2GLOBALFOUNDRIES, Sunnyvale, CA, USA, Email2:&Sriram.Balasubramanian@globalfoundries.com

3GLOBALFOUNDRIES, Dresden, Germany&

Abstract— Our study breaks down the dependence of SRAM read current (Iread) variability (σIread) into constituting pass-gate (PG) and pull down (PD) NMOS transistor variability. We report a bottoms-up model for σIread including feedback in stacked transistors and discuss its implications on SRAM performance.

I. INTRODUCTION Iread and its statistics is a key performance metric that limits

voltage scaling in SRAMs [1]. Traditional methods have depended on running millions of Monte-Carlo (MC) simulations but don’t address the fundamental relation between transistor and Iread variability.

In this work we develop a unified σIread model from its fundamental components – namely, the variability of the PG and PD devices, Fig. 1. We define the concept of effective stack variability and clarify the role of negative feedback present in the SRAM read stack that results in σIread being lower than the variability of an equivalent single PG transistor, Fig. 2. We validate this model using both MC simulations and 32/28nm technology (tech) SRAM hardware bit-cell data. With continued scaling, 6σ-Iread validation needed for large memories are a significant challenge in early tech development. Using this σIread model we verify the empirical Voltage Acceleration Method (VAM) [2] and derive the value of the VAM voltage shift (σVAM) based on PG and PD variability.

II. SRAM READ CURRENT VARIABILITY MODEL Iread is the current that flows from a pre-charged bit-line to

ground through stacked PG (in saturation) and PD (in linear region) NMOS devices that are ‘ON’, Fig. 1. During an Iread measurement, the read stack internal node voltage rises above ground to Vread with PG in saturation and PD in linear regions of operation, Fig. 1. σIread is then attributed to variability of the PG and PD devices respectively. The equations for Iread, σIread with its individual component breakdown are summarized in Table 1. A dominant source of PG variability is from its threshold voltage, σVTH,sat,PG [3]. It is important to note that the overall contribution of σVTH,sat,PG to σIread is reduced owing to the negative feedback of Vread through gate overdrive (ΔVTH,sat,PG and ΔVread are negatively correlated,

Fig. 3(a)). On the other hand, PD threshold voltage variability, σVTH,lin,PD impact on σIread is affected in two distinct ways – a small positive feedback through the (Vdd-VTH,lin-Vread/2) term and larger negative feedback through the drift field term (Vread) (ΔVTH,lin,PD and ΔVread are positively correlated, Fig, 3(b)). Overall the negative feedback component of Vread on both PG and PD variability effectively reduces σIread as compared to the inherent variability of both the PG and PD devices, Fig. 2. We note from the derived

978-1-4673-6146-0/13/$31.00 ©2013 IEEE

Table& 1." Equations" describing" SRAM" read" current" variability" as" a" function" of" PG" and" PD" device" variability." Single" transistor"variability"representation"of"σIread"through"an"effective"stack"variability,"σVTH,eff"is"derived"as"a"function"of"σVTH,sat,PG""and"σVTH,lin,PD."

Iread = KPG ⋅ (VDD −VTH ,sat,PG −Vread )αsat = KPD ⋅ VDD −VTH ,lin,PD − 0.5Vread( )αlin ⋅VreadΔIreadIread

$

%&

'

()PG

= −αsat ⋅ ΔVTH ,sat,PG

(VDD −VTH ,sat,PG −Vread )−

αsat ⋅ ΔVread(VDD −VTH ,sat,PG −Vread )

ΔIreadIread

$

%&

'

()PD

= −αlin ⋅ ΔVTH ,lin,PD

VDD −VTH ,lin,PD − 0.5Vread( )−

0.5 ⋅αlin ⋅ ΔVreadVDD −VTH ,lin,PD − 0.5Vread( )

+ΔVreadVread

ΔIreadIread

$

%&

'

()Tot

≈ −αsat ⋅ ΔVTH ,sat,PG

(VDD −VTH ,sat,PG −Vread )⋅β

1+β−

αlin ⋅ ΔVTH ,lin,PD

VDD −VTH ,lin,PD − 0.5Vread( )⋅

11+β

= A ⋅ ΔVTH ,sat,PG +B ⋅ ΔVTH ,lin,PD

σ IreadIread

= (A ⋅σVTH ,sat,PG )2 + (B ⋅σVTH ,lin,PD )2 =αsat ⋅σVTH ,eff

(VDD −VTH ,sat,PG −Vread ) (1)

σ Idsat,PGIdsat,PG

=αsat ⋅σVTH ,sat,PG

(VDD −VTH ,sat,PG −Vread )=αsat ⋅σVTH ,sat,PG

VPG,overdrive

(2)

Fig 3. SRAM bit-cell hardware data from a 32nm tech show (a) negative correlation of Vread vs. VTH,sat,PG (b) positive correlation of Vread vs. VTH,lin,PD. Both result in negative feedback of Vread on σIread

Fig 4. MC simulation results of a 28nm tech validate the effective stack variability model showing σIread as an extrapolation of σIdsat,PG across (a) Vdd, SRAM design points (β) and (b) temperatures.

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Simulations - 28nm tech Vdd = 0.7 to 1.3V β = 0.75 to 1.5

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Hardware Data 28nm tech Multiple Vdd

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Figure 5. SRAM bit-cell level measurements of (a) σIdsat,PG and σIread for a 32nm tech, and (b) σIread for a 28nm tech across multiple Vdd lie on the same unified straight line as predicted in Eq.(1,2).

Figure 6. At constant Iread, 28nm tech (a) Both simulations and the model, Eq.(1) indicate β ≈ 1 designs are preferred for lower σIread. (b) Relative contributions of PG and PD device variability towards σIread shows that PG contribution dominates even for β=1. Iread = f (Vdd −VTHeff ,read )ΔIreadIread

= A ⋅ ΔVTH ,sat,PG +B ⋅ ΔVTH ,lin,PD

ΔIreadIread

=∂Iread∂Vdd

⋅ΔVAMIread

= (A+B) ⋅ ΔVAM

σVAM =A ⋅σVTH ,sat,PG( )2

+ B ⋅σVTH ,lin,PD( )2

A+B(3)

σVAM =σVTH ,eff ⋅A

A+B%

&'

(

)*⋅ 1+ 1

β

%

&'

(

)* (4)

Table 2. Equations describing the sensitivities of Iread and σVAM required for estimating 6σ-Iread.

model σIread/Iread in Eq.(1) is purely a function of the gate-overdrive, σVTH,sat,PG, σVTH,lin,PD and PD/PG size ratio (β).

III. EFFECTIVE READ STACK IREAD VARIABILITY A convenient way to represent σIread is to represent it as the

variability of an equivalent single transistor (with Vsource=Vread) with an effective stack variability, σVTH,eff, which is dependent on both σVTH,sat,PG and σVTH,lin,PD, Eq.(1). Fig. 4 shows validation of this model by unifying normalized σIdsat,PG and σIread against σVTH,sat,PG and σVTH,eff normalized to PG device gate-overdrive. Results from MC simulations of a 28nm tech SRAM for a wide range of Vdd, temperatures and design explorations (varied β) all fall on a straight line with unified slope, Eq.(1,2). Effective stack variability plots for 32nm and 28nm measured Si hardware data across cell sizes and Vdd reveal that σIdsat,PG and σIread lie on the same straight line and the unified slope is relatively independent of technology as they are functions of σVTH,sat,PG, σVTH,lin,PD and gate-overdrive, Fig. 5.

IV. IMAPCT ON CHOICE OF CELL-RATIO (β) While the choice of 6T-SRAM β is often co-optimized to

meet read-disturb/write/performance margins, 8T read stacks are often tuned for performance (CVdd/Iread). In order to validate the σIread model, we explore one possible optimization to minimize σIread, by varying the sizes of PG

and PD devices (β varied by varying width) while maintaining a constant Iread. The simulation results show (and the model agrees) that β <1 is optimal for minimal σIread/Iread, Fig. 6(a). The variability model provides insights into the relative sensitivities of PG vs. PD (prefactors A vs. B) devices towards σIread. The PG limits σIread (for β>0.8) with the PD starting to limit σIread only when the PD device gets really small (for β<0.8), Fig. 6(b). At β=1, PG still dominates due to its larger sensitivity (A>B) and so for minimum

(a)

(b)

Figure 7. (a) Estimated σVAM in Eq.(4) and σVTH,eff in Eq.(1) are ≈ constant across Vdd of interest (b) 6σ-Iread estimated from smaller number of MC simulations at lower Vdd (VAM) using Eq.(3). (c) Extracted σVAM from Fig. 7(b) and calculated σVAM using Eq.(3) agree with each other.

σIread/Iread, optimum β < 1, Fig. 6(a). Also from a similar exercise, 2% improvement in σIread for every 10% increase in

length of the PD device was found, again favoring lower β values (figure not shown).

V. VAM METHOD FOR 6σ READ CURRENT ESTIMATION The VAM method proposed in [2] uses Iread measurements

at lower Vdd to predict 6σ-Iread. By equating the Iread sensitivity to Vdd and VTH shifts in the σIread model, we estimate the Vdd reduction (=Vdd-σVAM) to be applied to the read stack that would produce a σIread offset in the stack current, Table 2. We observe that σVAM (like σVTH,eff) is only a function of σVTH,sat,PG, σVTH,lin,PD , β and gate overdrive and is almost constant with Vdd, (for a given β, A/B is ≈ constant) allowing for extraction of 6σ-Iread by applying Vdd-6*σVAM to the read stack, Fig. 7(a). We recreate the VAM plot with simulation results for a 28nm tech by overlaying the Iread distribution plots at different Vdd by an Iread sigma shift Δσ (= ΔVdd/σVAM) in Fig. 7(b), thereby permitting the estimation of 6σ-Iread value. Given that σVAM is relatively constant, Δσ is also relatively constant up to 6σ-Iread projections, which agrees with the observations in [2]. Both the MC simulation extracted and the model estimated Δσ are in excellent agreement in Fig. 7(c), which validates the formulation that σVAM is indeed related to PD/PG variability.

VI. CONCLUSIONS We describe the dependence of SRAM Iread variability on

fundamental transistor variability parameters through a simple Si-validated model that includes the negative feedback of Vread on σIread. We illustrate the concept of effective stack variability that unifies σIread and single transistor variability into a single plot. Study indicates a preference for lower than typical β values for SRAM to achieve lower σIread. This has a profound impact on design choices for 8T-SRAM cells where writability is not a constraint. We evaluate the VAM method for accelerated Iread distribution tail analysis and explain the theoretical basis of the VAM voltage shift that can be used to extract 6σ-Iread value.

REFERENCES [1] E. Grossar et al, “Read Stability and Write-Ability Analysis of

SRAM Cells for Nanometer Technologies” IEEE Journal of Solid-State Circuits, Vol. 41, No. 11, Pg. 2577, 2006.

[2] J. Wang et al, ”Non-Gaussian distribution of SRAM read current and design impact to low power memory using Voltage Acceleration Method”, Symposium on VLSI Technology Digest, Pg. 220, 2011.

[3] A. Asenov, “Simulation of Statistical Variability in Nano MOSFETs”, Symposium on VLSI Technology Digest, Pg. 12, 2007