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A 11 mW 68dB SFDR 100 MHz bandwidth∆Σ-DAC based on a 5-bit 1GS/s core in 130nm

Pieter Palmers, Michiel Steyaert

Abstract—This paper presents a delta-sigma current-steeringdigital-to-analog converter implemented in a standard 130nmCMOS technology. The 5-bit core DAC provides 13-bit staticlinearity without calibration, using only 0.44mm2. The delta-sigma converter achieves 68dB SFDR over a 100MHz signalbandwidth at 1GHz sampling frequency. A novel very low powerthermometer decoder was used, resulting in a power consumptionof 11mW. In terms of power efficiency this converter outperformsall comparable D/A converters published in open literature. Thedesign demonstrates the viability of multi-bit delta-sigma D/Aconverters as an alternative for Nyquist-rate DACs in highlyintegrated broadband applications. It also shows that in deepsub-micron processes the use of a delta-sigma converter extendsthe usable bandwidth for D/A converters.

Index Terms—D/A Converters; current-steering; CMOS; delta-sigma; deep sub-micron

I. INTRODUCTION

Along with the emerging demand for multi-standard largebandwidth digital communication systems comes a need toimplement higher performance data converters. For cost andintegration reasons these are preferably implemented on thesame die as the digital baseband section. This enforces theuse of a modern deep sub-micron CMOS technology to im-plement these data converters. At very high conversion speedsintegration is also beneficial with respect to interfacing, sinceconnecting multiple chips with multi-bit interfaces runninggigabit/s per pin data rates is non-trivial and power hungry.Implementing data converters in modern day deep sub-microntechnologies however imposes new design challenges as aresult of their lower analog performance.

This paper presents a 5-bit delta-sigma modulated current-steering Digital-to-Analog Converter (DAC) achieving 68dBof SFDR for a 100MHz signal band. It was manufactured in apure-digital 130nm technology and consumes only 11mW atits nominal 1GS/s update rate.

The motivation and problem at hand are explained in sectionII. Section III describes the basic architecture, topology andfloor plan and the different building blocks of the DAC.The measurement results of the prototype are presented andcommented in section IV. Finally, some conclusions are for-mulated.

II. IN-BAND HARMONIC DISTORTION

From a system point of view, D/A converters are blocks thatshould generate a predefined signal bandwidth at a specifiedprecision and linearity. The major challenge in the design ofD/A converters is not merely achieving a high update rate, butachieving high linearity over a large signal bandwidth. In-band

distortion can be considered more important than out-of-banddistortion since the latter can be filtered (e.g. spectral imagesin Nyquist rate D/A converters).

One of the main sources of non-linearity in current steer-ing D/A converters is recognized to be the code depen-dency of the converters output impedance [1][2]. Sufficientoutput impedance has to be maintained over the completeoutput signal bandwidth. As calculated in [2], the relationbetween second order distortion performance (SFDRHD2),load impedance (RL), number of bits (B) and the requiredoutput impedance (Zreq) of the unit current cells is given by:

Zreq =SFDRHD2 ·RL · 2B

4(1)

This equation shows that in order to evaluate the maxi-mum usable bandwidth for a given linearity specification,the impedance of the switched current cell is a key param-eter. Therefore it is useful to examine the maximal outputimpedance a current cell can provide over the desired fre-quency range, given a certain technology.

Fig. 1. Ideal switched current cell and it’s simplified small signal equivalent

Fig. 1 shows an idealized switched current cell that consistsof a current source having an output impedance equal toZCS , and a saturated CMOS transistor operating as switch.Neglecting the complementary switch as it is turned off, and alldevice capacitances except for the gate-source capacitance, thesmall signal equivalent circuit reduces to the circuit shown onthe right. The output impedance of this configuration is easilycalculated to be (assuming ZCS � |sCgs| and gmrout � 1):

Zout = rout(1+gmZCS

1 + sZCSCgs) ≈ rout(1+gm

1sCgs

) (2)

Recognizing that gm

2πCgsis the transition frequency (fT ) of

the saturated switch transistor, equation (2) can be rewrittenas:

Zout ≈ rout(1− jfTf

) (3)

Equation (3) can now be used to determine the maximumfrequency fmax up to which the switched current cell achievesa certain required output impedance Zreq. Starting from

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|Zreq| =∣∣∣∣rout(1− j

fTfmax

)∣∣∣∣

and assuming that fmax � fT , we obtain:

fmax · Zreq = fT · rout (4)

This equation reveals a trade-off between circuit perfor-mance and technology. It reveals that for broadband highoutput impedance current cells the used transistors should notonly have high-speed, but also exhibit high output impedance.The relations obtained in this section are summarized in Fig.2. It shows that the output impedance drops with 20dB/dec toreach rout when frequency passes fT of the switch transistor,as indicated by equation (3). For a certain required impedance,the maximum operating frequency can be determined usingequation (4).

Fig. 2. Output impedance for a switched ideal current source

The presented calculations consider only the gate-sourcecapacitance of a switch transistor that cascodes very highimpedance current source, hence present an optimistic viewof the problem. Other significant capacitances are present atthe switch source node (e.g. wiring capacitance, source-bulkcapacitance), and current source output impedance is limited.Nevertheless it gives insight in the core problem of current celldesign in deep sub-micron CMOS technologies: since equation(1) limits the impedance, the maximum signal bandwidth isfixed by the fT rout product of the switches. Although thesetechnologies provide every increasing transition frequencies,short channel effects cause rout to drop, resulting in a stag-nating, in some cases even decreasing, fT rout product. In thisdesign, the used 130nm CMOS technology limits fmax toapproximately 80MHz for a 60dB SFDRHD2 specification.

The presence of higher order distortion for higher signalfrequencies is usually not a problem since it falls out of bandand hence is filtered by the reconstruction filter. Any distortionpresent in the output spectrum however will interact with thesample frequency and will be folded back (mixed) into theband of interest. It is therefore beneficial to use higher degreesof oversampling such that the magnitude and the number ofharmonics that are folded back is decreased.

III. ARCHITECTURE AND CIRCUIT DESIGN

Fig. 3 shows the floor plan of the experimental prototype.The clock and binary input data is brought on chip by a high-speed low-voltage differential signaling input stage. The binaryinput words are decoded by a 5-31 decoder that providesthe input signals for the switch drivers, driving the switchedcurrent cells. Current matching is provided by the current

Fig. 3. Prototype floor plan

source array (CSA). For clock and output routing, balancedtrees have been used to ensure low delay mismatch.

Aside from the clock distribution, the thermometer decoderis the main contributor to the total power consumption ofa unary DAC. The lack of regularity in the thermocodeconversion operation, since every output is dependent on all ofthe inputs in a unique way, results in a separate logic functionfor each output. This requires a full custom design processand a high power consumption since all data lines have tobe routed over the complete decoder. For this design, a 5-31decoder was designed that achieves the required speed witha very low power overhead. The decoder is inspired by themux-based topology proposed in [3].

Fig. 4. Multilevel 5-31 decoder architecture

Fig. 4 shows the 5-31 thermometer decoder architecture.In a first stage, the lower 3 bits are converted by a 3-to-7decoder. Such a decoder can be built using logic functions thatconsist of either one-level NAND3 gates or two-level NAND2gates. By restricting the decoder functions to these two logicfunctions the transition speed through the decoder can be fastand well equalized. The second stage consists of a set of equalmux blocks that select among three levels: logic 0, logic 1or first stage output. This selection is based upon the S[0:4]select signals that are generated by the SELGEN block. Thetruth table for this block is included in the figure. This designresults in high speed capability with low power consumption.

The specification for the static linearity of the DAC requiresadequate current source matching. The first order Pelgromrelationship [4] between current matching and area is givenby:

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(∆I

I)2 = (A2

β +4 ·A2

V T

(Vgs − VT )2)

1WL

(5)

Aside from the well-known fact that matching is largelydetermined by area, the equation also indicates the sensitivityof matching to the gate overdrive of the current sourcetransistor. On the other hand section II shows that the switchesshould also have a high fT , hence also high gate overdriveto maximize their speed. In deep sub-micron technologieswith a low power supply it becomes increasingly difficult tomeet both specifications simultaneously. Designing for highswitching speed results in very large area requirements for thecurrent source transistors.

In order to lower the area requirements, this design usesPMOS transistors as current sources and a 1.5V power supplyfor the current source array. Doing so allows for more currentsource transistor gate overdrive and hence lowers the effect ofVT mismatch, reducing the total area of the system. The maindisadvantage of this, aside from extra power consumption,is that one has to ensure that no voltage difference exceedsthe maximum operation voltage of the transistors (1.2V).The commonly used cascoded current cell however inherentlyprovides a cascode that can be used to shield the high-voltageCSA from the switches. To overcome systematic mismatcherrors, the spatial averaging technique proposed in [5] has beenused.

IV. MEASUREMENT RESULTS

All measurements are performed on a single ended outputsignal with 5-mA load current. If not specified otherwise, mea-surements are performed at the nominal sample rate of 1GS/s.Since the circuit is still functional at 2GS/s, measurements forthis sampling frequency have also been performed. The noiseshaped input signal was generated externally using a 3rd orderdigital noise shaping loop. It was applied to the chip over ahigh-speed LVDS interface.

Fig. 5. INL plot illustrating an uncalibrated static linearity of 0.21LSB12−bit.

Fig. 5 shows a typical measured INL plot, showing that theconverter provides 0.21LSB referred to 12-bit accuracy, cor-responding to better than 13bit static accuracy. This indicatesthe effectiveness of the used current source array scramblingand cell biasing.

Fig. 6 shows the output spectrum of the converter bothwhen 6MHz signal and 99MHz signals are applied. Theplots show the very limited harmonic downmixing due to thehigh oversampling ratio, notwithstanding the presence of a

(a) (b)

Fig. 6. Output spectrum for a 6MHz (a) and 99MHz (b) output signal,converted at 1Gs/s and 2Gs/s. The inset shows a zoomed-in version of theconverted signal to illustrate the fact that the signal smearing observed in themain plot is a measurement artifact. The lower quantization noise due to thehigher oversampling when using a 2GS/s update rate can be observed. Theextra spurious at 2GS/s are due to decoding errors starting to occur.

significant second order harmonic originating from the limitedoutput impedance of the current cell. At 2GS/s decoding errorsstart to occur, generating extra spurious. An example outputspectrum ranging up to the sample frequency is shown in Fig.7. The third-order noise shaping and the out-of-band distortioncan be observed.

Fig. 7. SFDR up to the sample frequency of 1GS/s. The signal appliedis a 50MHz sine, since this is the highest frequency that causes the secondorder harmonic to fall in-band. The third order noise-shaping and out-of-banddistortion can be observed.

A summary of the spectral performance within the band ofinterest is shown in Fig. 8, indicating better than 68dB SFDRfor signals up to 100MHz.

Fig. 8. SFDR within the DC-100MHz band, for signals from 5 to 100MHzsampled at 1Gs/s and 2Gs/s.

For multi-carrier signal generation applications, the higherorder harmonic distortion is not that important since it iseffectively filtered by the reconstruction filter. A more signifi-cant distortion mechanism for such systems is intermodulationdistortion, since these spurious appear in the desired signal

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band. Fig. 9 shows an overview of the third-order intermodu-lation performance of the converter. It shows better than 70dBintermodulation over a 50MHz band, and maintains at least58dB over the 100MHz signal band. .

Fig. 9. IMD3 versus center frequency for two tones spaced 2MHz apart,sampled at 1Gs/s and 2Gs/s.

A. Design summary and comparison

Fig. 10 shows a chip micrograph, marking the current cellarray, swatches and decoder. Table I summarizes the design.

Fig. 10. Chip photograph

TABLE IDESIGN SUMMARY

Technology 130nm CMOSArea 0.42mm2

INL 0.21 LSB12−bit

Load current 5mAAnalog supply 1.5V

Update rate 1Gs/s 2Gs/sDigital supply 0.9 1.2

Power 11.1mW 21.9mWBandwidth 100MHz 100MHz

SFDR@50MHz 70db 71dBIMD3@50MHz 70dB 76dB

SFDR@100MHz 70db 71dBIMD3@100MHz 58dB 58dB

To indicate the advantage of the delta-sigma oversampledarchitecture, Table II compares this design with the currentstate of the art deep sub-micron converters capable of con-verting a 100MHz band with at least 60dB of SFDR. Thecomparison clearly shows the power merits of the presentedconcept and design.

A side remark is that the bandwidth of low oversamplingconverters is severely limited by the presence of Nyquistimages, resulting in a significant power penalty in the recon-struction filter.

TABLE IICOMPARISON WITH RECENTLY PUBLISHED CMOS DAC AT 100MHZ

SIGNAL BANDWIDTH

This work [6] [7] [8]Bandwidth 100 100 120 125 MHzResolution 5 (12) 12 12 10 bit

Load current 5 5 5 (15) 5 mAUpdate rate 1000 200 350 250 MS/s

SFDR@100MHz 70 55 70 58 dBPower 11.1 25 198 (216) 14 mWFOM 36900 4100 620 (570) 7140 MHz/mW

Technology 0.13 0.13 0.18 0.18 µm

V. CONCLUSIONS

In this paper, a simple analysis was presented to assessthe maximal distorion performance of current steering D/Aconverters in nanometer CMOS technologies. It relates themaximal achievable bandwidth for a certain linearity speci-fication to technological parameters of the used process. Thisresults in a clear trade-off indicating the significance of signalbandwidth rather than raw update rate. By leveraging the highspeed of modern CMOS processes to achieve a large degree ofoversampling, some of these limitations can be circumventedand the usable bandwidth of the converter can be increased.

A multi-bit delta-sigma modulated D/A converter is pre-sented that achieves 12-bit performance over a signal band-width of 100MHz. It is based upon a 5-bit current steeringDAC that is operated at 1GS/s. The use of a 5-times oversam-pling not only allows for the application of a 3rd order noiseshaping function, it also reduces the downconversion of distor-tion products into the band of interest. The converter achieves13-bit static linearity without calibration by employing currentsource array averaging and extended overdrive biasing of thecurrent source transistors. A novel multilevel decoder circuitwas developed to reduce power consumption to only 11mW.When comparing the converter to current state of the artdesigns, the proposed techniques achieve an improvement ofpower efficiency by approximately a factor 5.

REFERENCES

[1] R. V.D. Plassche, CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters, Kluwer Academic Publishers, 2003.

[2] A. van den Bosch; et. al., “SFDR-bandwidth limitations for high speedhigh resolution current steering CMOS D/A converters,“ Proc. IEEE Int.Conf. El., Circuits and Systems, pp. 1193-1196, Sept. 1999

[3] Van Der Plas, G.A.M.; et. al., "A 14-bit intrinsic accuracy Q2 ran-dom walk CMOS DAC", IEEE Jnl. Solid-State Circuits, vol.34, no.12,pp.1708-1718, Dec 1999

[4] Pelgrom, M.J.M.; et. al., "Matching properties of MOS transistors", IEEEJnl. Solid-State Circuits, vol.24, no.5, pp. 1433-1439, Oct 1989

[5] Deveugele, J.; et. al. , "A gradient-error and edge-effect tolerant switchingscheme for a high-accuracy DAC," Circuits and Systems I: RegularPapers, IEEE Trans. on Circuits and Systems I, vol.51, no.1, pp. 191-195, Jan. 2004

[6] Clara, M.; et. al., "A 1.5V 200MS/s 13b 25mW DAC with RandomizedNested Background Calibration in 0.13u CMOS", IEEE Solid-StateCircuits Conference, Dig. of Tech. Papers, 2007, pp.250-251

[7] Doris, K.; et. al., "A 12b 500MS/s DAC with >70dB SFDR up to 120MHzin 0.18um CMOS", IEEE Solid-State Circuits Conference, Dig. of Tech.Papers, 2005, pp.116-117

[8] Deveugele, J.; et. al., "A 10-bit 250-MS/s binary-weighted current-steering DAC", IEEE Jnl. Solid-State Circuits, vol.41, no.2, pp. 320-329,Feb. 2006

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