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An Economic Method for Fabrication Sub-Quarter-pm Gate Doped-Channel FET's by Photolithography

S. W. Tan, W. T. Chen, M. Y. Chu and W. S. Lour

Department of Electrical Engineering, Taiwan Ocean University, 2 Peining Road, Keelung, Taiwan, China. Email: wslo@mail.ntou.edu.tw

Tel: 886-2-24622192 ext.6233 Fax: 886-2-24635408

Abstract

This paper reports a new sub-0.5ym gate-length FET processing technique by using conventional i-line optical lithography. The key methodology is to thermally re-flow the patterned photo-resist upon two-step spin-coated SOG According to this new process, the deposited gate metal has its final length and thickness be separately determined by taped resist profile and SOG thickness. The implemented gate length is as short as 0.41 wm. Then it was successfully applied to fabrication of a newly designed hetero-doped-channel field-effect transistor with digital-graded InXGal.,As multi-layer forming a HEMT-like channel. This digital-graded In,Ga,.,As channel by changing x values from 0.1 to 0.2 has most electrons be closer to gate metal. The measured sheet carrier density and mobility are 4.3~10" cm? and 3560 cmZV-'s8 while the peak carrier concentration is larger than 1 ~ 1 0 ' ~ C I I - ~ . A fabricated 0.41x100 pnz HDCFET exhibits the maximum transconductance of 370 mS/mm with an output current lager than 535 mA/mm andft (fmax) of 26 (32) GHz.

1. Introduction

The Most effective way to improve the high-frequency performance of FET-related devices is to shorten 'the gate length. The HEMT structure is possible for overcoming the threshold-voltage shift toward large pinch-off voltage or the increase of the drain conductance that caused by an increase of the aspect ratio (aLg, where a is the effective distance from gate metal to channel, and Lg is the gate length) [I]. An alternate to the HEMT structure is the hetero-doped-channel field-effect transistors (HDCFET's), which employ a thin heavily, doped narrow-gap material as a channel and a thin undoped wide-gap material as an. Schottky barrier [2]. Therefore HDCFET's, in particular InGaPflnGaAs ones, have recently received much attention to wireless communication for low noise amplifiers and high power amplifiers L2-41. These advantages associated with InGaPhGaAs HDCFET's generally include: 1) easy control in gate recess where the cap layer is removed by

wet etch to expose the underlying layer for the Schottky gate formation, 2) the reduction of short-channel effects that caused by an increase of the aspect ratio as the gate length is shortened and 3) no parallel conduction occurs.

Recent EB- or photolithography and self-alignment technologies have proved to be effective for implementing sub-half-micrometer patterning [5, 61. However, to produce such a sub-0.5-pm gate metal with acceptable performance and processing yield by using conventional optical lithography (in particular, with i-line lithography) is still difficult and complex. Although a taped photo-resist by thermal re-flow is possibly used to obtain a smaller gate window than that patterned by original mask. In such a technique, the gate length is determined by the taped photo-resist that is re-flowed upon spin-on-glass (SOG) coating layer and the thickness of deposited metal is dependent on the SOG thickness. Due to the isotropic etch profile of SOG coating layer, undercutting occurs when the etch process removes excessive SOG below the taped photo-resist. This is advantageous for the lift off process.

2. Device structure and materials

The HDCFET structure, as shown in Fig. 1, prepared by low-pressure metal organic chemical vapor deposition (LP-MOCVD) was grown on semi-insulating GaAs substrate. It consists of a 0.6-pm undoped GaAs buffer, a digital-graded channel (nt=5x10'* 50-&50-h50-A nt - I~ . lG~ . sAs /n i - Ino , ,5G~,~5As /n ' - Ino .~G~.~As , a 200-A undoped InGaP Schottky layer, and a 300- A,heavily doped GaAs cap layer. The n'-In,Ga,.,As digital-graded channel with x values equal to 0.1,0.15 and 0.2 is used to form a HEMT-like channel. Those In,Ga,.,As layers with lower In mole fraction (that is wider-gap materials) have their elections transferred into 111&ao.~As layer which is the closest to gate metal. Most of electrons should locate at the bottom of triangle-shaped well, as also shown in Fig. 1 the simplified conduction-hand diagram corresponding to HDCFET. This makes the thin IQ.~G%.~As layer dope much high than 5 ~ 1 0 ' ~ Also, electrons in such a designed channel exhibit more significant electron velocity overshoot. Hall measurement at room temperature indicates the sheet carrier concentration of

0-7803-8191-2/04/$17.00 02004 IEEE.

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4 . 3 ~ 1 0 ' ~ c K 2 with a mobility of 3560 cm*V-ls-'.

50 8, n+- Ino.~Gao.9As

I 0.6 pm undoped GaAs 1 - L I a S. I. G A S Substrate

Fig. 1 schematic cross section of an InCaPAn,Ga,.,As HDCFET structure with a digital-graded channel. The corresponding conduction-hand diagram also shows that the proposed structure forms a HEMT-like channel.

3. Device fabrication and experiment

The device fabrication started with mesa formation. Both GaAs and In,Gal.,As layer were selectively etched in 4H2S04:1Hz02:5Hz0 solution, while the InGaP layer was etched in HC1:H3P04 solution. Au/Ge metal was deposited upon cap layer and then annealed at 350 OC for 20 sec for both drain and source ohmic contacts. The drain-source spacing is fixed at 3 pm for all fabricated devices. After removal of cap layer, the spin-on-glass film was two-step spin-coated (both at 3000 rpm for 20 second) on the sample and was cured in oven (at 120 'C for 40 minutes; respectively). The two-step spin-coated SOG film, Honeywell #314, has its final thickness of 6000 A. A patterned photo-resist through mask is implemented by conventional i-line ( A =365 nm) optical lithographical method, as shown in Fig. 2(a), to have its original feature size of L=0.8-1.5 pm. The photo-resist film, FH-6400L (Fuji-Hunt Electronics Technology Co.), is spin-coated at 6000 rpm for 20 sec to have a thickness of 0.7 pm. The thermal flow of resist that occurs during post-development thermal bake is used to modify the edge profile of the resist. The used thermal bake temperature is in the range of 100 to 160 C for 1 to 10 minutes. Figure 2 (b) defines the extended length of resist from' window edge as AL. That is the final gate length available is determined as L-2AL, where Lis the original resist window size pattemed through mask. Followed process is the isotropic wet-etch o@SOG in the buffered oxide etch (BOE) solution to form undercutting. Finally, a thick An metal is directly,and precisely deposited upon the InCaP Schottky layer through the taped resist window [see Figs. 2(c) and 2(d)]. Clearly, the gate-metal could be as thick as that of two-step spin-coated SOG and be not

influenced by the taped wall profile of resist during lift off process. Furthermore the available gate length is 0.35-1.5 pm. Of course, an effective gate length down to 0.1-0.2 p n is also possible.

L' A ........ I+: ....... . .

m \/-- *e- - 3 V b + I t +

Au n Fig. 2 processing procedures for sub-0.5pm gate by using i-line optical aligner: (a) SOG coating, curing and PR patterning through gate mask, (b) PR re-flow to form a taped wall profile with a reduced length U; (c) SOG etch and An metal deposition and (d) lift-off process and SOG removal.

4. Results and discussion

Figure 3 summarizes the extended length of resist ( A L) as a function of re-flow temperature (T) and re-flow time (t). The filled symbols are obtained by fixing re-flow Temperature at 120 'C and changing the re-flow time, while those unfilled symbols are obtained by fixing t=5 minutes and changing T. From experimental results, we do not find obvious influence of patterned window size on extended length. The measured A L increases from 0.075 to 0.275 pm as the temperature increases from 100 to 160 C at a fixed 5-minute re-flow time. On the other hand, the measured A L increases from 0.1 to 0.25 $m as the time increased from 1 to I O minutes, where the re-flow temperature is maintained at 120 'C . Note also that the extended lengths are nearly linear to re-flow time (solid line) with an empirical equation as A L=O.lS+[(T-4)/50] Qm). The same results can be obtained for changing temperature ranged from 110 to 150 T (dashed line) and the empirical equation is A L=0.1+0.1625~[(t-100)/50]

For a 0.8 to 1.2ym open window size, the extended length of resist should be chosen in the range of 0.2 to 0.35 pm for achieving a sub-0.5-pn gate length. Since the final gate length depends on feature size of resist after thermal-bake process, one can appropriately choose either re-flow temperature or re-flow time to implement the required gate length.

(pm).

215

Re-Flow Time, t (min) 0 1 2 3 4 5 6 7 8 9 1 0 1 1 0 . 3 5 . , , , , . , . , . , . , , . , , ,

Re-Flow Temmrature : 120 QC

h c

0.05l e ' ' ' ' ' 90 100 110 120 130 140 150 160

Re-Flow Temperature, T ("C)

Fig. 3 extended length of PR ( A L) as a function of re-flow temperature and re-flow time.

Figure 4 shows some typical SEM pictures demonstrating the taped wall profile of resist being thermal re-flowed. Figs. 4(a) and 4(b) show the 0.48- and 0.67-pm final feature size that obtained from 1.0- and 1.2-pm patterned size, respectively, by t=5 minutes and T=150 'C. Figs. 4(c) and 4(d) also show the taped wall profile and undercutting after thermal bake and spin-coated SOG being isotropic etched. Therefore subsequent deposited gate metal through such a window with undercutting could be easily and reliably fabricated during lift-off process. This can significantly improve the - - . . fabrication yield eien i t a thick pate-metal I( Jepihited.

.. ---. . @.ip f4

,%sx&u,r..

Fig. 4 SEM pictures show the taped resist wall profiles after thermally re-flowing (a)-(c) and the undercutting after isotropic etching SOG

Figs. 5(a) and 5(b) show the room-temperature common-source characteristics for the fabricated HDCFET's with an effective gate length L'=0.41 and 0.67

pm, which are obtained from 0.8- and 1.2-pm patterned resist and are processed using the technologies described above. The L=1.0 and 1.5-pm gate HDCFET's fabricated using conventional processes without additional thermal bake for resist are also included for comparisons, as shown in Figs. 5(c) and 5(d). All devices have a 100-pm gate width. The used gate-source voltage (VGs) is 4 . 2 V per step with the top line of Vcs=O V.

- E E Q E

k U

. - c C Y

C .-

0 1 . 2 3 4 -1

0 1 2 3 4 Drain-to-Source Voltage (V)

Fig. 5 measured common-source I-V characteristics for newly designed HDCFET's with a 100-pm gate width. The used VGS is 4 . 2 V/step and the VGs for the top line is 0.0 V.

In order to further demonstrate what benefits can obtain from such a designed structure together with this new technology, we refer to the HDCFET dc and ac performances. Figure 6 shows the transconductance (gm) and drain saturation current (Ios) as a function of VGS for 0.41-, 0.67- and I.O-pn HDCFET's. They are deduced from Fig.5 with a fixed VoS=4.0 V. We find that the transconductance ' increases with increasing VGS and finally saturates at VGs=O.O V. In general, HEMT's have their transconductance decrease rapidly as Vos>o.O V due to parallel conduction. No clear degradation of transconductance at V,+O V was observed in our HDCFET's. This is a benefit of a HDCFET with an undoped wide-gap material as a Schottky barrier. In addition, the triangle-like well also provides sufficient confinement action to electrons, resulting in a low leakage current. As can' he found in Fig.6, the output conductance (gd) measured at VGs=O.O V and VDs=4.O V are as small as 8.3, 8.6, and 12.7 m S / m for0.41-, 0.67- and 1.0-pm HDCFET's, respectively. This again indicates that good confinement to electrons is obtainable for shortening gate length to sub 0.5 pn. Of course, the small aspect ratio due to both very thin Schottky and channel

216

layers (200 8, and 150 A) is also advantageous for reducing short-channel effects. For a 1x100 Fm2 HDCFET, the Ins at Vcs=O.O V is 368 d m m with the maximum gm=280 m S / m . However, the 1,s at V ~ ~ = 0 . 0 V and the maximum gm can he improved to 535 m A / m and 370 m S / m for a 0.41~100 pmZ HDCFET. Together with the known output conductance, the open-drain voltage gain (Av=gm/gd) is calculated to be larger than 42 for a 0.41~100 pm2 HDCFET.

Drain-to-Source Voltage VDs (V) 0 1 2 3

450 I Gate Width= I OOpm

400

350

2 300 3 j E 250

200

8150

LOO

50

0

- ,.

; *a

-1.8 -1.2 -0.6 0.0 Gate-to-Source Voltage VGs (V)

Fig. 6 Transconductance (g,,,), drain current (Ios) as a function of Vos. Dependence of output conductance on VDs is also included.

The microwave characteristics of the fabricated HDCFET's are measured at Vcs=O.O V and VoS=4.0 V by an HP8510B network analyzer in conjunction with Cascade probe. Figure 7 summarizes the dependence of the maximum transconductance, the cutoff frequency, and the maximum oscillation frequency of fabricated HDCFET's on &e gate length. In this region of the available gate length, the threshold-voltage shift is very small since a very thin InGaP layer and hence a very small aspect ratio is employed. All measured results increase with reducing gate length. The reduced capacitance and electron velocity overshoot really enhance both dc and ac performance as gate length is sholtened. The maximum f, and f m ~ r are 26 and 32 GHz, respectively, for the 0.41-$m gate-length HDCFET.

5. Conclusions

We have successfully developed a new sub-0.5-pm gate-length FET processing technique by i-line optical

lithography in this study. The key feature is to thermally re-flow the patterned photo-resist upon two-step spin-coated SOG The SEM pictures confmed that a taped resist wall profile and hence the final window size could be easily controlled by either re-flow temperature orre-flow time. Thus the deposited gate metal has its final length and thickness be separately determined by taped resist profile and SOG thickness. A newly designed HDCFET fabricated by employing this method has a gate length of 0.41 pm. Furthermore, the HDCFET exhibits the maximum transconductance of 370 m S / m with an output current lager than 535 mA/m andft (frnax) of 26 (32) GHz.

.,,,, * ...... Maximum Oscillation Frequency ___..__. Cutoff Frequency

- 50 ' ' ' ' ' ' ' ' ' ' ' ' - 41) 2 45

ij \--Trmconductance I 4 30

5

U e O ' 014. 0:6 0:s ' 110 ' 1:2 114 116 Gate Length (pm)

Fig. 7 Dependence of the maximum tansconductance, the cutoff frequency, and the maximum oscillation frequency of fabricated HDCFET's on the gate length.

Acknowledgments This work is partly supported by National Science

Council under the contract No. NSC 92-2215-E-019-001.

References

[I]. Ahmed M M, IEEE Trans Electron Devices 47 (2000) 299. 121. Chen H R, Wu M Y, Lour W S , Hung G Land Shih Y M,

Semicond. Sci Technol. 14 (1999) 312. 131. Lour W S , Chang W L. Liu W C, Shie Y H, Pan H J, Chen I

Y and Wang W C,Appl. Phys. Len. 74 (1999) 2155. [41. Liu W C, Chang W L, Pan H I, Yu K H, Feng S C and Lour

W S,Appf. Phys. Len. 74 (1999) 1996. 151. Nishimura K, Onodera K, Aoyama S, Tokumitsu M and

Yamasaki K, IEEE Trans. Electron Devices 44 (1997) 2113.

161. Mahajan A, Arafa M, Fay P, Caneau C and Adesida I IEEE Trans. Electon Devices 45 (1998) 2422.