Gate current: Modeling, A L extraction and impact on RF performance

R. van Langevelde, A.J. Scholten, R. Duffy*, EN. Cubaynes*, M.J. Knitel and D.B.M. Klaassen

Philips Research Laboratories, Prof. Holstlaan 4,5656 AA Eindhoven, The Netherlands Phone: +3 1-40-274241 8; Fax: +3 1-40-27441 13; E-mail: ronald.van.langevelde@philips.com

* Philips Research Leuven, Kapeldreef 75, B-3001 Leuven, Belgium

Abstract In this paper a new physical gate leakage model is introduced,

which is both accurate and simple. It only uses 5 parameters, malung parameter extraction straightforward. As a result the model can be used to extract effective length for modern CMOS technologies. The influence of gate current on the RF perfor- mance is studied.

Introduction With CMOS technology downscaling the increasing gate

leakage current seriously starts to affect circuit design. Nev- ertheless, the compact modeling of gate current is a relatively unexplored field [l-31. In this paper a new physics-based gate leakage model is introduced, which is at least as accurate as other models [3,4], but much simpler. It only uses 5 parameters, making parameter extraction easy and straightforward. Further- more, the model validity range is tested for thin oxides. Next, we show how the gate current can be used to extract AL. Up till now the study of gate current impact on circuit behaviour has been limited to digital considerations, e.g. stand-bye power dissipation and charge storage [5]. In this paper we study, for the first time, the impact of gate current on RF performance.

Gate current model The new gate current model is shown in Figs. 1 and 2.

It is part of a new compact MOS model, MOS Model 11, which is based on the explicit formulation of surface poten- tial & [6, 71. In the inversion region the intrinsic gate cur- rent ZGC consists of electrons (NMOS) or holes (PMOS) tun- neling from the inversion layer. The current continuity equa- tion ( a Z ~ s / a x = -W - JGC) is solved to calculate ZGC, under the assumption that ZGC only induces a small perturbation of the potential distribution along the channel ( ~ Z D S / ~ X z 0). Us- ing eq. (1) and (2) , ZGC can be solved from eq. (3). Under the same small-perturbation assumption the partitioning of ZGC can be simplified to eqs. (4) and (5). In accumulation the intrinsic gate current consists of electrons tunneling from gate to bulk in NMOS or vice-versa in PMOS [3]. Since no channel current is flowing, the solution of ZGB is straightforward. The overlap re- gions are considered as MOS-structures with different flat-band voltage and body factor. The overlap currents consist of elec- trons (NMOS) or holes (PMOS) tunneling from the accumula- tion layer in the overlap regions to the gate or vice-versa. In- cluding all the above components, the model gives an accurate

Used variables:

vox = vas- vFB -$p-$.s . +p = vGB - vFB - +s + -

Qinv = -Cox . (Vox - ko . &) G -Cox . Vinv

(7 %I2 Channel current: I D S = - p . W . [ Qinv. 2 -

. %]

p b T ( v 0 ~ 1 a 2 'e- fox

IGC = W . jk JGC . dx

(1)

Direct-tunnelling probability [SI:

B ~ox~[l-(l~oox/x~)3'*~ 3 - 3-y k . e - 2 ' XB , e g . Xgz ' Ox

Gate-to-channel current in inversion (VGB > V m ) [8]:

JGC = -Qinv g T ( Vox] % . Vox . Vinv . ,B*'v"X (2)

(3) Partition: IGS = W . (1 - x / L ) . JGC . dx (4). IGJJ = IGC - IGS ( 5 )

Gate-to-bulk current in accumulation (VGB < V m ) :

JGB = -cox ' vox. p b T ( - v o x ] , IGB % IGACC. vox2 .e-B*'vox (6)

Gatdsource or gatddrain overlap current (where X= S or D):

Voxov = VGX - VFBOV - *pOv - *so" 2

*PO" = (Jvm - VFB,, - +so, + y - 9) IC,, % ~Gov . voxov2 . (eB*.Voxov - e-B*'Voxov 1 (7)

Figure 1: Equations for gate current model. Vm and V m o v denote flat-band voltage of the intrinsic resp. overlap regions, and ko and kp denote body factor of the bulk silicon resp. gate polysilicon. B is a physical constant, and XB is the oxide potential barrier (both differ for electrons and holes). Parameters IGINV and IGACC scale with gate area (a W . L ) , and 1 ~ 0 ~ scales with width (a W).

1 .E49

1 .E-I 0

A 1.E-11 5 2 l.E-12

1 .E-1 3

l.E-14 - . I

-1.5 -1 -0.5 0 0.5 1 1.5

vGS

Figure 2: Gate current as a function of gate bias, symbols are measure- ments and lines are modelled results. All current components, intrinsic ( I G C and IGB) and extrinsic ( I G , ~ ) , as described in Fig. 1 are shown. (NMOS, W / L = 10pm/0.6pm, rox = 2.2nm, VDS = 0.OV)

0-7803-7050-3/01/$10.00 02001 IEEE 13.2.1 IEDM 01-289

2

- Model with QM-effects

... Model without QM-effects 1.5

3 - 1 c) -

0.5

0 0.4 0.8 1.2

V G S (v) Figure 3: Gate current as a function of VGS for two values of V ~ B . Quantum- mechanical lowering of potential barrier XB is taken into account. (NMOS, W / L = 10pm/lOpm, fox = 1.7nm, V D ~ = 50mV)

1 .E+02

l.E+01

l.E+00 E 2 l.E-01

1 .E-02 5 0

l.E-03

1 . E-04

1 .E-05

I Measurement

I

0 0.5 1 1.5

V G S (v) Figure 4: Gate current density as a function of gate bias for different values of oxide thickness. (NMOS, VDS = 0.OV)

description of ZG (Fig. 2), using only 5 adjustable parameters: ZGINV, ~GACC, ZGOV, B: (for electrons) and Bp‘ (for holes).

Carriers at the oxide interface are confined to a narrow po- tential well, resulting in energy quantization, which affects the surface potential [9] and the effective oxide potential barrier [8]. An effective potential barrier XB - AXB has been introduced (adding no parameters), where AXB o< E ~ R ~ ’ ~ and Eeff is the effective field. It results in an accurate description of the quan- tum effects at various VSB (Fig. 3). Similar accuracy is obtained for various tox (Fig. 4), and for the VDS dependence (Figs. 5 and 6). The ZGS/ZGD partition cannot be verified using measure- ments. In Fig. 7, it is therefore verified by breaking down the MOSFET into N = 10 equal segments, each described by the above model, similar to [ 101. The partition, which follows nat- urally from the segmentation model, is accurately reproduced by (4) and (5) adding no parameters.

Model validation for thin oxides The perturbation assumption may not hold true for future

technologies where JGC will be large. In Fig. 8, this is in-

1 .E-04 1. Measurements -Model I 1 .E-05

1 .E-06 CI

5 1 .E-07

0 z

1 .E-08

1 .E-09

l.E-10 -1.5 -1 -0.5 0 0.5 1 1.5

vGS (v) Figure 5: Gate current as a function of gate bias for various values of drain bias. (NMOS, W / L = 10pm/0.6pm, fox = 1.4nm)

1 .E-09

I 1.E-11 1 I

1 .E-I2 0 0.5 1 1.5

vDS (v)

Figure 6: Gate current as a function of drain bias for various vdues of gate bias. (NMOS, W / L = IOpm/IOpm, rOx = 2.2nm)

1

0.8

n W

0

U) 0.6 Q

- \ - 0.4

(3

% 0.2 0

0 -

- Compact model

- I G S ~ I G V G S = 1.5 v

A Segmentation model

Figure 7: Modelled partition of IGS and IGD current components as a func- tion of drain bias are verified using a segmentation model (N = IO). (NMOS, W / L = IOpm/0.6pm, fox = 2nm)

vestigated by comparing the compact model with the segmen- tation model using parameters scaled according to the ITRS roadmap [ 1 11 down to 50nm CMOS for pure Si02 gate oxides (worst case). Clearly, the perturbation assumption is valid for

290-IEDM 01 13.2.2

1 .E-03

1 .E-04

1 .E-05

3 l.E-06 +* l.E-07

1 .E-08

1 .E-09

l.E-10

1. Seamentation model I "

- Compact model 50nm CMOS I

0 0.5 1 1.5

V G S (v)

300

0

1000 1. Segmentation model

0 0.2 0.4 0.6 0.8

V G S

G n Y

500 (3

0 0

0

Figure 8: The small perturbation assumption is verified using a N = 10 seg- mentation model for minimum channel length devices in future technologies, following from ITRS-specifications.

Figure 10: The influence of gate current on the potential dis&ibution, see ~ i ~ . 9, behavior: gate capacitance, drain current as well as gate current decrease as compared to the perturbation theory.

in different

.--- with gate current

gate current - Q = a, 0

a, C C

c 200 U

p, I00

2 0 0

-100

5: fi E .- x

I ""V

100

10

1

Gate current dominated operation

Normal MOS operation

0 0.2 0.4 0.6 0.8 1

x / L (-)

~

.,.I

130 100 70 50 Technology Generation (nm)

Figure 9: The predicted influence of gate current on the channel potential distribution for an L = 0.5km device in 50nm technology. The influence of IG is no longer negligible, which results in different behavior, see Fig. 10.

Figure 11: The maximum value of channel length below which the transistor still functions as a M O S E T (i.e. IDS >> I ~ ) for CMOS technologies scaled according to the ITRS roadmap [ I l l .

short-channel devices down to the 50nm node. However, for longer channel lengths this may not be the case, see Fig. 9, re- sulting in a decrease in gate capacitance, ZG and ID, see Fig. 10. The overall MOSFET behavior is dominated by ZG, and our model is no longer accurate. As a rule of thumb the perturba- tion assumption breaks down when ZG is in the same order of magnitude as the on-current. The maximum channel length be- low which the transistor still operates as a MOSFET, is shown for future generations in Fig. 1 1.

Extraction of A L L&awn - L is a prerequisite for

compact modeling, since it affects I - V , C-V as well as noise characteristics. In addition, a A L which is consistently used in both DC and AC is required for statistical simulation [ 121. For modern devices with pocket implants, however, the tradi- tional extraction method of A L using gain factor /3 is not accu- rate anymore [ 13, 141. An alternative method using CGB measu- rements looks promising [14, 151, but the increased ZG in fu-

A realistic value of A L

ture devices interferes with accurate capacitance measurements. However, since both ZGINV and IGACC scale with gate area, see Fig. 1, either one can be used to extract A L (or A W). The accumulation behavior is insensitive to VT and poly-depletion favoring ZGACC. Plotting the extracted ZGACC as a function of mask length, A L can be determined (Fig. 12). The obtained A L corresponds with the one obtained from CGB.

Impact on RF performance In order to investigate the impact of IG on RF performance

we have simulated the cut-off frequency fi, the maximum os- cillation frequency fma, the input impedance, the minimum noise figure (taking into account shot noise in the gate leakage), linearity and the matching behavior for future short-channel de- vices. It was found that f+, fma as well as the linearity figure are not affected by ZG down to 50nm. The input impedance, however, changes significantly with increasing IG, see Fig. 13, resulting in an increase of the input resistance, which may fa- cilitate impedance matching for RF design. This increased in-

13.2.3 IEDM 01-291

? - I Model with I G and RG

n E > t v

B 0

Figure 12: Extraction of AL using capacitance CGB in accumulation: squares are measured results ( IVGS~ = 1.8V , VDS = OV) and dashed line is scaling rule. The same value of AL can be extracted by optimizing gate current model for different mask lengths and using the results for extracted parameter IGACC: bullets are extracted results and solid line is scaling rule. (0.18pm CMOS, tox = 3.2nm)

1000 I--- Model with I G - Model without IG I A c:

100 Y

al 0 c m

U)

c U) 10

2 .- c

2 1 c - 0. I

I 1 OOnm CMOS I I I I 0 0.4 0.8 1.2

V G S

Figure 13: Predicted input resistance, Re(l/YGG), as a function of gate bias for short-channel devices in future CMOS technologies as calculated from segmentation model. The influence of gate current is shown. ( NMOS, W = 60 x 3pm, VDS = VDD, f = 2GHz )

put resistance furthermore results in an increase in minimum noise figure, which is significant at f = 2GHz and decreases with increasing frequency. The impact of ZG on matching is studied by looking at the influence of fox variations on the on-

= 0.2 0

a P

.- U

L .I- U)

U - 0.1 .-

.- s c

c v)

m .- 5i

0 0.5 0.6 0.7

/ O N / w (mAlPm)

Figure 14: Statistical analysis of the on-current of a 50nm n-MOS transistor assuming only oxide thickness variations (U = 5%). The influence of gate current (solid lines) and polysilicon gate resistance (Rpoly = lOQ/O) for two channel widths (dashed lines) are investigated.

current, see Fig. 14. The spread in Zon only changes slightly due to ZG for the 50nm device. However, gate resistance RG may lead to an effective gate bias drop resulting in a decrease of ZD and ZG [ 161, thus affecting matching behavior consider- ably, see Fig. 14. This can be prevented by minimizing RG using multi-finger layouts 1171.

Conclusions A new model for gate current has been developed suitable

for compact MOS models. It includes physical partitioning and quantum-mechanical quantization effects. Using only 5 parameters, the model gives an accurate description over the whole operation region, and scales well with geometry and ox- ide thickness. The model can furthermore be used to extract A L for modern CMOS technologies where convent iona l extraction methods fail. It has been found that, except for the noise figure, most of the RF performance of short-channel devices will be unaffected by the increased gate current with CMOS downscal- ing. Furthermore, if care is taken to minimize gate resistance, the matching properties will not change significantly. References

P. O’Sullivan et al., ESSDERC’99, p.488 C.-H. Choi et al., IEDM’99, p.735 K.M. Cao etal . , IEDM’OO, p.815 www-device.eecs.berkeley.edu/ bsim3 P.J. Wright et al., IEEE Trans. El. Dev., 37, p.1884, 1990 www.semiconductors.philips.com/Philips-Models R. van Langevelde et al., ESSDERC’OI, p.81 Z.A. Weinberg, J. Appl. Phys., 53, p.5052, 1982 R. Rios et al., IEDM’95, pp.931 A.J. Scholten er al., IEDM’99, p.163 www.itrs.neV1999-SIA-Roadmap M. van Dort et al., IEDM’95, p.941 H. van Meer et al., IEEE El. Dev. Let?. ,21, p. 133,2000 A.J. Scholten et al., ESSDERC’OI, p.311 T.S. Hsieh et al., ICMTS’OI, p.263 M. Koh et al., IEDM’98, p.919 L.F. Tiemeijer et al., IEDM’OI

292-IEDM 01 13.2.4