Impact of 0.25pm dual gate oxide thickness CMOS process on flicker noise performance of multifingered deep-su bmicron MOS devices

1 ,

K.W.Chew, K.S.Yeo, S.-F.Chu and YM.Wang

Abstract: The flicker noise performance of 0 . 2 5 ~ thin gate oxide transistors from the dual gate oxide thickness process and the single gate oxide thickness process have been evaluated and compared. A total of 20 transistors have been measured. The results reveal that thn gate oxide transistors from the dual gate oxide thickness process show a maximum of an order reduction in the current noise spectra. This reduction can be attributed to the lower nitrogen concentration peak at the Si/Si02 interface. Hence the dual gate oxide thickness process will be the state-of-the-art for the implementation of system-on-chip designs. In general, the low-frequency noise behaviour of the fabricated deep-submicrometre MOSFETs is best described by the number fluctuation with correlated mobility fluctuation model.

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1 Introduction

With the aggressive scaling down of CMOS into the deep- submicrometre regime, coupled with its high-density inte- gration capability and low manufacturing cost, CMOS technology has become a viable option for implementing front-end transceiver systems. Voltage-controlled oscillators (VCOs) are one of the essential building blocks of such sys- tems, where the spectral quality of the local oscillator signal influences the out-of-band interference. The low-frequency noise behaviour of deep-submicrometre MOSFETs will impact on the phase noise of these nonlinear circuits. This is because, first, with the scaling down of technology the corner frequencies of the low-frequency noise, also known as flicker or llfnoise, tend to become higher [I]. Secondly, the llf noise spectrum at low frequencies can be up-con- verted to high frequencies giving rise to a llf3 sideband around the carrier frequency [2, 31. Hence one will not be able to get the same noise performance for VCOs imple- mented in CMOS technology as compared with those implemented in bipolar technology.

To enable system-on-chip (SoC) design to be imple- mented in CMOS technology, it is necessary to provide multiple supply voltages on the same wafer. Ths requires the ability to grow multiple gate oxide thicknesses simulta- neously. Dual-thickness gate oxide technology offers high- voltage thck gate oxide MOSFETs for circuits requiring a large signal swing such as inputloutput stages and lugh- gain amplifiers, whereas the low-voltage thin gate oxide MOSFETs cater for high-speed applications. This offers definitive advantages for SoC design integrating radio-

0 IEE, 2001 ZEE Proceedings online no. 20010626 DOL 10.1049/pcds:20010626 Paper fmt received 30th November 2000 and in r e d form 19th June 2001 K.W. Chew, S.-F. Chu and Y.M. Wang are with Chartered Semiconductor Manufacturing Ltd., Singapore 738406 K.S. Ye0 is with the School of Electrical and Electronic Engineering, Nanyang Technological University, Nanyang Avenue, Singapore 639798

frequency (RF), analogue and digital circuits. For this reason, worldwide foundries have begun offering the dual thickness gate oxide process (henceforth called the dual gate oxide process) starting from the 0 . 2 5 ~ technology, whereby 2SV, 5nm thin gate oxide devices were developed for the core chip area and 3.3V, 7nm thick gate oxide devices were developed for the input/output , (YO) area. However, due to the additional processing steps required to incorporate the two different gate oxide thicknesses, the flicker noise performance of devices fabricated using the dual gate oxide process needs to be re-evaluated. Th~s moti- vates us to study and compare the flicker noise perform- ance of 0.25 pn multifingered devices, which have been laid out for wireless applications, fabricated from the dual gate oxide process and the standard thickness gate oxide process (henceforth called the single gate oxide process). We also attempt to identify the dominant noise mechanism at different transistor biasing conditions.

2 Review of flicker noise theories

Flicker noise in MOSFETs has been extensively studied in the past [4]. In the early days of flicker noise research in MOS transistors, two different theories have been raised to explain its physical origins.

In the carrier number fluctuation theory, originally pro- posed by McWhorter [5], the flicker noise is attributed to the random trapping and detrapping processes of charges in the oxide traps near the Si-Si02 interface [6-11]. The charge fluctuation in turn modulates the channel carrier density. Several assumptions have been made in formulat- ing the carrier number fluctuation model. The key ones are (U) The MOSFET is biased in the strong inversion regon so that carriers in the conduction band tunnel directly intoand out of the oxide traps at the same energy level. Inelastic tunnelling is regarded as unlikely [ 121. (b) The MOSFET is biased in the linear region so that we can assume band bending to be nearly constant along the channel from the source to the drain.

IEE €'roc -Circuits Device5 Syst Val 148, No 6, December 2001 312

For a MOS device with an area W x L and having carriers with mobility p, the corresponding drain current noise power spectral density according to the carrier number fluctuation model is given by [13]

where S, represents the carrier number fluctuation power spectral density defined in [13]. The normalised drain current noise power spectral density is defined as sld/Iz. Following this definition, it can be deduced that the normalised drain current noise spectral density for the carrier number fluctuation model is proportional to the ( g , / I d ) 2 ratio. The corresponding input- or gate-referred noise spectral density, which is defined as S , = Sld/gm2, is given by [ 141

where a, is the tunnelling parameter and Nt(Ef) is the oxide trap density in an energy interval of (+kT) around the electron quasi-Fermi level in silicon. Eqn. 2 predicts no explicit gate voltage dependence of the MOS transistor flicker noise in linear operation.

The mobility fluctuation theory [15-171, on the other hand, considers flicker noise as a result of fluctuation in bulk mobility. This theory is based on Hooge's empirical relation for the spectral density of flicker noise in a homo- geneous sample [18]. Adapting Hooge's model to a typical MOS transistor in the linear region, the normalised drain current spectral density is given by [19]

(3)

and the input-referred gate voltage noise spectral density in strong inversion is given by [13]

(4)

Eqn. 3 shows that the normalised drain current noise spec- tral density follows a l/Ntotal or a 111, law. Ths implies that the normalised drain current noise spectral density should increase exponentially in weak inversion due to the expo- nential variation of the drain current with the gate over- drive voltage. Eqn. 4 shows a linear dependence of Svg with the gate overdrive voltage in strong inversion.

Some authors have combined both the carrier number and the mobility fluctuation models to explain a broader set of data 120-221. However, they have combined the two theories in an uncorrelated manner, whereas in fact both fluctuations arise from the same mechanism. More recently, with the availability of submicrometre MOSFETs, researchers are able to study the noise generated by individ- ual oxide traps [23-251. Capture and emission of a channel carrier by the oxide traps results in discrete modulation of the channel current resembling a random telegraph signal (RTS). Based on the new information obtained from the study of RTSs in small area MOSFETs, researchers have proposed a comprehensive flicker noise model, which incorporates both the carrier number fluctuation and the mobility fluctuation mechanisms in a correlated manner [14, 19, 261. The drain current noise spectral density in this concept is given by [26]

where a,, is a scattering parameter.

IEE Proc.-Circuits Devices Syst., Vol. 148. No. 6. December 2001

The sign of the mobility term in eqn. 5 is chosen accord- ing to whether the trap is neutral or charged when filled. The input-referred gate voltage noise spectral density can be written as [26]

Eqn. 6 predicts that SVg will show a quadratic increase (or parabolic dependence) with the gate overdrive voltage.

3 Device fabrication and measurement

Fig. 1 shows a block diagram of a portion of Chartered Semiconductor's 0.25 pn CMOS baseline process flow and the necessary plug-in modules to achieve the dual thckness gate oxide process. The single gate oxide process flow starts with the shallow trench isolation (STI) scheme; lOnm sacn- ficial oxide growth; followed by well and channel dopants implantation; sacrificial oxide removal; 4.3 nm oxynitride (N,O) gate oxide growth; polysilicon gate patterning; lightly-doped drain (LDD) implantation; nitride spacers formation; source and drain regions implantation; silicida- tion; contact formation; metallisation and finally passiva- tion.

STI

...

thick gate oxide arowth (5.0nm) " . . I

thick gate oxide etch

for thin aate area

pre-thin gate clean gate poly deposition

followed by standard .. .

b Fig. 1 Block diigrum showing key d&rences between Chrtered Stmicon- ductor j. 0 . 2 5 ~ buselhe CMOS single gate oxide rmd dual gate ox& process

a Baseline process b Plug-in modules for dual thickness gate oxide process STI = shallow trench isolation

pow

For the dual gate oxide process, prior to the 4.3nm oxynitride (N20) gate oxide growth, a 5.0nm thick gate oxide is grown. Ths gate oxide functions as the gate dielec- tric for the thick gate transistor area, and acts as a sacrifi- cial oxide layer for the thm gate transistor area. In the latter, this oxide layer is subsequently etched away using an additional mask. Next a hydrofluoric (HF) acid clean is carried out before proceeding back to grow a 4.3nm of oxynitride (N20) gate oxide for the thin gate transistor area. The subsequent processing steps are similar to that of the single gate oxide process.

In retrospect, the thin gate oxide transistors of the dual gate oxide process effectively undergo two cleaning cycles since as mentioned earlier, the gate dielectric of the thick gate area also acts as a sacrificial oxide for the thin gate area. In contrast the transistors of the single gate oxide process undergo only one cleaning cycle.

313

The test structures available for measurements are all minimum channel length devices. The devices are layout as an array of single transistors (also known as 'fingers') con- nected in parallel. Multifingered transistor layout ensures enough current drive for wireless applications. The devices are identified by the length of each finger Wj, the width of each finger L and the number of fingers Nj.

On-wafer measurements have been carried out using the Cascade Microtech probe station, An HP41 56 parametric analyser has been used to provide the biasing voltages at the device's source, gate and bulk, and to provide a con- stant current source at the device's drain. The voltage noise at the drain is fed to a low-noise voltage amplifier and the amplified signal is output to the HP35670A dynamic signal analyser. The background noise level has been corrected for by performing noise measurements at the drain bias of 500pV. For subsequent measurements, this background noise level is subtracted away from the measured data.

1 0 7

4 Results and discussion

Fig. 2 shows the drain current noise spectral density versus the frequency for SG and DG NMOSFETs and PMOS- FETs corresponding to Nr = 28, Wf = 2 . 3 8 ~ and L = 0 . 2 4 ~ . SG refers to MOSFETs fabncated from the single gate oxide process and DG refers to thn gate oxide MOSFETs fabricated from the dual gate oxide process. The fitting has been achieved using the HSPICE level-3 flicker noise model given by [27]

- 0

I

KF is a technology and bias dependent noise parameter. AF is the frequency exponent that can vary from 0.7 to 1.3 [13]. For an ideal flicker noise spectrum, AF is equal to 1. Table 1 compares the KF and AF values for a total of 20 devices.

1 10 1'02 1 03 1 04 frequency, Hz

Fig. 2 Compariron of &ail current noise power spectra for SG and DG NMOSFETs and PMOSFETs with nianber of fm ers N - 28, length of each fmger = 2.38 pn and wulth of each fmger L = f 2 4 d - Solid lines represent the fitting by HSPICE level-3 flicker noise model U NMOS SG A NMOS DG 0 PMOS SG 0 PMOS DG L = 0 . 2 4 ~ ; W,o, = 6 6 . 6 4 ~ ; N,= 28; IVJ = 2.5V; iVgl = 0.7V

We observe from Fig. 2 that at constant Vg and in weak inversion, the NMOSFETs are noisier than the PMOS- FETs. Intuitively, electrons have higher mobilities than holes. By using the Hooge's flicker noise model, the Hooge's parameter can be given as [28]

a H = a l a t t (k)2 (8)

Since the Hooge's parameter is proportional to the effective mobllity, whch is dominated by the parameter p in weak inversion, from eqn. 4, it can be seen that a higher effective mobility would lead to more flicker noise.

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Table 1: Comparison of HSPICE level-3 flicker noise model KF and AF noise coefficients for five NMOS SG transistors, five NMOS DG transistors, five PMOS SG transistors and five PMOS DG transistors for dimensions specified

MOSFET Nfx Wfx L dimensions (w2) KF(V2F) AF

8 x 9.58 x 0.24 NMOS SG 1.5 x 0.9

8 x 9.58 x 0.24

8 x 9.58 x 0.24

8 x 9.58 x 0.24

12 x 4.78 x 0.24

12 x 4.78 x 0.24

12 x 4.78 x 0.24

12 x 4.78 x 0.24

28 x 2.38 x 0.24

28 x 2.38 x 0.24

28 x 2.38 x 0.24

28 x 2.38 x 0.24

56x1.18x0.24

56 x 1 .I8 x 0.24

56x 1.18x0.24

56x1.18x0.24

116 x 0.58 x 0.24

11 6 x 0.58 x 0.24

11 6 x 0.58 x 0.24

116 x 0.58 x 0.24

NMOS DG

PMOS SG

PMOS DG

NMOS SG

NMOS DG

PMOS SG

PMOS DG

NMOS SG

NMOS DG

PMOS SG

PMOS DG

NMOS SG

NMOS DG

PMOS SG

PMOS DG

NMOS SG

NMOS DG

PMOS SG

PMOS DG

5.5 x 0.9

1 . 3 ~ 10-24 1.2

4.9 x 10-~5 1.2

7 . 5 ~ 10-24 1.1

5 . o ~ 10-24 1.1

7.0 x 1.1

4.8 I 0-24 0.9

7.5 x 0.9

1 . 5 ~ 1.1

3 . 6 ~ 10-25 1.1

6.0 x 1.1

1 . 2 ~ 1.1

3.5 x 1.1

6.ox 10-25 1.1

9.8 x 10-25 I .o 3.5 x 1 0-25 I .o 3.8 x 1 0-25 I .I 1 . 5 ~ 10-~5 1.1

1 . 8 ~ 1.1

Fig. 3 shows a comparison of our extracted Hooge's parameter with those published in the literature [26, 291. Our extracted Hooge's parameter values are at least one order lower than those reported at IV,l = 1.5V, thus reflect- ing our state-of-the-art processes. Furthermore the Hooge's parameter values for the DG transistors are lower than those for the SG transistors. Ths reinforces the observation from Fig. 2 that the dual gate oxide process results in thin gate oxide transistors with better flicker noise performance than their counterparts from the single gate oxide process. This is consistent with the earlier description that thn gate oxide transistors from the dual gate oxide process experi- ence two cleaning cycles.

0 m

I"sl." Fig.3 Comparison of extracted Hoo e's parameter vdues for SG and DG NMOSFETs and PMOSFETS with &&kd &tu /26, 291 - - 0 PMOSSG NMOSDG 0 PMOSDG 0 PMOS [29] 0 NMOSSG + NMOS[26]

To further support this observation, conventional base- level charge-pumping measurements have been carried out and the results for a NMOSFET shown in Fig. 4. It can be

IEE Proc.-Circuits Devices Sy.st., Vol. 148, No. 6, December 2001

seen that indeed the charge-pumping current level for the DG transistor is lower than that of the SG transistor. To locate the root cause of this decrease in charge-pumping current level for the DG transistor, SIMS analysis has been performed on both the SG and DG transistors. The results are shown in Fig. 5. We conclude that the I l f noise improvement is mostly likely caused by the lowering of the nitrogen concentration peak at the interface between the gate insulator and the silicon for the DG transistors.

.

-:- polysilicon gateloxynitride j Si sub

1

Si (counts) ->

I 6 t 12 - - - 106

105

i o 4

I -1 0 1 2 3 4

v,, v Fig.4 Ver$caiwn of observed flicker noise improvement wing bme-level chrge-pmping technique Trapezoidal gate pulse with period of Sp, riseifall gradient of 5OnsN and a pulse height of 3V has been used. Start base voltage is -3.W and stop base voltage is O S V in steps of 0.2V -0- dualgate ,

-0- single gate

2c

16

I€

14

g 7-

5 1: $

‘5 0

B 1c c 0 ._ c F F E 8 00

6

4

2

0 I 1 50 100 150

depth, nm Fig. 5 Comparison of SIMS mlysis performed using polysilicon-oxiuksili- con capacitor shuciwe with area of 47.7378pd for both SG and DGprocesses ~ SG

DG _ - - _

Fig. 6 shows the input-referred noise spectral density Svg against the gate overdrive voltage. For Vh = 1 .OV, a quad-

IEE Proc.-Circuits Devices Syst.. Vol. 148, No. 6, December 2001

ratic increase of Svg with the gate overdrive in s t rong inver- sion is observed for both the SG and DG transistors, while there is a slight rise of Svg in the weak inversion region. This trend suggests that carrier number fluctuation with correlated mobility fluctuation dominates, The carrier number fluctuation model can account for the slight varia- tion of Svg in the weak inversion region if different types of traps (donors and acceptors) are considered [19]. When V, is increased to 2SV, the DG NMOSFET shows a rela- tively constant noise level suggesting that the carrier number fluctuations dominate. For the SG NMOSFET, there is a strong increase of Svg in the weak inversion region. The mobility fluctuation model can explain this phenomenon. The gate voltage spectral density of the mobility fluctuation model in weak inversion can be written as

Eqn. 9 illustrates a l /Zd (or l / Q N ) dependence of S , at low drain current. Hence a steep increase of Svg in weak inver- sion can be attributed to the exponential vanation of Id (or QN) with Vg, whde the subthreshold swing Z d g , remains almost constant [ 191.

gate overdrive voltage, V

Fig.6 density uguinst ihe gute overdrive voltuge at V, = 1.0 and 2.5 V

NMOS SG and DG trmktors’ input-referred guie voltage speciral

--0-- SG VdF = 1.OV --0-- DG V,, = 1.OV -0- SG V i = 2.5V -0- DG Vh = 2 .W L = 0.24p”; W,o, = 6 6 . 6 4 ~ ; N, = 28; freq. = 5 Hz

Figs. 7 and 8 show the normalised drain current noise km/Zd)* and the l /Zd ratios against the drain current in a log-log plot at V, = 1.0 and 2.5V, respectively. Fig. 7 shows that the normalised current noise for both the SG and DG NMOS transistors at v d s = 1.OV do not follow the (gF,7/zd)2 or the l /Zd variations. Fig. 8 reveals that at V, = 2.5V, the normalised current noise for the DG transistor run parallel to the (&lId)2 plot, reiterating that the carrier number fluctuation dominates. Furthermore it cap be seen in Fig. 8 that there is a strong exponential increase ( - 1 / Z t ) of the normalised drain current noise for the SG transistor in weak inversion. This again suggests that mobility fluctu- ation may be dominant in that region.

Figs. 9-11 show similar plots for the PMOSFETs with identical layout and dimensions. Fig. 9 shows that for V,,

315

drain current, mA Fig.7 (g,,&)2 and I/Id ratios ugumst dram current ut V* = I O v -A- SG -0- DG

NMOS SG and DG trmstors’ normalsed drum current nou-e,

L = 0 2 4 ~ , W r o , = 6 6 6 4 ~ , N / = 2 8 , f ~ q = 5 & , V h = 1OV

14

12

5 $ 10- s

E 7 IO2

-

-

10-13[ , , , , . , , , , , , . . , . , ,110-2 1 10 1 02

drain current, mA Fig.8 NMOS SG and DG trunshtors’ mrinulired druin current noise, (gJId)’ and l/Id ratios u g h t drain ament ut V, = 2.5 V

4- DG -A- SG

L = 0 . 2 4 ~ ; W,or = 6 6 . 6 4 ~ ; NI= 28; fmq. = 5 H z ; Vh = 2.5V

, Q :: :: ..

-gate overdrive voitage, V Fig. 9 denslty ugainrt gate overdriw voltage at vsd = 1.0 and 2.5 V --0-- SG V,= 1.OV -0- SG V, = 2.5V -a-- DG vs‘j= 1.ov -0- DG V = 2 S V L = 024p1, W,, = 6 6 . 6 4 ~ ; Nj= 28; freq. = 5Hzsd

316

PMOS SG and DG trunsistors’ Wtqefiired gate voltage spectral

= l.OV, a stronger quadratic increase of S , than the NMOS transistors is observed. Fig. 10 shows a simicant departure of the normalised current noise from the variation at strong inversion for both the SG and DG tran- sistors. This phenomenon can be attributed to the extra correlated mobility fluctuation model [19]. Fig. 11 shows a strong exponential increase (-l/Il) of the normalised current noise at weak inversion for both the SG and DG transistors suggesting that mobility fluctuation dominates in that region. In general, it has been observed from Figs. 6 1 1 that the normalised drain current or the input- referred gate voltage noise levels of SG NMOSFETs and PMOSFETs are higher than their DG counterparts.

i I O 3

1 0 2 10-13 I . . , , , , .., , , , , .. .., , , , , , , , J 10.2 10.1 1 10

drain current, mA Fig. 10 (gn/rd2 and& rutios ugaht drain current ut V, = 1.0 v -A- SG 4- DG L = 0 . 2 4 ~ ; W,o, = 6 6 . 6 4 ~ ; Nf = 28; V, = 1 .OV; freq. = 5 Hz

PMOS SG and DG trmistors’ normalised drub current noire,

109 ~ o.

10-10 : r k I

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p 10’2,

2 - - b

i 10-13

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i , , , , . , ( , ( , , , , , , , . , , . , , , , , j 10-2 1014 10.1 1 10 IO2

drain current, mA Fig. 11 (gJId)’ ami ]/Id mtws against druin m t at v,, = 2.5 v 4- DG L = 0 . 2 4 ~ ; W,,, = 6 6 . 6 4 ~ ; Nf = 28; Vsd = 2.5V; freq. = 5 H z

PMOS SG and DG trunsistors’ normalised cliain current noise,

-A- SG

5 Conclusions

We have demonstrated that the dual gate oxide process, which provides both thin and thck gate oxide transistors in a single process technology, produces thm gate oxide tran- sistors with better flicker noise performance than their counterparts from the single gate oxide process. The results

IEE Proc -Cucurts Devlces Svst , Vol 148, No 6. December 2001

show a maximum reduction of approximately an order of magnitude in the current noise spectra. This is mostly likely due to the lowering of the nitrogen concentration peak at the Si/Si02 interface causing llf noise improvement. The dual gate oxide process will therefore be state-of-the-art for the implementation of SoC designs.

We have reviewed the classical flicker noise theories and subsequently tried to apply them to our experimental fmd- ings. Our results show that the number fluctuation with correlated mobility fluctuation model seems to be the most appropriate to describe the low-frequency noise of our MOS devices.

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