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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1

Increase in Read Noise Margin of Single-Bit-Line SRAM UsingAdiabatic Change of Word Line Voltage

Shunji Nakata, Hiroki Hanazono, Hiroshi Makino, HirokiMorimura, Masayuki Miyama, and Yoshio Matsuda

Abstract— A single-bit-line (BL) static RAM (SRAM) circuit thatemploys adiabatic charging of a word line during a read operation wasfound to provide a large dynamic noise margin (DNM) for reading.Single-BL reading is achieved by using a left access transistor and ashared reading port. The shared reading port greatly reduces the BLcapacitance, enabling the voltage of the BL connected to the low-voltagenode of the flip-flop to change from the precharge voltage to GND. Ananalysis of the time-wise change in DNM revealed that the read noisemargin of this circuit was 1.9 times larger than that of a conventionaltwo-BL circuit. This circuit enables the design of an SRAM that is smallerthan a conventional one, resulting in lower energy consumption.

Index Terms— Adiabatic, low power, read noise margin (RNM).

I. INTRODUCTION

Wireless sensor network technologies are attracting attention inemerging applications, such as industrial monitoring and securitysurveillance. The power available to a wireless senor network islimited because it comes from a battery or supercapacitor. Thus,network nodes must have the capabilities of low-power sensing,processing, and communication [1], [2].

Since a static RAM (SRAM) is a key circuit in a sensor node,it is important to reduce its power consumption. A graph of powerconsumption versus frequency (Fig. 1) reveals two frequency regions:from 300 MHz to 1 GHz is the high-speed range used for commu-nication in high-speed routers; and 80 MHz and below is the low-speed range used for home and industrial appliances, wireless sensornetworks, and other low-power applications. Our target (see Fig. 1)is even smaller power consumption.

One way to reduce the power of an SRAM is to reduce the supplyvoltage (VDD) [3]. The way investigated in this brief is to reducethe device size to the nanometer region [4]–[6]. Reducing the devicesize by one-half cuts the gate capacitance by one-fourth, which shouldresult in a large reduction in power consumption. However, if we tryto use a nanoscale SRAM in a system, we find that the static noisemargin (SNM) is too small due to the large variation in thresholdvoltage (VT). So, we have to develop a new SRAM circuit.

Our previous study of SNM showed that an SRAM with a single-bit line (BL) had a larger SNM than one with two BLs, and that theBL precharge voltage should be lower than VDD [6].

In this paper, we attempted to adiabatically charge a word line(WL) in a single-BL SRAM to stabilize the flip-flop (FF). Adiabaticcharging has been widely investigated [7]–[19] and is already beingused to charge the cells of plasma display panels [7]. We found thatit significantly increased the dynamic noise margin (DNM) for a readoperation. This brief is organized as follows. Section II explains asingle-BL read operation, the adiabatic charging of a WL, and thetime-dependent analysis of the DNM. Section III describes the circuit

Manuscript received March 19, 2012; revised January 30, 2013; acceptedFebruary 5, 2013.

S. Nakata and H. Morimura are with the NTT Microsystem IntegrationLaboratory, Atsugi 243-0198, Japan (e-mail: nakata.shunji@lab.ntt.co.jp).

H. Hanazono, M. Miyama, and Y. Matsuda are with the Graduate School ofNatural Science, Kanazawa University, Kanazawa 920-1192, Japan (e-mail:matsuda@ee.t.kanazawa-u.ac.jp).

H. Makino is with the Faculty of Information Science and Technol-ogy, Osaka Institute of Technology, Hirakata 573-0196, Japan (e-mail:makino@is.oit.ac.jp).

Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TVLSI.2013.2247642

High-speed SRAM

Powerconsumption

100010010Frequency (MHz)

Low-power SRAM

Target

Fig. 1. SRAM target in this brief.

WLWL WL VDDVDD

V1V2

BL

V1V2

BL /BLGND GNDGND

(a)GND

(b)

Fig. 2. Two types of SRAM circuits. (a) Two BLs are used. (b) Single BLis used, for reading.

gege

VDD WL

BL

WLBL

VDD

time0

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Fig. 3. Low voltage of FF for (a) abrupt and (b) gradual charging.

t0

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DNMBL in the proposed SRAM

WL

(a)

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V1V2

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/BLGND

Fig. 4. Analysis of DNM. (a) Circuit for analysis, and time-wise changesin (b) BL and (c) DNM.

structure. Section IV concerns the DNM. Finally, Section V discussesthe operation of an SRAM and device scaling.

II. CONCEPT OF PROPOSED SRAM

A conventional SRAM [Fig. 2(a)] uses two precharged BLs forreading. The problem is that the low-voltage node of an FF increasesfrom 0 V. In contrast, a single-BL SRAM [Fig. 2(b)] uses only oneBL for reading. When V1 = 1 and V2 = 0, V2 is not connected to theprecharged BL; so it remains at a low level. Therefore, a single-BLSRAM has a larger SNM than one with two BLs [6].

To examine the effect of adiabatically charging, we assumethat the capacitance of a BL is small and that the voltage of aBL decreases from the precharge voltage to 0 because the initialconditions are V1 = 0 and V2 = 1. In a conventional SRAM,WL charges abruptly, resulting in a large change in V1 [Fig. 3(a)]because a large current flows from the BL to the V1 node. Thisdestabilizes the FF. In contrast, if the WL charges adiabatically, V1remains close to the GND level [Fig. 3(b)]. Thus, the FF is stable.

To calculate the DNM, we analyzed the time-wise change in thestate of an FF [Fig. 4(a)]. We assumed that the voltage of the WLgradually changed from GND to VDD; and that the voltage of theBL connected to the low-voltage node of the FF gradually changedfrom the precharge voltage to GND [Fig. 4(b)]. Then, we calculatedthe DNM from the initial to the final state. We calculated input–output curves for the two inverters in the FF: for one inverter, theinput voltage is V1 and the output voltage is V2; and for the other,the values are reversed. The DNM is defined to be the length of theside of the largest square enclosed by the curves. From the DNM [asillustrated in Fig. 4(c)], we can determine the stability of the FF. Inthis brief, we investigated how the DNM changed over time.

1063-8210/$31.00 © 2013 IEEE

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2 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

MCGL

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Fig. 5. (a) SRAM that uses single BL for read operation. (b) WL driverwhen a charge recycling clock is used. (c) Layout of (a).

0

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P1

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P4

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Fig. 6. RNM versus BL voltage.

III. CIRCUIT STRUCTURE

We assume that 16 cells are connected to the BL [Fig. 5(a)]. TheBL is connected to the global bit line (GBL) via the write and readports [6]. They are activated by the write port switch signal (WPSW)and the read port switch signal (/RPSW). Only the read word line(RWL) goes high during reading, while both the RWL and the writeword line (WWL) go high during writing.

For reading, the /RPSW is set low. When V1 is low, the GBLincreases from the precharge voltage to the read-port supply volt-age, VRP; and when V1 is high, the GBL does not change. In aconventional SRAM, BL and /BL show a small voltage difference.In contrast, the proposed SRAM uses the read port to reduce theBL capacitance; that is, connecting only 16 memory cells to theBL dramatically reduces the BL capacitance. So, the BL is totallydischarged to GND. This read port provides a large DNM, asexplained in Section IV.

The SRAM circuit [Fig. 5(a)] employs high-resistivity WL driversfor cell stabilization. They produce a gradual, or adiabatic, chargingsignal. The meaning of the word “adiabatic” needs some explanation.“Adiabatic” is used in thermodynamics and mechanics. In thermody-namics, an adiabatic process is one that produces no heat flow; i.e.,there is no Joule heating. For a transistor, that means that it is notturned on when there is a voltage potential. In mechanics, on theother hand, an adiabatic change is a slow deformation of a state inwhich a certain parameter changes very slowly. In our circuit, thatparameter is the WL voltage. So, in the term “adiabatic charging” forthe circuit in Fig. 5(a), “adiabatic” has the sense used in mechanics.

If a charge recycling clock is used as the WL signal, the circuitis designed as in Fig. 5(b). A stepwise waveform from a tankcapacitor is suitable because of its stability. This charging operationis adiabatic in both the thermodynamic and mechanical senses. Thetank capacitor circuit does not have to be on the same chip as theSRAM; the stepwise signal just has to be input into the SRAM chip.The tank capacitor circuit is closer to a digital than an analog circuitbecause it only outputs the voltage of the tank capacitor. The digitalcharacteristics make the circuit very stable. This circuit structure isuseful when a WL has a large capacitance.

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Fig. 7. DNM when WL is charged abruptly. 32 cells are connected.

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BL=1.0 V

Fig. 8. DNM when WL is charged abruptly. 16 cells are connected.

In this paper, the circuit in Fig. 5(a) was used to simplify the timedependence of the DNM. For writing, the memory cell ground line(MCGL) of the circuit is increased from GND to VDD/2 to providea large enough write noise margin (WNM) [17]. Doing this with thestepwise charge recycling clock enables adiabatic operation. A 64-kbSRAM [Fig. 5(c)] designed for 0.18-μm process technology has acore size of 1741 × 827 μm.

IV. SIMULATION RESULTS ON RNM

SPICE simulations of the SNMs of two-BL and single-BL SRAMswere carried out under the following assumptions: a 45-nm designrule suitable for a nanoscale SRAM, a VDD of 1 V, a gate length of50 nm and a gate width of 60 nm for the transistors in a memory cell,and VT’s of 0.43 for nMOS and −0.33 V for pMOS. The simulationswere performed with pre-layout parameters. In the simulation results(Fig. 6), the gray line shows the SNM of the two-BL SRAM whenthe BL voltage is decreased and the /BL voltage is kept at 1 V.

For a single-BL SRAM, when V1 is high, the SNM is the largestat a BL of 1 V (“a” in Fig. 6). When V1 is low, the SNM is thesmallest (0.145 V) at a BL of 1 V (point P1). When the BL voltagedecreases to 0 V, curve “a” moves to “b”, and “c” moves to “d”. TheSNM of the single-BL SRAM takes the minimum value when V1 ishigh or low, as indicated by “c” + “b” (orange line). At a BL voltageof 0.6 V, the SNM of the single-BL can increase to 0.16 V (pointP2), which is larger than 0.145 V (P1). The discussion below showsthat adiabatic WL charging moves P1 to P3, and P2 to P4, therebyproviding a much larger RNM.

First, we consider the change in the DNM of a single-BL over timewhen WL is abruptly charged, assuming that 32 cells are connectedto the BL. Fig. 7 shows the WL (red) and BL (blue) voltages, andDNM (black) for initial BL voltages of 1.0, 0.75, and 0.6 V. At t = 0,the WL voltage is low; so the DNM is constant during holding. Att = 0.5 ns, the WL voltage abruptly jumps to 1 V and the DNMbecomes small. At this time, the DNMs are 0.145 V and 0.16 Vfor BL voltages of 1 V and 0.6 V, respectively. These values areconsistent with P1 and P2 in Fig. 6. After t = 0.5 ns, the BL voltagebegins to decrease because current flows from the BL to the low-voltage node of the FF, V1. As a result, the FF becomes more stableand the DNM increases. At t = 4.5 ns, the DNM reaches 0.38 V.

If we reduce the number of cells connected to the BL from 32to 16, the BL capacitance will be halved. This should lead to arapid decrease in the BL voltage and a rapid increase in the DNM.And the simulation results (Fig. 8) show that the DNM increasestwice as fast as in the previous case.

Next, we consider the DNM of an SRAM with an adiabaticallycharged WL. Figs. 9 and 10 show the DNMs for 32 and 16 cellsconnected to the BL, respectively. The initial BL voltages are 1.0,

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NAKATA et al.: INCREASE IN RNM OF SINGLE-BL SRAM 3

0 1 2 3 4 50

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Fig. 9. (a) DNM when WL is charged gradually, assuming that 32 cells areconnected to the BL and (b) magnification of DNM in (a).

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(b)

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Time (ns)

Vol

tage

(V

) DNM

(b)

Fig. 10. (a) DNM when WL is charged gradually, assuming that 16 cellsare connected to the BL and (b) magnification of DNM in (a).

0.75, and 0.6 V. In Fig. 9, the DNM is 0.35 V at t = 0, and itdrops when the WL voltage becomes larger than VT. The minimumDNMs are 0.24, 0.22, and 0.20 V for BL voltages of 0.6, 0.75, and1.0 V, respectively. In Fig. 10, the WL voltage gradually increases inthe same way as in Fig. 9; but the BL voltages decrease faster thanin Fig. 9 due to the smaller BL capacitance. This rapid decrease iseffective in keeping the DNM large. In fact, the DNMs are larger thanthose in Fig. 9. When the initial BL voltage is 0.6 V, the minimumvalue of the DNM is 0.27 V at t = 1.6 ns. This value is plottedas P4 in Fig. 6, and it is 1.7 times larger than the 0.16 V at P2.Furthermore, it is 1.9 times larger than the SNM of a conventionalSRAM, which is 0.145 V.

Now, let us consider operating speed. The access time of a 45-nm512-kb SRAM is 4 ns at a VDD of 1 V and the parameters in [20,Fig. 23]. If VT is changed, the access time will also change. Here,we take 4 ns as an example from that previous study. In our circuit,the rise and fall times are 3.5 ns; and a previous study showed thesensing time to be 2 ns [6, Fig. 8]. Therefore, one cycle is estimatedto be 4 + 3.5 + 2 + 3.5 = 13 ns, which yields an operating speed of80 MHz.

The inverter input–output curves in a single-BL SRAM weresimulated for the abrupt (Fig. 11) and gradual (Fig. 12) charging.

In Fig. 11(a), the DNM is characteristic of the hold state, and thevalue is 0.352 V. In Fig. 11(b), the DNM has the minimum value of0.166 V. This is because the WL turns on and node V1 is connectedto the BL. The stable point in Fig. 11(a) (blue circle; V1 = 0 V, V2 =1 V) moves to a different point in Fig. 11(b) (red circle; V1 = 0.2 V,V2 = 1 V). So, the DNM in Fig. 11(b) is small. In Fig. 11(c), V1

Fig. 11. Inverter input–output curves for the abrupt charging of the WL inFig. 8. The BL voltage is 0.6 V.

Fig. 12. Inverter input–output curves for gradual charging of the WL in Fig.10. The BL voltage is 0.6 V.

is smaller, and the DNM is larger, than in Fig. 11(b). After that, V1decreases further, and the DNM increases to 0.384 V in Fig. 11(f).

Similarly, in Fig. 12(a), the DNM is characteristic of the hold state.In Fig. 12(b), the DNM decreases to 0.338 V due to the increase inV1. In Fig. 12(c), the DNM is even smaller and has the minimumvalue of 0.266 V. Gradual WL charging keeps V1 from increasingdrastically. The stable point in Fig. 12(a) (blue circle; V1 = 0 V,V2 = 1 V) moves to a different point in Fig. 12(c) (red circle; V1 =0.1 V, V2 = 1 V), where V1 is only half the value in Fig. 11(b). Thismakes the DNM larger in Fig. 12(c). After that, V1 decreases, andthe DNM increases to 0.378 V in Fig. 12(f).

Figs. 11(d)–(f) and 12(e)–(f) show no cross-coupled curves. Thismeans that the only stable state is V1 = 0 and V2 = 1. We useFig. 12(f) as an example to explain this. At t = 3 ns, the cell statereaches the final state, in which the BL voltage is 0 V and the WL is1 V, as in Fig. 10(a). This is the write condition (V1 = 0, V2 = 1).So, only the state V1 = 0 and V2 = 1 is possible.

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4 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

-0.4

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Fig. 13. Variation in RNM. (a) Illustration of SNM distribution and(b) RNM-5σ versus scaling factor, K. The numbers indicate the design rule.

V. DISCUSSION

Now, let us examine the energy consumption of the WL driver.To produce a gradually changing WL signal, we use high-resistivityCMOS buffers. This requires that the gate width of the transistorsin the WL drivers be smaller than usual. That reduces the energyconsumed by a WL driver. Another factor is the energy dissipationdue to the short-circuit current. In an adiabatic WL driver, the outputsignal changes gradually; but the input signal is fast, which means thatthere is almost no short-circuit current. The energy dissipation due tothe short-circuit current is the same as that in a conventional circuit,even when the WL is charged adiabatically. This can be explainedas follows: from [21, eq. (9)], the dissipated charge, QSC, that flowsfrom the power supply to GND due to the short-circuit current isgiven by QSC = β/(12VDD)(VDD − 2VT)3 · τ , where β is the gainof a transistor and τ is the rise or fall time of the input signal. Theinput signal is fast, as in a conventional circuit, which means thatτ is the usual small value and QSC is not changed. Consequently,the energy consumed by the WL driver due to the charging of thecapacitor and short-circuit current is smaller.

The next item to consider is the RNM. The RNM varies due tothe statistical variation in VT. The standard deviation of SNM, σ ,is given by σ 2 = ∑6

i=1 σ 2i (∂SN M/∂VTi)

2, where SN M is thevalue of the SNM, VTi is the VT of the ith transistor in the cell,and σi is the standard deviation of VTi [22]. Since ∂SN M/∂VTi isalmost linear [23] and since σi is proportional to (LW )−1/2, whereL is the length and W is the width of a transistor, σ is almostproportional to (LW )−1/2. Fig. 13(a) illustrates the SN M distribution.For a correct operation, SN M-5σ must be positive. Fig. 13(b) showsRNM-5σ as a function of the scaling factor, K. K is set to 1 fora design rule of 65 nm, in which case σ is set to 20 mV [5].DN Mmin is the minimum DNM for a BL voltage of 0.6 V. Basedon the previous discussion, SN M is set to 0.14, and DN Mmin to0.28 V. For these values and a design rule of 45 nm, SN M-5σis 0 for a conventional SRAM. So, it is impossible to design aconventional SRAM with a design rule of < 45 nm. However, for theproposed SRAM, DN Mmin-5σ [red line in Fig. 13(b)] is larger thanSN M-5σ , which allows a design rule as small as 23 nm. Thismeans that a low-energy SRAM is possible. With a high-k gate or aFinFET [24], σi and also σ are smaller; so an even smaller SRAMshould be possible. Here, we also assumed that ∂ DN Mmin/∂VTi isalmost linear due to the fact that the graph in Fig. 12(c) for theminimum DNM is almost the same as the butterfly plot for the SNMof a conventional SRAM. However, the analysis is not completelyaccurate. Monte Carlo simulations would give more accurate results;and we plan to use them in the future.

The use of a stepwise WL signal [8] should further reduce thepower consumption. In addition, a gradually increasing WL voltagemakes DNM larger. The total energy, Etot, for the N-step chargingof capacitor CL is Etot = (1/N + 2N2mρ/Tt)CLV 2

DD, where mis the factor for completing each step of charging, ρ is the averagetransistor delay, and Tt is the total charging time [8]. The first term isthe energy for charging CL , and the second is the switching energy.

InvB

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Fig. 14. Two circuit states in a cell. (a) WL = VDD and (b) WL = VDD /2.

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WNM

0 VDD

VDD

InvA

InvB

V1

V2

WNM

0 VDD

VDD

(b)

Fig. 15. Input–output characteristics of inverters. (a) Noncross-coupledcurves for Fig. 14(a). (b) Cross-coupled curves for Fig. 14(b).

Fig. 16. WNM versus time for abrupt WL charging.

When the ratio of these two terms is 5:1, we have Tt > 10N3mρ.In advanced design technology, ρ is 0.6 ps [25]. When N = 6 andm = 2, Tt is calculated to be 2.6 ns, which is consistent with Figs. 9and 10. Thus, a stepwise signal should provide both a large DNMand a small energy dissipation.

Regarding a write operation, we use a WWL driver with the samehigh resistivity as the RWL. So, there are no mismatches between theWWL and the RWL. This solves the problem of asymmetry betweenBL and /BL during a write operation. A write operation is performedwhen the WWL and RWL are 1. Now, let us consider the WNM.The WNM can be determined from the input–output characteristicsof the circuit in Fig. 14. In Fig. 14(a), inverter A, InvA, and inverterB, InvB, operate when W L = VDD, B L = 0 V, and /B L = V DD. InFig. 14(b), InvA and InvB operate when W L = V DD/2, B L = 0 V,and /B L = V DD. In Fig. 15(a), which shows the input–outputcharacteristics for Fig. 14(a), the WNM is defined to be the lengthof the side of the smallest square enclosed by the two curves, whichis the conventional positive WNM. In Fig. 15(b), which shows thecharacteristics for Fig. 14(b), the curves are cross-coupled, whichmeans that the data might not be written correctly. In this case,WNM is negative and is defined to be the length of the side of thelargest square enclosed by the curves between the two intersections.Simulations of WNM for abrupt WL charging (Fig. 16) show that, att = 0, WNM is negative (−0.35 V). This means that there are twostable states; so a write operation might not be performed correctly.When WL reaches 1 V, WNM becomes positive; so there is only onestable state and a write operation is performed correctly. Simulationsof WNM for adiabatic charging (Fig. 17) show that the initial andfinal WNM are the same as those for abrupt charging. What isdifferent is the write time: it is about 2 ns for adiabatic chargingbut <0.1 ns for abrupt charging. Thus, adiabatic operation does notchange the WNM, but it does make the write time longer.

Next, we compared the RNM, speed, and energy consumption ofthe proposed circuit with those of a conventional SRAM (Table I).For a conventional 45-nm SRAM at VDD = 1 V [26, Table II],the operating speed should roughly be in the range 300–850 MHz.However, RNM-5σ is 0, as explained above. This means that anSRAM does not operate correctly when the design rule is < 45 nm.

This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

NAKATA et al.: INCREASE IN RNM OF SINGLE-BL SRAM 5

Fig. 17. WNM versus time for adiabatic WL charging.

TABLE ICONVENTIONAL SRAM AND ADIABATIC-WL SRAM

Circuit Type Conventional SRAM Adiabatic WL-SRAM

Operating cond. 45 nm, 1 V 45 nm, 0.7 V 45 nm, 1 V 23 nm, 1 V

RNM-5σ 0 Negative 140 mV 0Speed 300–850 MHz Not work 80 MHz 80 MHz

Energy/cycle (relative) 1 Not work α α/4

It also means that a 45-nm SRAM does not operate correctly atVDD = 0.7 V. On the other hand, an adiabatic 45-nm SRAM hasa large RNM of 140 mV, although the operating speed is low as80 MHz. The energy/cycle, which includes the energy dissipation ofthe WL drivers and memory cells, is α, which is smaller than thevalue for a conventional SRAM (α < 1). This is because the energydissipation of the WL driver in an adiabatic circuit is smaller, asexplained above. α is much smaller when stepwise charging is used.

Since, for an adiabatic 23-nm SRAM, RNM-5σ is 0, we canfabricate one. Its operating energy is α/4 due to the smaller gatecapacitance. So, in low-speed applications, an adiabatic circuit isvery effective in reducing energy consumption. Regarding leakagepower, it is not significant in an SRAM designed for low-powerapplications due to the use of a high VT. In fact, if the circuitin [26] operates at 80 MHz, the power consumption is estimated to be4.3 pJ × 80 MHz = 344 μW, while the leakage power is 25.2 μW,which is just 7.3% of that. These values are for a word length of32 bits. If it is four times larger (128 bits), the leakage power willbe 1.8% of the operating power consumption, which is negligible.

VI. CONCLUSION

We designed a new SRAM with a small-capacitance BL thatemploys a shared read port and adiabatic WL charging for reading.Using the proposed circuit, an SRAM that consumes much lessenergy than a conventional one is possible.

REFERENCES

[1] D. Ho, K. Iniewski, S. Kasnavi, A. Ivanov, and S. Natarajan, “Ultra-lowpower 90 nm 6T SRAM cell for wireless sensor network application,”in Proc. IEEE Int. Symp. Circuits Syst., May 2006, pp. 4131–4134.

[2] S. R. Singh and K. Moez, “Ultra-low leakage 90 nm content addressablememory design for wireless sensor network applications,” in Proc. IEEEInt. Midwest Symp. Circuits Syst., Aug. 2009, pp. 1191–1194.

[3] F. Frustaci, P. Corsonello, S. Perri, and G. Cocorullo,“Techniques for leakage energy reduction in deep submi-crometer cache memories,” IEEE Trans. Very Large ScaleIntegr. (VLSI) Syst., vol. 14, no. 11, pp. 1238–1249,Nov. 2006.

[4] L. Chang, D. M. Fried, J. Hergenrother, J. W. Sleight, R. H. Dennard,R. K. Montoye, L. Sekaric, S. J. McNab, A. W. Topol, C. D. Adams,K. W. Guarini, and W. Haensch, “Stable SRAM cell design for the32 nm node and beyond,” in Proc. Symp. VLSI Technol., Jun. 2005,pp. 128–129.

[5] S. Ohbayashi, M. Yabuuchi, K. Nii, Y. Tsukamoto, S. Imaoka, Y. Oda,M. Igarashi, M. Takeuchi, H. Kawashima, H. Makino, Y. Yamaguchi, K.Tsukamoto, M. Inuishi, K. Ishibashi, and H. Shinohara, “A 65-nm SoCembedded 6T-SRAM design for manufacturing with read and write cellstabilizing circuits,” in Proc. Symp. VLSI Circuits, 2006, pp. 17–18.

[6] S. Nakata, H. Suzuki, H. Makino, S. Mutoh, M. Miyama, and Y. Mat-suda, “Increasing static noise margin of single-bit-line SRAM by lower-ing bit-line voltage during reading,” in Proc. IEEE Int. Midwest Symp.Circuits Syst., Aug. 2011, pp. 1–4.

[7] L. F. Weber and R. C. Younce, “Independent sustain and addresstechnique for the AC plasma display panel,” in Proc. SID Int. Symp.Dig., vol. 17. May 1986, pp. 220–223.

[8] L. J. Svensson and J. G. Koller, “Driving a capacitive load withoutdissipating fCV2,” in Proc. IEEE Symp. Low Power Electron., Oct. 1994,pp. 100–101.

[9] W. C. Athas, L. J. Svensson, J. G. Koller, N. Tzartzanis, and E. Chou,“Low-power digital systems based on adiabatic-switching principles,”IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 2, no. 4, pp.398–407, Dec. 1994.

[10] K. Roy and S. C. Prasad, Low-Power CMOS VLSI Circuit Design. NewYork, USA: Wiley, 2000.

[11] S. Kim and M. C. Papaefthymiou, “True single-phase adiabatic cir-cuitry,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 9, no. 1,pp. 52–63, Feb. 2001.

[12] A. Blotti and R. Saletti, “Ultralow-power adiabatic circuit semi-customdesign,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12,no. 11, pp. 1248–1253, Nov. 2004.

[13] S. Nakata, “Adiabatic charging reversible logic using a switched capac-itor regenerator,” Inst. Electron. Inf. Commun. Eng. Trans. Electron.,vol. E87-C, no. 11, pp. 1837–1846, Nov. 2004.

[14] M. E. Hwang, A. Raychowdhury, and K. Roy “Energy-recovery tech-niques to reduce on-chip power density in molecular nanotechnologies,”IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 8, pp. 1580–1589,Aug. 2005.

[15] K. Kim, H. Mahmoodi, and K. Roy, “A low-power SRAM using bit-line charge-recycling,” IEEE J. Solid-State Circuits, vol. 43, no. 2, pp.446–459, Feb. 2008.

[16] H. Mahmoodi, V. Tirumalashetty, M. Cooke, and K. Roy, “Ultra-low-power clocking scheme using energy recovery and clock gating,” IEEETrans. Very Large Scale Integr. (VLSI) Syst., vol. 17, no. 1, pp. 33–44,Jan. 2009.

[17] S. Nakata, H. Suzuki, R. Honda, T. Kusumoto, S. Mutoh, H. Makino,M. Miyama, and Y. Matsuda, “Adiabatic SRAM with a shared accessport using a controlled ground line and step-voltage circuit,” in Proc.IEEE Int. Symp. Circuits Syst., Jun. 2010, pp. 2474–2477.

[18] J. C. Kao, W. H. Ma, V. S. Sathe, and M. Papaefthymiou, “Energy-efficient low-latency 600 MHz FIR with high-overdrive charge-recoverylogic,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 20, no. 6,pp. 977–988, Jun. 2012.

[19] S. E. Esmaeili, A. J. Al-Kahlili, and G. E. R. Cowan, “Low-swing differ-ential conditional capturing flip-flop for LC resonant clock distributionnetworks,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 20,no. 8, pp. 1547–1551, Aug. 2012.

[20] K. Nii, M. Yabuuchi, Y. Tsukamoto, S. Ohbayashi, S. Imaoka,H. Makino, Y. Yamagami, S. Ishikura, T. Terano, T. Oashi,K. Hashimoto, A. Sebe, S. Okazaki, K. Satomi, H. Akamatsu, andH. Shinohara, “A 45-nm bulk CMOS embedded SRAM with improvedimmunity against process and temperature variations,” IEEE J. Solid-State Circuits, vol. 43, no. 1, pp. 180–191, Jan. 2008.

[21] H. J. M. Veendrick, “Short-circuit dissipation of static CMOS circuitryand its impact on the design of buffer circuits,” IEEE J. Solid-StateCircuits, vol. 19, no. 4, pp. 468–473, Aug. 1984.

[22] V. Gupta and M. Anis, “Statistical design of the 6T SRAM bit cell,”IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 1, pp. 93–104,Jan. 2010.

[23] K. Takeuchi, R. Koh, and T. Mogami, “A study of the threshold voltagevariation for ultra-small bulk and SOI CMOS,” IEEE Trans. Electron.Dev., vol. 48, no. 9, pp. 1995–2001, Sep. 2001.

[24] Z. Guo, S. Balasubramanian, R. Zlatanovici, T. J. King, and B. Nikolic,“FinFET-based SRAM design,” in Proc. IEEE Int. Symp. Low PowerElectron. Design, Aug. 2005, pp. 2–7.

[25] Y. Li, C. H. Hwang, and T. Y. Li, “Random-dopant-induced variabilityin nano-CMOS devices and digital circuits,” IEEE Trans. Electron. Dev.,vol. 56, no. 8, pp. 1588–1597, Aug. 2009.

[26] B. Rooseleer, S. Cosemans, and W. Dehaene, “A 65 nm, 850MHz, 256 kbit, 4.3 pJ/access, ultra low leakage power mem-ory using dynamic cell stability and a dual swing data link,”IEEE J. Solid-State Circuits, vol. 47, no. 7, pp. 1784–1796,Jul. 2012.