integrated circuits - :::: 국립한밭대학교 반도체설계실...
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q 논리게이트를 집적화하여 하나의 칩에 구현
u SSI(Small Scale IC)
10개 이내의 게이트 / 칩 (기본게이트)
u MSI(Medium Scale IC)
수십개의 게이트 / 칩 (디코더, 카운터)
u LSI(Large Scale IC)
수백개의 게이트 / 칩 (ALU)
u VLSI(Very Large Scale IC)
수천-수만개의 게이트 / 칩 (CPU, Memory)
u ULSI(Ultra Large Scale IC)
수십-수백만개 이상의 게이트 / 칩(고성능프로세서)
u GSI(Giant Large Scale IC)
Integrated Circuits
Commonly used 7400-Series SSI ICs
1 2 3 4 5 6 7
14 13 12 11 10 9 8
Vcc
GND
7400
1 2 3 4 5 6 7
14 13 12 11 10 9 8
Vcc
GND
7408
1 2 3 4 5 6 7
14 13 12 11 10 9 8
Vcc
GND
7432
1 2 3 4 5 6 7
14 13 12 11 10 9 8
Vcc
GND
7402
1 2 3 4 5 6 7
14 13 12 11 10 9 8
Vcc
GND
7404
1 2 3 4 5 6 7
14 13 12 11 10 9 8
Vcc
GND
7410
1 2 3 4 5 6 7
14 13 12 11 10 9 8
Vcc
GND
7486
1 2 3 4 5 6 7
14 13 12 11 10 9 8
Vcc
GND
7420
1 2 3 4 5 6 7
14 13 12 11 10 9 8
Vcc
GND
7427
q Positive logic AND = Negative logic OR q Positive logic OR = Negative logic AND
Logic SignalValue Value
1 H
0 L
q Positive logic q Negative logic
Logic SignalValue Value
0 H
1 L
Positive logic Positive logic Negative logic Negative logic AND OR AND OR X Y F
0 0 0
0 1 0
1 0 0
1 1 1
X Y F
0 0 0
0 1 1
1 0 1
1 1 1
X Y F
0 0 0
0 1 1
1 0 1
1 1 1
X Y F
0 0 0
0 1 0
1 0 0
1 1 1
Positive Logic and Negative Logic
Characteristics of IC Logic Familyq Fanout
u 정상동작에 영향을 주지않고, 게이트의출력에 걸어 줄수 있는 부하의갯수
q Power dissipation
u 게이트를 동작시키기 위해 필요한 전력
q Propagation delay
u 입력측의 신호가 출력측에 전달되기 까지걸리는 시간
q Noise margin
u 입력신호에 포함될 수 있는 잡음의최대 허용치
q Degree of integration
q Component cost
IC Digital Logic Familyq RTL (Resistor Traansistor Logic)
q DTL (Diode Transistor Logic)
q TTL (Transistor Transistor Logic) : 보편적으로 널리 쓰임
q ECL (Emitter Coupled Logic) :고속 동작에 적합
q MOS (Metal Oxide Semiconductor) : 고집적도
q CMOS (Complementary Metal Oxide Semiconductor) : 고집적도, 저전력
q I2L (Integrated Injection Logic) : 고집적도
q BiCMOS
Bipolar Transistor
IB Vo
RB
Vi
IC
IE
VCC
RC
VBE[V]
IB[mA]
0.6 0.7 0.8
IC[mA]
VCE[V]
VCC
RC
VCC
0.6mA
0.5
0.4
0.3
0.2
Region VBE [V] VCE [V] Current Relationship
Cutoff < 0.6 Open circuit IB=IC=0
Active 0.6 - 0.7 > 0.8 IC=hFEIB
Saturation 0.7 - 0.8 0.2 IB >> ICS/hFE
IB =
RTL(Resistor Transistor Logic)
A
VCC=3.6V
640Ω
B C
Y= A+B+C
450Ω 450Ω 450Ω
u L:0.2V, H:1.0-3.6V
u Power dissipation:12mW
u Propagation delay: 25ns
u Noise Margin: 0.4V
u Fanout= 5
VCC=3.6V
640Ω
Y= ABC
A
B
C
DTL(Diode Transistor Logic)
VCC=5V
2KΩ
Q1
5KΩ
D1 D2P
5KΩ
Y= ABC
A
B
C
u L:0.2V, H:4-5V
u Power dissipation:12mW
u Propagation delay: 30ns
u Noise margin: 1V
u Fanout: 8
u A,B,C중 하나가 L 이면
→ P=0.2+0.7= 0.9V
Q1이 ON되려면 P는 최소한
P= 0.7+0.7+0.7= 2.1V
∴ Q1 is OFF → Y=5V
u A,B,C모두 H 이면
Q1 is ON → Y= 0.2V
TTL(Transistor Transistor Logic)
u TTL output
1) Open-collector output
2) Totem-pole output
3) Tristate output
TTL series name Prefix FanoutPower
dissipation[mW]
Propagationdelay[ns]
Speed-Powerproduct
[pJ]
Standard 74 10 10 9 90
Low-power 74L 20 1 33 33
High speed 74H 10 22 6 132
Schottky 74S 10 19 3 57
Low-power Schottky 74LS 20 2 9.5 19
Advanced Shottky 74AS 40 10 1.5 15
Advanced low-powerSchottky
74ALS 20 1 4 4
Open Collector TTL
AB
CD
Y
VCC
OC
OC
AB
CD
OC
OC
Y
VCC
YI1
I2
I3
I4
Bus lineOC1
OC2
OC3
OC4
OC51
1
1
01
10
0
0
0
3-State TTL GateVCC
A Q2Q1
Q5
Q3
Y
Q4
D1
Q8Q7Q6C
A
C
A
C
Y=A if C=highY=high impedance if C=low
Y=A’ if C=lowY=high impedance if C=high
ECL(Emitter Coupled Logic)
VCC2=GND
Q7
RC1220Ω
Rp50KΩ
Q6
Q8
Q5Q4Q3Q1 Q2
A B C D
Rp50KΩ
Rp50KΩ
Rp50KΩ
RE779Ω 6.1KΩ
RC2
245Ω907Ω
VCC1=GND
VBB= -1.3V
4.98KΩ
VEE= -5.2V
ORoutput
NORoutput
ECL gates
A
B
(A+B)’ : NOR
(A+B) : OR
A
B
A
B
(A+B)’+(C+D)’=[(A+B)(C+D)]’
(A+B)(C+D)
