introduction to lcd driver ic driving circuits of tft- lcd ... · introduction to lcd driver ic •...

98(上) 1

Flat Panel Display Principle and Flat Panel Display Principle and Driving Circuit DesignDriving Circuit Design

Chapter 4Chapter 4Driving Circuit Design of A-Si TFT

中興大學電機系中興大學電機系汪芳興汪芳興

Page 2 19598(上) NCHU EE 汪芳興 fansendragonnchuedutw

Ch4 Driving Circuits Design of A-Si TFTndash Gate Driving Circuit

ndash Source Driving Circuit

ndash LCD-TV Driving Technology

ndash Small-Size TFT-LCD Driver IC

ndash Trends of Digital Interface

Outline


Introduction to LCD Driver ICbull Improved Visualization

ndash A Fundamental Market Enabler


Driving Circuits of TFT- LCD Module

Con

nect

orC

onne

ctor

DCDC Converter

DCDC Converter

LVDS Receiver

LVDS Receiver

Timing Controller

Timing Controller

Gamma Correction

TFT-LCD1280(3)1024

Pixels

TFT-LCD1280(3)1024

Pixels

X-Driver IC

Y-D

river

IC

G1

G1024

D1 D3840

InverterDC POWER

4 CCFL

IF + X PCB

Y PCB

ASIC

LVDS

+5V



bull Example


Gate Driver IC

bull Also called scan driver or row driverbull Function

ndash Read in start signalndash Progressively turn on pixel TFTs on each gate linendash Turn off TFT during pixel holding period

bull Design considerationndash RC delay of bus line (for large-size panel)

bull Capacitive coupling driving (CC driving)bull Gate-driver in panel


Gate Driver Architecture

Bi-directional Shift Register

Level Shifter

Output Buffer

CLKSP1

buffer

levelshift

SR

buffer

levelshift

SR

buffer

levelshift

SR

buffer

levelshift

SR

buffer

levelshift

SR

Out1 Out2 Out3 Outn

SP2

Gate driver IC 電路方塊圖

VDDGND

VGGVEE

digital

analog

SR frequency 10k~75kHz Output voltage range gt 12V

To Display Area

RESET

ENB

UpDown

CLKSP1


Timing of Gate Driver

G1

G2

G256

Gate driver 1

CLK

STP

G1

G2

Gate driver 2

Gat

e dr

iver

1G

ate

driv

er 2

256 CLK


Key Specifications

bull Channel number(240256264270300308hellip)

bull Max operation frequency (200KHz 500KHz)bull 2 level or 3 level drivingbull Operation voltage

ndash digital 5V 33Vndash analog VGGgt20V VEElt-10V

bull Package (TCP COG COF)

0 19598(上) NCHU EE 汪芳興 fansendragonnchuedutw

Package of Driver IC






Channel Number vs Resolution

bull Gate driver No of driver and No of output channel

3002401200UXGAUXGA2561024SXGASXGA

256192154128768XGAXGA200150120600SVGASVGA

120480VGAVGA

33445566lines


Power OnOff Sequence

This IC is a high-voltage LCD driver so it may be damaged by a large current flow if an incorrect power sequence is used Connecting the drive powers VEE amp VGG after the logical power VDD is the recommended sequence


Gate Driver Circuits

Shift register Level shifter Buffer

Example


φ

φ

φ

φ

IN OUT

CMOS Shift RegisterStatic SR


Shift Register

bull Latchndash Basic memory

element

ndash Two cross-coupled logic inverter

ndash Bistable circuit

G1

G2

W X

Y Z


Shift Register ndash Latch 1

CLK

CLK

CLK

CLK

SP(L)

ENB1ENB2

S1 S2

N1 N2

US 6157361SHARP



US 6724361 B1


Level Shifter ndash Example 1

Vpp

GND

Vout

N2

P2

Vcc

GND

N1

P1

Vin

Vdd

GND

OUT

T2

T1

IN

Inverter Type

Ref Low Power Digital VLSI Design A Bellaouar M Elmasry

With both transistors of the inverters turned on a current path from the supply voltage to ground is present resulting in undesirable power consumption



Vcc

GND

Vout

N2

P2

Vcc

GND

N1

P1

Vin

N3

P3

Vcc

Vdd

P4

Vdd

VccN4

Vdd

GND

M1

M2

INPUT

M3

Vdd

GND

M4

M5

M6

INPUT

OUTPUT

Latch Type

This circuit overcomes the problem of direct power consumption by using a latch

US 4486670INTERSIL


Output Buffer

IN OUT

Area ratio = e (27) ~ 3


TSMC HV Process

Source Web of TSMCPage 24 19598(上) NCHU EE 汪芳興 fansendragonnchuedutw

Roadmap of High Voltage Technology

bull Roadmap of TSMC HV technology

Source Web of TSMC


Two-Line Scanningbull Frame inversionbull column inversion

bull row inversionbull dot inversion


Vd 1

CLC

Vpixel

CstTFT

Vd 2 Vd 3Vg N-2

Vg N-1

Vg N

VdN-2

VdNVdN-1

VdN+1

(N-2)th (N)thline time

~10us ~10us

1 frame ~16ms

Two-Line Scanning

bullFirst pulse is for precharge


Scan Driver Consideration

Dual Driving

The scan driver with both side driving effectively reduces the RC time constant of the gate line

gt 40ldquo

RefIDW 00rsquo p167


Gate Driver Design

Toshiba 15rdquo UXGA

RefSID 00rsquo p1121

Shut circuitShut circuit was inserted between SR outputs and LS inputs to avoid over current phenomena due to timing difference between right and left side scan driver outputs

Level shifterLevel shifter is divided in two stagestwo stages First stage is made to shift high level from 10 V to 15 V second stage is made to shift low level from 0 V to ndash2 V


Three-level Capacitive Coupling Driving (C C Driving)

bull Cst on gate

CstClc

Cgd

Cds

Scan line n

Scan line n-1

Vcom

3-level

Vghl Vgc

Pixel voltage

V1V2

V3321 VVV Δ+Δ=Δ


Three-level C C Driving

bull Feed-through effect is eliminated

CdsCgdCstClcCgdVghlV

+++times=Δ 1

CdsCgdCstClcCstVgcV

+++times=Δ 2

CdsCgdCstClcCgdVgcV

+++times=Δ 3

If ie 321 VVV Δ+Δ=Δ ( )CgdCstVgcCgdVghl +times=times

CgdCstCgdVghlVgc+

times= then

778205040

05025

4710504040

25050case previousConsider

=+

=+

timesΔ=

=++

times=Δ

gds

gdghlgc

gd

CCC

VV

VV


Three-level C C Drivingbull Cs on Gate with 3-Level Driving Scheme

Data Center

Positive Driving

Negative Driving

Data Line Voltage Level

Black(+)

White(+)

Black(-)

White(-) Temporal Vcom

Positive Driving

Negative Driving

Temporal Pixel Voltage Level

Final Vcom

Positive Driving

Negative Driving

Final Pixel Voltage Level

Black(+)

White(+)

Black(-)

White(-)

Black(+)

White(+)

Black(-)

White(-)


Cs on gate

CstClc

Cgd

Cds

Scan line n

Scan line n-1

Vcom

Negative Polarity

GN-1(+)

VP

V1V2

V3

bullline inversionbulllow voltage source driverbullcomplex scan driver

Positive Polarity

V4

V5

V6

GN(-)

GN-1(-)

GN(+)

VP

Vcom

Vblack(+)

Vblack(-)

Vg Ve+

Ve-Vg

Four-level C C Driving

Not valid for Vcom AC



bull Pixel voltages of positive polarity and negative polarity for LC cell are symmetry

( ) ( )

( )

( )CgdCCstCgdVeV

CgdCCstCstVeV

CgdCCstCgdVeVgV

LC

LC

LC

++timesminus=Δ

++times+=Δ

++timesminus+=Δ

)(3

)(2

)(1 ( ) ( )

( )

( )CgdCCstCgdVeV

CgdCCstCstVeV

CgdCCstCgdVeVgV

LC

LC

LC

++times+=Δ

++timesminus=Δ

++times+minus=Δ

)(6

)(5

)(4

CstCgdVgVeVe

VVVVVV

times=+minusminusthere4

ΔminusΔ+Δminus=ΔminusΔ+Δ

2)()(

654321Q



bull Cs on Gate with 4-Level Driving Scheme

Data Center

Positive Driving

Negative Driving

Black(+)

White(+)White(-)


Black(-)


Data Center

Positive Driving

Negative Driving

Black(+)

White(+)White(-)

Black(-)


Comparison of Addressing

XXX VX V4-level driving

VVX VX V3-level driving

VVVV2-level driving

high voltage

high voltage

Lowhigh voltage

Lowhigh voltage

Output range

DCDCACDCACDCCommon voltage

DotColumnRowFrame

Vcom ACDC


Trend of Gate Driver ICbull package

ndash TCP（Tape Carrier Package）rarr

ndash COG（Chip on Glass） rarr

ndash COF （Chip on Film） rarr

ndash GIP（Gate-Driver In Panel）


Gate-Driver In Panel


bull Gate Driving Circuitbull Source Driving Circuit

ndash Driver Architecturesndash Driver Specificationsndash DAC ndash Output Bufferndash Low power consumption

bull LCD-TV Driving Technologybull Small-Size TFT-LCD Driver ICbull Trends of Digital Interface

Ch4 Driving Circuits Design of A-Si TFT


Source Driver Circuits

bull Also Called Column Driver (Data Driver)

bull Driver Architecturesndash Line-at a-time (LAAT)

ndash Point-at a-time (PAAT)

bull Data Drivers Typesndash Analog Data Driver

ndash Digital Data Driver


Analog Data Driver

bull Serial In Serial Out

Shift Register

pixel

Qi Qi+1Video

in

pixel

Shorter charging time

Shift RegisterQi-1 Qi

Video in

control

pixel

Qi+1 Qi+2

bull Serial In Parallel Out

Samplecapacitor

hold capacitor


Comparison of Analog Data Driver

higherlowestCircuits complexity

NoNoReformed video needed

1(TVL Pix-H)1(TVL Pix-H )SR frequency

TVL Pix-HTVL Pix-HSample time

TVLTVL Pix-HPixel charging time

SIPO1 phase

SISO1 phase

TVL vertical line time Pix-H horizontal pixel number


LAAT Driver Architecture

Pixel1

Pixel2

Pixel3

Pixel4

Pixel5

Pixel6

Pixel7

Pixel8

Pixel Pixel Pixel Pixel Pixel Pixel Pixel PixelArray

All video signals stored in A latches are written to B latches simultaneously in each horizontal scanning period Features (1) has sufficient charging capability (2) very difficult to achieve good uniformity of output voltages of the analog buffer

SR

Video in

SR SR SR SR SR SR SR

Sample Sample Sample Sample Sample Sample Sample Sample

HoldHoldHoldHoldHoldHoldHoldHold

BufferBufferBufferBufferBufferBufferBufferBuffer

CLK DIOFor a-Si TFT-LCDs

Driver IC


Sample

Hold

Buffer

Sample

Hold

Buffer

Sample

Hold

Buffer

Sample

Hold

Buffer

SR SR SR SR

PAAT Driver Architecture

Pixel1

Pixel2

Pixel3

Pixel4

Pixel5

Pixel6

Pixel7

Pixel8


DeMUX 12

A high speed and wide voltage range analog interface circuit that consumes a large amount of power is required Feature (1) less data driver ICs (2) shorter pixel charging time than LAAT

DeMUX 12 DeMUX 12 DeMUX 12

Videoin

CLK DIOFor some large-size LTPS TFT-LCDs

Driver


LAAT vs PAAT

bullbull SanyoSanyo has been selling products using the PAAT technology Since small-size panels have only 234 scan line there is sufficient time to use PAAT technology

bullbull SeikoSeiko--EpsonEpson has adopted the LAAT architecture because there studies indicated that the crosstalk on a multiplexed circuit was too severe


Max Frequency of Shift Registers

RefSIDrsquo96 Digest pp673Vcc=5V Freqlt2MHz μnp=7035 cm2Vs


Digital Data Driver

(a) Decoder type is very difficult to achieve full gray scale because the circuit configuration is too complicated

(b) DAC type is the most promising one because it has a less complicated configuration while keeping full digitalinterface

RefIDW 00rsquo p171(a) (b)


Comparison of DigitalAnalog Data Driver

lowhighcost

ADC neededCompatible to PC

video signal processing

NoYesgamma correction

lowhighnoise immunity

simplecomplexcircuits complexity

AnalogDigital


Architecture of Source Driver IC for Large-Size TFT-LCDs

Latch Signal

Polarity Signal

Analog Part

Digital Part

To LCD data line

CLKDIO1

Out1 Out2 Out3 Outn

DIO2

HoldReg

Sample Reg

SR

Buffer

LevelShifter

HoldReg

Sample Reg

SR

Buffer

LevelShifter

HoldReg

Sample Reg

SR

Buffer

LevelShifter

HoldReg

Sample Reg

SR

Buffer

LevelShifter

HoldReg

SR

Buffer

LevelShifter

sample reg

DigitalAnalog Converter DAC

Dat

are

ceiv

er

GammaReferencevoltages

Datain

Output buffers

Level Shifter


Timing Diagram of Source Driver

Data latch

CLK

DIO1

128 CLKs

Invalid Driver 1 Driver 2

128 CLKs

DIO2

P1 P2 P3 P130P129P128P4 P5 P131 P132 P133P127

1st 384 Outputsfor 1~128 Pixel

2nd 384 Outputsfor 129~256 Pixel



Tst

POL

Odd outputs

Even outputs Negative

Positive

Tst

Vcom

OutputOutput load condition

LD

1K

15P

1K

15P

1K

15P

1K

15P

1K

15P

High-Z High-Z

High-Z

(CLK1)


Key Specificationsbull Channel number (384 402 420 480 640 720hellip)bull Gray scale (6 bit 8 bit 10 bithellip)bull Max operation frequency (45MHz 55MHz 65MHz 75MHzhellip)bull Pixel charging time (eg R=2k C=20pF 65us 90 115us 999)bull Framerowcolumndot inversionbull Output voltage deviation (plusmn20mV plusmn10mV plusmn5mV plusmn3mV)bull Output voltage (10V 12V 135V 15V 18V)bull Interface (TTL RSDS mini-LVDS)bull Operation voltage (25V 33V)bull No of Gamma reference voltage (10 14 18)bull Package (TCP COG COF)bull Others (data inversion low-power mode offset canceling charge

sharing hellipetc)



720

7

4201680x3WSXGA+7206424801920x3HDTV

4804321440x3WXGA

4141366x3WXGA

512

402

12

480

420

38431224019210 9

1400x3SXGA+

1600x3UXGA

2048x3QXGA

6404801280x3SXGAWXGA3841024x3XGA

480402300800x3SVGA384240640x3VGA568No of lines

bull Source driver No of driver and No of output channel


Resolution vs Max Frequency

107 μs2025 MHz133 μs162 MHzUXGAUXGA

125 μs135 MHz156 μs108 MHzSXGASXGA

167 μs7875 MHz207 μs65 MHzXGAXGA

213 μs495 MHz264 μs40 MHzSVGASVGA

267 μs315 MHz317 μs252 MHzVGAVGA

Horizontal period

Pixel frequency

Horizontal period

Pixel frequency

75 Hz75 Hz75 Hz75 Hz60 Hz60 Hz60 Hz60 HzFrame rateFrame rate

Higher resolution shorter pixel charging time higher driving frequency


DA Converter

bull Fundamentals of Data Converter

bull Digital-to-Analog Converters

資料來源Philip E Allen Douglas R Holberg rdquoCMOS analog circuit designrdquo Oxford 2002林克旯 ldquoADC及DAC積體電路實作rdquo MSD聯盟-混合訊號式積體電路設計技術推廣教育計畫


Fundamentals of Data Converter

bull Ideal DA converterbull Quantization error in ideal DACsbull Performance limitationbull Offset errorbull Gain errorbull Accuracy



Idea DA Converter

bull Ideal N-bit DACDigital input

1 2 011 2 12 2 2 2

n nin n n

b b bbB Lminus minusminus= + + + +

Where bi is 1 or 0 ie binary bn-1 is the MSB and b0 is the LSB



Idea DA Converter (cont)

bull Analog output Vout is related to Bin through an analog reference VRef

1 Vout and VRef may be voltage current or charge2 We assume here that they are voltage (for simplicity)3 Definitions

1 2 011 2 1

2 2 2 2

2

n nout ref ref inn n

refLSB N

b b bbV V L V B

VV

minus minusminus

⎛ ⎞= + + + + = times⎜ ⎟⎝ ⎠

= where VLSB is defined as the voltage changes when one LSB changes

bull 1 LSB = 12N unitless definition資料來源Philip E Allen Douglas R Holberg rdquoCMOS analog circuit designrdquo Oxford 2002林克旯 ldquoADC及DAC積體電路實作rdquo MSD聯盟-混合訊號式積體電路設計技術推廣教育計畫



bull An ideal 2-bit DAC exampleInput-output transfer curve In general the maximum value of Vout is not VRef but rather VRef(1-2-n) or equivalently VRef-VLSB

bull A multiplying DAC (MDAC) is realized by simply allowing the reference signal VREF to be a varying input signal along with BIN Such an arrangement results in Vout being proportional to the multiplication of the input signals BIN and VRef



Quantization Error in DACs

bull Quantization error (noise) is the inherent uncertainty in digitizing an analog value with a finite resolution converter It is equal to the analog output of the infinite-bit DAC minus that of the finite-bit DAC

bull Fig 1014 amp 1015



Performance Limitation

bull Definitions for determining the transfer responses for DACsndash The transfer response of a DAC is defined to be the

analog levels that occur for each of the digital wordbull Resolution

ndash The number of distinct analog levels corresponding to different digital words Thus an N-bit resolution implies that the converter can resolve 2N distinct analog levels



Offset Error

bull Offset error is in units of LSBsbull Offset error is the output that occurs for the input

code that should produce zero output

2-bit example

00( ) outoff

LSB

VE DAC V=

資料來源Philip E Allen Douglas R Holberg rdquoCMOS analog circuit designrdquo Oxford 2002林克旯 ldquoADC及DAC積體電路實作rdquo MSD聯盟-混合訊號式積體電路設計技術推廣教育計畫 Page 62 19598(上) NCHU EE 汪芳興 fansendragonnchuedutw

Gain Errorbull Gain error is the difference at the full-scale value between

the ideal and actual when the offset error has been reduced to zero

bull Gain error is in units of LSBsbull DACs

( ) 11 00 (2 1)Nout outgain DAC

LSB LSB

V VEV V

⎛ ⎞= minus minus minus⎜ ⎟

⎝ ⎠2-bit example



Accuracy

bull Absolute accuracyndash The difference between the expected and actual

and transfer responsendash Includes 1offset error 2 gain error 3 linearity

error

bull Relative accuracyndash The accuracy of offset and gain errors have been

removed



Accuracy (contrsquo)

bull Accuracy can be expressed as a percentage error of full-scale value as the effective number of bit or as a fraction of an LSBndash For example a 12-bit accuracy implies that the converterrsquos

error is less than the full-scale divided by 212ndash A converter may have 12-bit resolution with only 10-bit

accuracy or 10-bit resolution with 12-bit accuracyndash An accuracy greater than the resolution means that the

converterrsquos transfer response is very precisely controlled (better than the number of bits of resolution)



DA Converter





Digital-to-Analog Converters

bull Nyquist-rate DA converters

bull Decoder-based DAC

bull Binary-weighted converters

bull Glitches

bull Thermometer-code DACs



Nyquist-rate DA converters

bull Four main types

Decoder-based

Binary-weighted

Thermometer-code

Hybrid



Decoder-Based DAC

bull Most straight forward approachndash Create 2N reference signals and pass the

appropriate signal to the output

bull Three main typesndash Resistor string

ndash Folded resistor-string

ndash Multiple resistor-string



Decoder-Based DAC


appropriate signal to the outputbull Types

ndashResistor stringndash Folded resistor-string



R

R

R

R

R

R

R

R

R

b0 b0

b1 b1

b2

b2

Vout

VRef

2N resistors

Bin = b22-1+b12-2+b02-3

Resistor-string DACbull Example 1a 3-bit DAC

with transmission gate tree-like decoder

Transmission gates might be used rather than n-channel switches

Extra drain and source capacitance (to GND) is offset by the reduced switch resistanceLarger layoutCan operate closer to positive supply voltage



Resistor-string DAC (contrsquo)

bull Only n-channel switches are used 1 About the same speed as the transmission gate

implementation2 Compact layout (no contacts are required in the tree)

bull Monotonicity is guaranteed (if the bufferrsquos offset does not depend on its input voltage)

bull The accuracy of this DAC depends on the type of resistor uesd Polysilicon (20-30 Ω) can have up to 10 bits of accuracy




bull Speedndash Can be estimated using open-circuit time-constant

approach (refer to microelectronics textbook written by Sedra and Smith)

ndash Time-constant3 2 3 3

( 1) (2 3 )

tr tr tr tr tr tr

tr tr

R C R C N R C

N N R C

asymp + sdot + + sdot

= + sdot

L

Where Rtr is on resistance of switchesCtr is drain or source capacitance of switches andN is bit number




bull Example 2a 3-bit DAC with digital decoding

Compared to example11 Higher speed2 More area for decoding circuit

SpeedTime-constant asympRtrmiddot 2NCtr

For N≦6 example 2 is fasterFor Ngt7 example 1 is faster

bull Compromise between example 1 and example 2

Folded resistor-string DAC

R

R

R

R

R

R

R

R

R

VRef

Vout

b2

b1

b0

2N resistors (all equal-sized)

資料來源林克旯 ldquoADC及DAC積體電路實作rdquo MSD聯盟-混合訊號式積體電路設計技術推廣教育計畫


Decoder-Based DAC



ndash Resistor string

ndashFolded resistor-string



資料來源Philip E Allen Douglas R Holberg rdquoCMOS analog circuit designrdquo Oxford 2002蘇育民 ldquo數位類比轉換器設計與測試之研究rdquo 暨南國際大學電機工程學系碩士論文 2004 Page 76 19598(上) NCHU EE 汪芳興 fansendragonnchuedutw

Folded resistor-string DAC (contrsquo)

bull Reduced the amount of digital decodingbull Reduce large capacitive loadingbull Decoding is very similar to that for a digital memorybull Example

ndash 4 bit (2 bit+2 bit) DACndash Time constant asymp Rtrmiddot(22Ctr)+2Rtrmiddot(22Ctr)

bull Other design examplesndash 12 bit = 6 bit + 6 bit or 4 bit + 4 bit + 4 bit or helliphellipndash 10 bit = 5 bit + 5 bit or 3 bit + 3 bit + 4 bit or helliphellip

資料來源Philip E Allen Douglas R Holberg rdquoCMOS analog circuit designrdquo Oxford 2002蘇育民 ldquo數位類比轉換器設計與測試之研究rdquo 暨南國際大學電機工程學系碩士論文 2004





bull Binary-weighted convertersbull Glitches



Binary-Weighted (or Binary-Scaled) Converter

bull An appropriate set of signals that are all related in a binary fashion

bull The binary array of signals might be voltages charges or currents

bull Five main typesndash Binary-weighted resistor DACndash Reduced-resistor-ratio laddersndash R-2R-based DACndash Charge-redistribution switched-capacitor DACndash Current-mode DAC

資料來源Philip E Allen Douglas R Holberg rdquoCMOS analog circuit designrdquo Oxford 2002林克旯 ldquoADC及DAC積體電路實作rdquo MSD聯盟-混合訊號式積體電路設計技術推廣教育計畫蘇育民 ldquo數位類比轉換器設計與測試之研究rdquo 暨南國際大學電機工程學系碩士論文 2004


Binary-Weighted Resistor DAC

3 2 1

1 2 33 2 1

2 4 8 2 2 2

Fout F ref ref In

In

b b b RV R V V BR R R R

where B b b bminus minus minus

⎛ ⎞ ⎛ ⎞= minus minus minus minus = ⎜ ⎟⎜ ⎟⎝ ⎠⎝ ⎠

= + + +LL

bull 4-bit example

資料來源Philip E Allen Douglas R Holberg rdquoCMOS analog circuit designrdquo Oxford 2002 p624


Binary-weighted resistor DAC (contrsquo)

bull Does not require many resistors or switchesbull Disadvantage

1 Resistor ratio and current ratio are on the order of 2N If N is large this large current ratio requires that the switches also be scaled so that equal voltage drops appear them

2 Monotonicity is no guaranteed3 Prone to glitch



Reduced-resistor-ratio Ladders

bull Reduce the large resistor ratios in a binary-weighted array

bull Introduce a series resistor to scale signals in portions of the arrayndash Ex VA= -14VRef



Reduced-resistor-ratio Ladders (contrsquo)

bull An additional 4R was added such that resistance seen to right of the 3R equals R

bull One-fourth the resistance ratio compared to the binary-weighted case

bull Current ratio has remained unchangedndash Switches must be scaled in size

bull Repeating this procedure recursively one can obtain an R-2R ladder



R-2R-based DAC

bull Smaller size and better accuracy than a binary-sized approach ndash Small number of componentsndash Resistance ratio of only 2

bull 4-bit example

bull Current ration isstill largerarr largeratio of switch sizes

11 1

_2 2 2

N Nref i R iF

R out F refi ii i

V b I bRI and V R VR Rminus

= =

sdot ⎛ ⎞= = sdot = sdot⎜ ⎟⎝ ⎠

sum sum



R-2R-based DAC (contrsquo)

bull R-2R ladder DAC with equal currents through switchesbull Slower since the internal nodes exhibit some voltage swings (as

opposed to the previous configuration where internal nodes all remain at fixed voltage)

資料來源呂學旺 ldquo場發射顯示器驅動電路之設計rdquo 國立交通大學電子工程學系碩士論文 1994魯得中 ldquo場效激發元件驅動器的設計rdquo 國立交通大學電子工程學系碩士論文 2003


Charge-redistribution switched-capacitor DAC

bull Insensitive to Op Amp input-offset voltage 1f noise and finite amplifier gain

bull An additional sign bit can be realized by interchanging the clock phases (shown in parentheses)

資料來源Philip E Allen Douglas R Holberg rdquoCMOS analog circuit designrdquo Oxford 2002


Current-mode DAC

bull High-speedbull Switch current to output or to groundbull The output current is converted to a voltage through RFbull The upper portion of current source always remains at

ground potential







bull Glitchesbull Thermometer-code DACs


Glitchesbull A major limitation during high-speed operationbull Mainly the result of different delays occurring when

switching different signalsbull Example01111helliphellip1rarr1000helliphellip0

1 I1 represents the MSB current and I2 represents the sum of (N-1) LSB currents

2 The MSB current turns off slightly early causing a glitch of zero current



Glitches (contrsquo)

bull Glitch disturbance can be reduced by1 Limiting the bandwidth (placing a capacitor

across RF)

2 Using a sample and hold on the output signal

3 Modifying some or all of the digital word from a binary code to a thermometer code







bull Glitches



Thermometer-Code DACbull Digital recode the input to a thermometer-code equivalent

bull Advantages over its binary-weighted counterpart1 Low DNL errors2 Guaranteed monotonicity3 Reduced glitching noise

bull Does not increase the size of the analog circuitry compared to a binary-weighted approach



Thermometer-Code DAC (contrsquo)

bull Total area required by the transistor switches is the samebull All transistor switches are of equal sizes since they all

pass equal currentsbull Example Thermometer-code resistor DAC



Thermometer-Code Current-Mode DAC

bull Row and column decoders

bull Inherent monotonicity

bull Good DNL errors

bull INL errors depend on the placement of the

current sources



Thermometer-Code Current-Mode DAC (contrsquo)

bull In high-speed applications1 The output current feeds directly into an off-chip

50Ω or 75Ω resistor rather than an output opamp2 Cascode current sources are used to reduce current-

source variation due to voltage changes in Vout



Examples of DAC 1bull Chun-Yueh Huang Tsung-Tien Hou Hung-Yu Wang ldquoA 10 bit 100-MHz

current-steering DACrdquo ASIC 2005 ASICON 2005 6th international Conference On Volume 1 24-0 Oct 2005 Page(s)411 - 414


Examples of DAC 2

12-bit DAC Paper- A Novel Linear Digital-to-Analog Converter using Capacitor coupled Adder for LCD Driver ICs


Examples of DAC 3bull 12 Bit Linear DAC using capacitor coupled adder


R-String DAC

R2

R2

R

R

R

R

R

R

R

b1b1

out

5

-19

b3b2b2 b3



R-String DAC (contrsquo)



DA Converter of Source Driver ICDAC with

ROM Decoder


Gamma Correction

Adjust the voltage of V1~V8 to obtain the desire transmittance

T-V curve is non-linear


Gamma Correction

18 Gamma Voltage10 Gamma Voltage

資料來源 Datasheet of Novetek Corp


R-String (ROM Decoder) DAC

AdvantagesSimple architecture

Low noise

Optimized gamma curve

DisadvantagesLarge area

Area increase rapidly as bit number increases

Steady current consumption in R-string


Output Buffer

DAC P

DAC N

Polarity control signal

OddOutput

EvenOutput

Gamma Voltage

(+)

Gamma Voltage

(-)

To data line

Rail to rail OP-AMP

-+

+-


Output Buffer

DAC P

negativebuffer


OddOutput

EvenOutput

Gamma Voltage

(+)

Gamma Voltage

(-)

To data line

Positive and negative signals are applied by DAC1 and DAC2 separately Dynamic range of each DAC is reduced to frac12 compared with conventional ones

PN type OP-AMP

DAC N

positivebuffer

+-

+-


OP-AMP ndash An Example

Wide Dynamic Range (Rail to Rail )

Low deviation

High driving ability

Low power consumption

Optimum OP AMP area


Design of Output Amplifierbull OP-AMP

V1V2

+

-

Vss

Vdd

+

-+

-

Vout=Av(V1-V2)+

-

Ref P E Allen D R Holberg ldquoCMOS Analog Circuit Designrdquo 2nd Ed Oxford 2002


Design of Output Amplifierbull CMOS OP-AMP

DifferentialTransconductance

stage

High-gainstage

OutputBuffer

Compensationcircuitry

Bias Circuitry

Vout VoutrsquoV1V2



Model for a Nonideal Op-Amp

bull Finite differential-input impedance Rid Cidbull Output resistance Routbull Common-mode input resistance Ricmbull Input offset voltage Vosbull Input offset current Ios=|IB1-IB2|bull Common-mode rejection ratio v1CMRRbull Noise in2 en

2

Vout(s)=Av(s)[v1(s)-V2(s)] plusmnAc(s)[v1(s)+V2(s)]2

Ref P E Allen D R Holberg ldquoCMOS Analog Circuit Designrdquo 2nd Ed Oxford 2002 Page 110 19598(上) NCHU EE 汪芳興 fansendragonnchuedutw

Classification of Op-Amp

Hierarchy

Current to voltage

Current to voltage

voltage to current

voltage to current

conversion

Classic differentialamplifier

Differential-to-single-ended load

(current mirror)

Transconductancegrounded gate

Class A (sourceor sink load)

modified differentialamplifier

Sourcesink Current load

MOS diodeload


Class B (push-pull)

Currentstage

1stvoltagestage

2ndvoltagestage



Examples of Op-Amp

bull Classical two-stage CMOS op amp

bull Folded-cascode op amp



Design of Op Amp

bull Proceduresndash Choosing or creating the basic

structurendash Select dc currents and transistor

sizendash Boundary conditions

bull Process specification (Vt krsquo Coxhellip)bull Supply voltagecurrent and rangebull Operating temperature and range

1 Hand calculation

2 Computer simulation



Design of Op AmpExample≧70 db≧5 MHz≦1 us≧5 Vus≧plusmn15 V≧60 db≧60 db≧plusmn15 VNA≦ plusmn 10 mV≦100 nVradicHz1 kHz≦ 5000 x (min L)2

ndash Performance requirementbull Gainbull Gain bandwidthbull Settling timebull Slew ratebull Input common-mode range ICMRbull Common-mode rejection ratio CMRRbull Power-supply rejection ratio PSRRbull Output voltage swingbull Output resistancebull Offsetbull Noisebull Layout area


Model Parameters for a Typical CMOS Bulk Process

V0807Surface potential at strong inversion2|φF|

V-1005(L=1um)001(L=2um)

004(L=1um)001(L=2um)

Channel length modulation parameterλ

V1205704Bulk threshold parameterγ

uAV2500plusmn101100plusmn10Transconductanceparameter (in sat)

Krsquo

V-07plusmn01507plusmn015Threshold voltage (VBS=0)VT0

p-channeln-channelunitTypical parameter valueProcess descriptionParameter

symbol

Model parameters for a typical CMOS bulk process using the simple model with values based on a 08um silicon-gate bulk CMOS n-well



Design of Op Ampbull Procedures

ndash Decide on a suitable configurationbull Trade-off between noise offset powerhellip

ndash Determine the compensation methodbull Especially for very large CLOAD

ndash Design device sizes for proper dc ac and transient performance

bull Hand calculation 80 important to get a feel for sensitivity of parameter variation

bull computer simulation 20 for optimization

Rule (use of simulator) x (common sense) = constant


Frequency and Phase Response (13)

bull For a single-loop negative-feedback system

Stable |A(jω0deg) F(jω0deg)| = |L(jω0deg)| lt 1where ω0deg is defined as Arg[- A(jω0deg) F(jω0deg)] = Arg[L(jω0deg)] = 0deg

or Arg[- A(jω0dB) F(jω0dB)] = Arg[L(jω0dB)] gt 0degwhere ω0dB is defined as |A(jω0dB) F(jω0dB)| = |L(jω0dB)| = 1

A(s)

F(s)

+

-ΣVin(s) Vout(s)




bull Bode Plotsndash |A(jω) F(jω)| amp Arg[- A(jω) F(jω)]


Phase MarginΦM = Arg[L(jω0dB)]



bull Time response of a second-order systemndash Large PM results in less lsquoringingrsquo good stabilityndash PM gt45deg (at least) gt 60deg (preferable)



Second-order Uncompensated Op Amp

bull Small-Signal Equivalent Circuit


Prsquo1=-1(RICI)Prsquo2=-1(RIICII)

If F(s)=1 (worst case)PM ltlt 45deg

need compensation


Miller Compensation of Op Ampbull Miller Compensation Technique

P1= -1(gmIIRIRIICC)P2= - gmIICC (CICII+ CCCII+ CICC) ≒ - gmIICII

Z1 = gmIICC

CII gtgt CI CC


Miller Compensation of Op Ampbull Root locus plot of the

loop gain F(s)=1

bull Bode plotsndash P2 does not affect the

magnitude until after |AF|lt1

ndash Z1 increases the phase shift


Two Stage Op Amp with Parasitic Cbull There are more than two pole due to C1 C2 C3bull We will concentrate on two most dominant (small) pole

and the RHP zero


C

m

C

mI

Cg

CgGB 2=cong

C

m

C

mI

m

II

mII

Cm

dsdsdsds

CmII

III

Cg

Cgz

Cg

Cgp

Cggggg

CgGGp

21

2

62

6

76421

))((

=cong

minus=

minuscong

++minus=

minuscong

Unit gain bandwidth


Miller Compensation Techniquebull P1miller polemiller pole and accomplish the desire

compensationbull M6 is a NMOS CC is multiplied by the gain of the

2nd stage gmIIRII to give a capacitor in parallel with RI of gmIIRIICC

bull Multiplying gmIIRIICC times RI and inverting it Then we get

Cm

dsdsdsds

CmII

III

Cggggg

CgGGp

6

7642

1

))(( ++minus

=minus

cong


Miller Compensation Techniquebull P2output poleoutput pole at least equal to GB and is due to the

capacitance at the output of the op ampbull CII = CL(load capacitance)bull Since |p2| is near or greater than GB the reactance of CC

is approximately 1(GBCC) and is very smallbull M6 is a MOS diode and its small signal resistance is gm6

-1bull Multiplying gm6

-1 by CII and inverting gives


2

62 C

gCgp m

II

mII minus=

minuscong


Miller Compensation Techniquebull Z1 (the RHP zero) boosts the loop gain magnitude

while causing the loop phase shift to become more negative undesirable

bull It worsens the stability of the op ampbull It comes from the two feedback path

bull The signals through these two paths may be equal and opposite and cancel creating the zero

VsCRsCgRV

sCRRV

sCRsCRgsV

CII

CmII

CII

II

CII

CIImout 1

)1(1

1

)1()( 66

+minusminus

=⎟⎟⎠

⎞⎜⎜⎝

⎛+

+⎟⎟⎠

⎞⎜⎜⎝

⎛+

minus=

Vrsquorsquo

Vout

VDD

CC

Vrsquo

++

--

M6

RII


Output Deviation of Buffer

IC1 IC2

Vxidea voltage of gray m

VocOutput offset

between chip tochip

VdvoOutput deviation

Voabsolute offsetbetween chipidea voltage

V(m ave)Average output voltage

of gray m


Offset Cancellation

Voffset

VinVo=Vin+Voffset

VoffsetVo=Vin+VoffsetVin

Phase 1

Phase 2

Caz

Vcaz=(Vin+Voffset)-Vin

VoffsetVo=Vin+Voffset-VcazVin

Caz

Vo=Vin

How Long the Ph1 is enough to sample the correct VoffsetHow Long the Ph2 is enough to charge the pixel voltage

+-

+ -

- +

- +

- +-+


Layout of Source Driver

Channel 384

Channel 383

Channel 382

Channel 381

Channel 4

Channel 3

Channel 2

Channel 1

Length

Height

384 channel source driver

Channel 420

Channel 419

Channel 418

Channel 417

Channel 4

Channel 3

Channel 2

Channel 1


Channel 480

Channel 479

Channel 478

Channel 477

Channel 4

Channel 3

Channel 2

Channel 1

480 channel source driver Gamma

resistor

Gammaresistor

Gammaresistor

Layout lengthchannel ＜ 2 cm 480 = 41 um


TSMC HV Process


Power Saving mode (1)

1st IC 2nd IC 3rd IC 4th IC 5th IC 6th IC 7th IC 8th IC

LCD Panel

Start pulse

Start pulse input for 1st IC

Start pulse output for 1st IC

Clock disable signal for 1st IC

Start pulse input for 2nd IC

Start pulse output for 2nd IC

Clock disable signal for 2nd IC

Start pulse input for 8th IC

Start pulse output for 8th IC

Clock disable signal for 8th IC

dtdVCI times=

P = fdCloadVDD2

Turn on one clock



Distribute clock tree

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

clock

clock

Clock 2Clock 1

Clock 2Clock 1



Dual edge clocking

1 2 3 4

CK1XCK1CK2XCK2


Charge Sharing

To data line

DAC P

Charge SharingControl signal

OddOutput

EvenOutput

OP

OPDAC NData

Data

Vgmama+

Vgmama-

-+

-+


Charge Sharingbull Because only half of the charges with positive potential are

recycled power saving efficiency of the previous charge sharing is theoretically limited to 50


Waveform of LCD Driver


Power Consumption of LCD Source Driver

Power Consumption IC

CNS for Car

4~8mA

DSC Game PDA

2~3mA

05 ~ 2 mA

Mobile-phone

lt 03mA(power saving )

Large size panel


Trend of LCD Source Driver

6-bit 8-bit to 10 bit resolution

384 480 to gt500 output channels for SXGA+ WSXGA+ UXGA WUXGA panel

TTL to RSDSmini-LVDS data interface for low power and EMI issue

10V to 18V for wide-view-angle panel

Reduced chip size for cost down


TV application


Outline







LCD TV vs LCD Monitor


LCD TV Electronics

LCD Control Board

Display AreaHDTV 1920x1080 1280x720WXGA 1366x7681280x768

SDTV 720x480

cable

Data driverData driverPCB with data bus

DCDC power

ASIC(T-CON RSDSTTLtransmitter)

Scan driverScan driver

Inverter Back light unit

LCD Module

TTLLVDSTMDS

γ

Gamma Volt GenMiniMini--LVDSLVDSRSDSRSDSTTLTTL

OSD

Scaler

MCU

ADCAnalog

RGB

VideoDecoder

DigitalDVI

TMDSRx

De-interlace

Tuner

YC

SyncSep

Compositevideo

AntennaRF in

YCbCr

YPbPr

Set-Top BoxAntennaCable


Digital TV System

Digital Tuner VSBCOFDMDemodulator

MPEG2Decoder PODCI

32MB DDRSDRAM

Scaler IC


LCD-TV Control ICbull Trumpion-Zipro Chip


LCD TV Block Diagram

TUNERTUNER SAWSAW VIFSIFVIFSIF

OSDOSDCONTROLLERCONTROLLER

RESETRESET

RGBRGB DECODERDECODER

SWITCHSWITCH

ELECTRONICELECTRONICVOLVOL

PowerPower MOSFETMOSFET

DiodesDiodes

LCDLCDDRIVERDRIVER

PANELPANEL 1F1Fγγ CORRECTCORRECT

MICONMICON

BACKBACK LIGHTLIGHTDCDC--DCDC

CONVERTERCONVERTERDCDC--ACAC

INVERTERINVERTER

ComplexComplex DevicesDevices(PNP+NPN)(PNP+NPN)

LCDLCDPANELPANEL

POWERAMPPOWERAMP

EXTERNALEXTERNALSOUNDSOUND

EXTERNALEXTERNALVIDEOVIDEO スキャンコンバータスキャンコンバータ

2SC39502SC3950LC74723MLC74723MLC74725MLC74725MLC74781MLC74781MLC74782MLC74782MLC74883MLC74883M

LA7585LA7585LA758788LA758788

LA7565LA7565

NTSCPALNTSCPAL AFOutputAFOutput

LA426061LA426061LA426570LA426570LA428082LA428082

STK401STK401--XXXXXX

LA7221LA7221

Audiovideo SwitchAudiovideo Switch

LA5661LA5662LA5661LA5662FTS2005FW332ECH8605~6FTS2005FW332ECH8605~6

2SD1804T2SD1802T2SD1804T2SD1802T2SC57062SC5706--PM2SJ5032SJ485PM2SJ5032SJ485

CPH310931163216320532125504CPH3109311632163205321255042SA20392SC55662SC57072SA20392SC55662SC5707

ビデオ出力ドライバビデオ出力ドライバ

CPH31153109CPH31153109CPH5702CPH5706CPH5702CPH5706

LC41XXLC41XXLC758XXLC758XX

LC875448ALC875448ALC87F54C8ALC87F54C8A

LA76818LA76818LA863228LA863228

FSS140132134FSS140132134CPH33043414CPH33043414

SVC208SVC208SVC230SVC230

CPH5506CPH5506

LA426642674268LA426642674268LA427642774278LA427642774278

SBS004005006SBS004005006SBE001SBE002SBE001SBE002


De-interlacebull example


Luminance of LCD vs CRT

Display Quality for Moving Picture Which is Better


Black Insertion

bull Emulate impulse-type displayndash Turn off backlightndash Insert black data or clear the data on pixel

bull Double frame rate (60 -gt 120 -gt 240 Hz)


Adjustable Gamma Curve

DAC

γminus18R1 string

γminus22R2 string

γminus26R3 string

switch

Gamma control code(from T-CON)

Vref [118] Vout

8-bit Data

Use external Gamma control code to control final Gamma resistance rings

V0~V255



γminus18 γminus22 γminus26

example


Over 8-bit Color Depth

Over-8 bit data

Vref [118]new DACnew DAC

with with γγ--R stringR string

Vout (over-8 bit resolution)

8 bit Source driver IC 10 bit 12 bit


Overdrive for LCD TV

Gn-1

Gn

Gray Level

Framen n+2n+1n-1n-2 n+3

Ideal Response Voltage by Driver

Actual Response

Gn-1

Gn

Gray Level


Gn

Overdrive Response

Voltage by Driver

Conventional Overdrive


FFD ( Feedforward Driving )Method by Mitsubishi

Tr+ Tf asymp 25ms (ONOFF)Tr Tf lt 20ms (Gray Level)

Effect on LC Overdrive


Overdrive Circuits

Memory

Lookup Table

Control ckts

Data

Dn

Dn+1

Ctrl

addressReadWrite

Datarsquo


Over-8 bit color depthDynamic gamma correctionDynamic backlight control

Dynamic Contrast Enhancementbr

ight

ness

Normal image

brig

htne

ss

bright imagebr

ight

ness

dark imagePage 154 19598(上) NCHU EE 汪芳興 fansendragonnchuedutw

Other Technologies

bull 10 bit color depth (source driver IC)ndash 107 billion colors

bull LED backlightndash R G B mixed LED BLU

bull NTSC ratio gt 100bull RGB color sequential method (CF-free)bull Power consumptionbull Thin module thickness

bull Digital Image Processingndash SonyWEGA enginehellip


LCD TV Trends

Technology trends and challenges

Size

BrightnessCR

Response Time

LCD Monitor

15-20rdquo

250400

25~16ms

Viewing angle 140160

Resolution XGA~UXGA

2002~2003

LCD TV

15-20rdquo 20-30rdquo 32-65rdquo

400~550500~700 gt550gt2k

25~16ms 16~12ms lt 8 ms

160160 176176

SVGA~WXGA WUXGA~HDTV

2004~2008

challenge

COST


Outline







Applications of Small Size Display

TFTTFT


Small-Size TFT-LCD Driver IC

Controller025 μm

Sourcedriver05 μm

DCDC converter06 μm HV

Gatedriver

06 μm HV

Controller + Source driver

DCDC converter+ gate driver

HV

Single chipHV

4 Chip TCPCOF Type

2 Chip COGCOF Type

1 Chip COG Type

小尺寸TFT-LCD驅動晶片解決方案演進圖

HitachiSamsung

奇景聯詠

智寶科技


Architecture of One Chip TFT-LCD Driver IC

bull Simple IC Sketch for TFT Mobile Phonendash 25V BlockOSC SRAM APR Some Logic

ndash 5V BlockIO Source Regulator Charge Pump (PWR)

ndash 3240V BlockGate Regulator Charge Pump (PWR)

Gate Driver Source Driver

PWR SRAMGAMA64

APRSRAM

Gate Driver

PWR


Single Chip TFT-LCD Driver IC for Mobile Phone Application

18

64

18

(176+2)CHGate Driver

Gate control

PowerSupplyCircuit

TimingGenerator

OSCSystem Interface

181698-bit parallel 3-pin SPI

Indexregister

Controlregister

graylevelgenerator

396 ChannelSource Driver

Built-in GRAM132x18x176 bit

Read WriteData latch

Gammaadjusting

Addresscounter

VGHVGL

VgoffGVDDVGS

AVDD

18

G17

7G

176

G17

5 G

2G

1G

0

S396

S395

S394

S3 S2 S1

SPIC

ontrol

RW

Data

VDD3VDD

Latch circuitand

Vcom


Voltage Setting

VcomL(VCL+05 to 10V)

VDD(20V ~ 33V)

Note adjust the conditions of AVDD-GVDD gt 05V VcomL-VCL gt 05V and VgoffL-VGL gt 05V with loads becauseThey differ depending on the display load to be driven In addition Vci can be directly input to Vci1

VCI(25V ~ 33V)

BT2-0

BT2-0

VRH3-0

VREG2OUT

VCOM4-0

VGH(+9 ~ +165V)

AVDD(+35~ +55V)

VcomH(+30~ VREG1OUT)

VCL

VgoffH (to -50V)

VgoffL(VGL+05 to -5V)

VGL (-165 to -9V)

-1 times-1 times

VREG1OUT

VDV4-0

VCI1

VC2-0

VSS(0V)

VC3=1VRL3-0

GVDD(+30~ +50V)

VC3=0VRL3-0


Voltage Waveforms


sn(source output)

VCOM

Gn (Gate output)

VGH(+9 ~ +165V)


VgoffH (~to -50V)


GVDD(+30~ +50V)VDD(20V ~ 33V)

AVDD(+35~ +55V)

VSS(0V)

電壓波形設定示意圖


Power Pins Description (12)

A power supply for the TFT-display counter electrodeThe alternating cycle can be set by the M pin Connect this pin to the TFT-display counter electrodeThis pin is also used as equalizing function When EQ = ldquoHighrdquo period all source driverrsquos outputs (S1 to S396) are short to

Vcom level (Hi-z) In case of VcomL lt 0V equalizing function must not be used (Set EQ bit (R07h) to be ldquo00rdquo for preventing the abnormal function)

OVcomOUT

This pin outputs a reference voltage for VREG2 between VSS and VGL When the internal reference voltage is not used the reference voltage can be generated from the voltage of REGN Connect this pin to a capacitor for stabilization When this pin is not used leave it open

OVREG2OUT

This pin outputs a reference voltage for VREG1 between AVDD and VSS When the internal reference voltage is not used the reference voltage can be generated from the voltage of REGP Connect this pin to a capacitor for stabilization When this pin is not used leave it open

OVREG1OUT

Input pins for reference voltages of VREG1OUT when the internal reference-voltage generation circuit is not used Leave these pins open when the internal reference-voltage generation circuit is used

IOREGP

A power supply pin for generating VcomL When VcomL is higher than VSS outputsVSS levelIOVCL

System ground level for analog circuit block-AVSS

System ground (0V)-VSS

An internal reference power supply for VREG1OUTVREG2OUTConnect VDD when VDD = 25 to 33 VConnect a 25 to 33 V external-voltage power supply when VDD = 20 to 25 V

IOVCI

Standard level for grayscale voltage generatorConnect a capacitor for stabilizationIOGVDD

A power output pin for source driver block that is generated from power blockConnect a capacitor for stabilization (AVDD +35 ~ +55 V)Connect this pin to VCI2 pin When not using a charge-pump circuit 1 leave it open

IOAVDD

System power supply for regulator as external power(VDD3 +25 ~ +33 V)-VDD3

System power supplyAs NT3911 has internal regulator VDD range varies with each modeNon-regulated mode (PregB = 1) +20 ~ +25 VRegulated mode (PregB = 0) +20V

-VDD

DescriptionIOSymbol



When the Vgoff alternation is driven this pin indicates a low level of Vgoff Connect a capacitor for stabilization An internal register can be used to adjust the voltage

OVgoffL

When the Vgoff alternation is driven this pin indicates a high level of Vgoff Connect a capacitor for stabilization When the CAD bit is low the VgoffH output stops and a capacitor for stabilization is not needed

OVgoffH

An power output pin for gate driverThis pin is a negative voltage for the gate off level Alternation can be synchronized by M pin Set the internal register

according to the structure of the TFT-display retention volumeFor the amplitude at the alternation driving this pin outputs a voltage between VcomH and VcomL with the VgoffL reference

voltage

OVgoffOUT

Power supply pin for off level for gate of TFTConnect this pin to VgoffOUT When VgoffOUT is not used connect an external-voltage power supply higher than -TBD V

IVgoff

A Negative power output pin for gate driver bias circuits and operational amplifiersConnect a capacitor for stabilization When internal VGL generator is not used connect an external-voltage power supply

higher than -150 V

OVGL

A positive power output pin for gate driver internal charge-pump circuits bias circuits and operational amplifiers Connect a capacitor for stabilization

Connect this pin to VCI3 pin When not using a charge-pump circuit 2 leave it open

OVGH

When the Vcom alternation is driven this pin indicates a low level of Vcom An internal register can be used to adjust the voltage Connect this pin to a capacitor for stabilization

When the VCOMG bit is low the VcomL output stops and a capacitor for stabilization is not needed

OVcomL

This pin indicates a high level of Vcom generated in driving the Vcom alternationConnect this pin to the capacitor for stabilization

OVcomH

A reference voltage of VcomHWhen VcomH is externally adjusted halt the internal adjuster of VcomH by setting the register and insert a variable resistor

between VREG1OUT and VSS When this pin is not externally adjusted leave it open and adjust VcomH by setting the internal register

IVcomR

DescriptionIOSymbol


Power Definition (12)

mA2015-IVCI

uA500200-IVDDOperating Current

No load VDD3=3V VDD=2V VCI=27V VBS=VSS and all operating is stoppeduA5--IscPower consumption for Stand-

by mode

G0 ~ G177 Vo=18V vs 175V VGH-VGOFF=30VuA--250IGOHGate Driver Driving Current of

Outputs

G0 ~ G177 Vo=-12V vs -115V VGH-VGOFF=30VuA--| -250 |IGOLGate Driver Sinking Current of

Outputs

S1 ~ S396 Vo=45V vs 35VAVDD=5V Gradation outputuA--50ISOHSource Driver Driving Current of

Outputs

S1 ~ S396VGVDD-01-01VdrDynamic Range of Output

Source DrivermV-plusmn20-VocOutput Offset between Chips

Source DrivermV-plusmn20-VodOutput Voltage deviation

V33-25VCIInternal reference power supply voltage

V5-3GVDD

V-5--16VGOFF

V-9--165VGL

V165-9VGH

For the analog circuit power

V55-35AVDD

LCD Supply Voltage

ConditionsUnitMaxTypMinSymbolParameter

(VDD =20V VDD3=3V VSS =0V TA=25 oC)

(For the analog circuit)


Power Definition(22)(For the regulator circuit)

VCI=33V VC2-0=rdquo100rdquo VRH3-0=rdquo1001rdquoVDV4-0=rdquo01101rdquoV-109-111-113VCOMLLow level reference voltage of

Vcom

VCI=33V VC2-0=rdquo100rdquo VRH3-0=rdquo1001rdquoVCM4-0=rdquo10101rdquoV475466457VCOMHHigh level reference voltage of

Vcom

VCI=33V VRL3-0=rdquo0001rdquoV-673-66-647VgoffLLow level reference voltage of Vgoff

VCI=33V VC2-0=rdquo100rdquo VRH3-0=rdquo1001rdquoVDV4-0=rdquo01101rdquoV-081-083-085VgoffHHigh level reference voltage of

Vgoff

uA150-100IGVDDGVDD driving current

uA-100--500IVREG2VREG2OUT driving currentVCI=33V VRL3-0=rdquo0001rdquo

V-673-66-647VREG2OUT

Reference voltage output for gate driver

mA25-1IVREG1VREG1OUT driving currentVCI=33V VC2-0=rdquo100rdquo VRH3-0=rdquo1001rdquo

V595583571VREG1OUT

Reference voltage for grayscale voltage generator

VCI=33V VC2-0=rdquo100rdquoV25625246REGPReference voltage of VREG1OUT

uA500200-IRVDDRVDD driving currentVDD3=33V

V2120195RVDDReference voltage for internal digital power


(Reference for system design)


Power Supply Circuits

VCI2

VCI VCI

VDDVSSVCIVSS

C7

int

VGL

VGH

C1VGH

C22P

C16

A dj u s t V C O M Hv ol t ag e ( w he nusing an ex temalvar ia ble res i sto r)

C11+

C1 5REGP

VCL

C31MVCI3

C22M

C12-C12+

C11-Vci1

VCIOUT

VCOMR

VGOFFOUT

VGOFFL

C20

C19

VCOMOUT

VCOMH

VREG1OUT

VREG2OUT

C 21

C 11

AmplificationCircuit2

(Vgoffadjustment)

AmplificationCircuit 1(GVDD

adjustment)

VcomHadjustment

circuit

VcomAmplitudeadjustment

circuit

GVDDoutput

amplifier

VcomHoutput

amplifier

VcomLoutput

amplifier

VgoffHoutput

amplifierVgoffLoutput

amplifier

VgoffHamplitudeadjustment

circuit

C12

C9GVDD

VGOFFH

C10

Voltageadjustment

circuitRegulator

Charge-pump

circuit 1

C23PC23M

C21M

Charge-pump

circuit 2

C21P

C31P Charge-pump

circuit 3

C41-Vci4

C41+ Charge-pump

circuit 4

REGN

C14C17

AVDD

C18

C4

C3

C2

C6

VC1

C5

C3

Configuration of the Internal Power-supply Circuit

AVDD

VGL

GVDD

VCOML


GAMMA ADJUSTMENT FUNCTION bull The NT3911 provides the gamma adjustment function to display 262144 colors

simultaneously The gamma adjustment executed by the gradient adjustment register and the micro-adjustment register that determines 8 grayscale levels

R5 G 5R4 R3 R2 R1 G4 G 3 G2 G1 G 0 B4 B3 B2 B1B5R0 B0

GRAMMSB LSB

PKP00PKP01PKP02

PKP10PKP11PKP12

PKP20PKP21PKP22

PKP30PKP31PKP32

PKP40PKP41PKP42

PKP50PKP51PKP52

PRP00PRP01PRP02

PRP10PRP11PRP12

VRP00VRP01VRP02

VRP10VRP11VRP12

VRP03

VRP13VRP14

PKN00PKN01PKN02

PKN10PKN11PKN12

PKN20PKN21PKN22

PKN30PKN31PKN32

PKN40PKN41PKN42

PKN50PKN51PKN52

PRN00PRN01PRN02

PRN10PRN11PRN12

VRN00VRN01VRN02

VRN10VRN11VRN12

VRN03

VRN13VRN14

Positivepolarityregister

Negativepolarityregister

GrayscaleAm plifier

8 64 grayscalecontrol

ltRgt

LCD driver

64 grayscalecontrol

ltG gt

LCD driver

64 grayscalecontrol

ltBgt

LCD driver

64

V1

V0

V63

6 6 6

R G BLCD


Scan Mode

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176

G176 G174 G172 hellip G4 G2G175 G173 G171 hellip G3 G1

11


01

G176 G175 G174 G173 hellip G4 G3 G2 G110

G1 G2 G3 G4 hellip G173 G174 G175 G17600

Scan ModeGSSM

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176

bull Gate scan mode of NT3911 is set by SM and GS bit GS bit determines the scan direction whether the gate driver scans forward or reverse direction SM bit determines the method of display division (EvenOdd or UpperLower division drive) Using this function various connections between NT3911 and the liquid crystal panels can be accomplished

A

B

C

D

A

B

C

D


Structure of Grayscale Amplifier bull The structure of the grayscale amplifier is shown as below Determine

8-level (VIN0-VIN7) by the gradient adjuster and the micro adjustment register Each level is split by the internal ladder resistance and level between V0 to V63 is generated

G r a d ie n t a d ju s t m e n tr e g i s t e r M ic r o a d ju s t m e n t r e g is t e r ( 6 X 3 b i t s ) O s c i l la t i o n a d ju s t m e n t

r e g i s t e rP R P N 0 P R P N 1 P K P N 0 P K P N 1 P K P N 2 P K P N 3 P K P N 4 P K P N 4 V R P N 0 V R P N 1

33 3 3 3 54333

8 t o 1s e le c t o r


8 t o 1s e l e c t o r




L a d d e rr e s is t a n c e

G V D D

V G S

G r a y s c a l ea m p l i f i e r

V I N P N 0

V I N P N 1

V I N P N 2

V I N P N 3

V I N P N 4

V I N P N 5

V I N P N 6

V I N P N 7

V 0

V 6 3

V 6 2

V 5 5

V 4 3

V 2 0

V 8

V 1V 2V 3

V 9

V 2 1

V 4 4

V 5 6V 5 7


Gamma Adjustment Register bull This block has the register to set up the grayscale voltage adjusting

to the gamma specification of the LCD panel These registers canindependently set up to positivenegative polarities and there are 4-type of register groups to adjust gradient and amplitude on number of the grayscale characteristics of the grayscale voltage (average ltRgtltGgtltBgt are common) The following figure indicates the operation of each adjusting register

Grayscale Number Grayscale Number Grayscale Number Grayscale Number

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

a) Gradient adjustment b) Amplitude adjustment c) Reference adjustment d) Micro-adjustment


Chip Size amp Pad Dimensions

bull NOTESbull Scribe line included in this chip size (Scribe line 120um)

8080Dummy Pad1195239742

7036Output Pad10054Input Pad

Pad sizeum

250020720-Chip sizeYX

UnitSize

Pad nameItems


Process Feature for One Chip Driver IC

025um1P3M (MIM Process)

LV (Dual Gate) HV 25V 5V 40V (+-20V)Oxide Thickness 48A 110A 1000A

40V HVMOS Structure LDMOSLV HV Well Structure Retrograde Drive-In Well + NBL

Isolation STI P-EPIGate Material Poly (SD Implant Doped) + Salicide

S D Area SalicideCapacitor MIM

High Rs Poly 400~2000 Ohm

Technology

Source Novatek training material


Product Applications

bull TFT Driver IC for Mobile Phone

bull STN Driver IC for Mobile Phonendash NT7523為Hi-Fas CSTN One Chip Driver IC使用025μm

25532V Process



LV and HV Device Type and Related Data (1)

25 5V Devices Characterization5 LV Devices ( 25V NMOS and PMOS 5V NMOS and PMOS 25V Native NMOS ) STI Field IsolationTriple Well StructureSalicide Structure

25 5V Devices Cross Section Sketch

LV and HV Device Type

Source Novatek training material Page 176 19598(上) NCHU EE 汪芳興 fansendragonnchuedutw

LTPS TFT-LCD Driver ICs

LTPSTFT-LCDA-Si TFT-LCD

Gat

e D

river

IC

Source Driver ICT-Con T-Con

Gat

e D

river

IC

T-Con

LTPS TFT-LCD

Simplified Source Driver IC

Source Driver IC

Gat

e D

river

IC

De-MUX

Conventional a-Si TFT-LCD

LTPS TFT-LCDExample 1


非晶矽與多晶矽 TFT-LCD 驅動方式比較圖


Outline







Interfaces in TFT-LCD Monitor


Digital vs Analog


Panel Input Interface


TTL vs LVDS


Comparison of TTLRSDSand Mini-LVDS

TTL RSDS Mini-LVDS Remark 8-bit 24X2 24 12 Bus lines 6-bit 18X2 18 10

Voltage Swing 33V 200mV 200mV Lower amplitude for reducing EMI

XGA 325M (2 ports)

67M ( 1 port)

67M (2 ports)

SXGA 54M (2 ports)

54M (2 ports)

108M (2 ports)

Frequency

UXGA - 81M 162M LCD

Application ~SXGA ~ UXGA ~ QXGA

PCB Area 1 07~08 05~07 T-CON Pins 6-bit ~100 ~64 ~100

Driver IC Input Pins

6-bit ~80 ~60 ~50

Remark RSDS and Mini-LVDS use twin-pair lines


RSDS Definition

bull Reduced Swing Differential Signalndash plusmn200 mV swing (typical)ndash 21 mux - 2 data per clock cyclendash 100 ohm differential terminalsndash Voffset = 12 Vndash RGB data and clock only

bull Apply to bus between T-Con and source driversndash Reduce EMIndash Reduce power consumptionndash Reduce source driver bus width


8 Bit RGB RSDS Data

Start pulseR0 R1

R2 R3

R4 R5

G0 G1

G2 G3G4 G5

B0 B1

B2 B3

B4 B5

Invalid data

Invalid data

Invalid data

R6 R7

G6 G7

B6 B7


System Diagram RSDS Configuration

Single-end

FrontBack


RSDS Features and Benefits

bull Reduced pin T-Con countsndash Enable smaller area PCBs

bull Reduced number of componentsndash Small area PCBsndash Lower costndash Number of componentsTTLRSDS = 190101 (in

141rdquo XGA) 468 reduction

bull Reduced number of PCB layersndash Number of layersTTL RSDS = 64


Mini-LVDS

Data Bus Structure


Mini-LVDS

6 bit data 5 pairs


8 bit data 6 pairs

Mini-LVDS


RSDS is the major interface

Mini-LVDS become important for high resolution panel

RSDS Mini-LVDSPCB Size Larger Smaller

TCON XGA TQFP6480SXGAUXGATQFP128144

TQFP100

Driver Size Same SameFrequency Limitation DIO(Start Pulse) NoResolution Limitation lt= UXGADual Buses QXGA or largerDual BusesPossible Driver Vendors More Limited

RSDS vs Mini-LVDS


Point to Point Differential Signaling (PPDS)

bull PPDS is based largely on the RSDStrade

bull Advantagesndash The total number of input signals

for each column driver is greatly reduced

bull 8-bit RSDS system 12 data pairsand the clock pair by each column driver

bull In a PPDS system signal data pairand a clock pair

bull 26 in RSDS 4 in PPDS

2mA2mATypical Output Current

50Ω50ΩTransmission Lines

08V13VCommon Mode Voltage

plusmn200mVplusmn200mVDifferential Signal Level

PPDSRSDSParameter

Table 1 Comparison of PPDS and RSDS levels


PPDSTM

bull Advantages (cont)ndash improved signal integrity

bull typical RSDS bus architecture bull vias and stubs on every signal

line creates a large number of impedance discontinuities

bull point to point system no vias and stubs data signal maintain higher level Higher color depth

ndash Major improvement in EMIbull Due to the incoming LVDS clock

and PPDS clock operating at different frequency


PPDS Protocol

bull The total reduction in data signals from an RSDS based system to the PPDS architecture

bull The protocol is split into 5 required intervaland 1 optional interval


SummariesTechnology Trends of Large-Size TFT-LCD Source Driver IC

10-bit(1024灰階)


Memo

19598(上) NCHU EE 汪芳興 fansendragonnchuedutw


bull Example


Gate Driver IC

bull Also called scan driver or row driverbull Function

ndash Read in start signalndash Progressively turn on pixel TFTs on each gate linendash Turn off TFT during pixel holding period

bull Design considerationndash RC delay of bus line (for large-size panel)

bull Capacitive coupling driving (CC driving)bull Gate-driver in panel


Gate Driver Architecture

Bi-directional Shift Register

Level Shifter

Output Buffer

CLKSP1

buffer

levelshift

SR

buffer

levelshift

SR

buffer

levelshift

SR

buffer

levelshift

SR

buffer

levelshift

SR

Out1 Out2 Out3 Outn

SP2

Gate driver IC 電路方塊圖

VDDGND

VGGVEE

digital

analog

SR frequency 10k~75kHz Output voltage range gt 12V

To Display Area

RESET

ENB

UpDown

CLKSP1


Timing of Gate Driver

G1

G2

G256

Gate driver 1

CLK

STP

G1

G2

Gate driver 2

Gat

e dr

iver

1G

ate

driv

er 2

256 CLK


Key Specifications















256192154128768XGAXGA200150120600SVGASVGA

120480VGAVGA

33445566lines







Example


φ

φ

φ

φ

IN OUT



Shift Register


element



G1

G2

W X

Y Z



CLK

CLK

CLK

CLK

SP(L)

ENB1ENB2

S1 S2

N1 N2

US 6157361SHARP



US 6724361 B1



Vpp

GND

Vout

N2

P2

Vcc

GND

N1

P1

Vin

Vdd

GND

OUT

T2

T1

IN

Inverter Type





Vcc

GND

Vout

N2

P2

Vcc

GND

N1

P1

Vin

N3

P3

Vcc

Vdd

P4

Vdd

VccN4

Vdd

GND

M1

M2

INPUT

M3

Vdd

GND

M4

M5

M6

INPUT

OUTPUT

Latch Type


US 4486670INTERSIL


Output Buffer

IN OUT



TSMC HV Process




Source Web of TSMC





Vd 1

CLC

Vpixel

CstTFT

Vd 2 Vd 3Vg N-2

Vg N-1

Vg N

VdN-2

VdNVdN-1

VdN+1


~10us ~10us

1 frame ~16ms

Two-Line Scanning




Dual Driving


gt 40ldquo

RefIDW 00rsquo p167


Gate Driver Design







bull Cst on gate

CstClc

Cgd

Cds

Scan line n

Scan line n-1

Vcom

3-level

Vghl Vgc

Pixel voltage

V1V2

V3321 VVV Δ+Δ=Δ





+++times=Δ 1

CdsCgdCstClcCstVgcV

+++times=Δ 2

CdsCgdCstClcCgdVgcV

+++times=Δ 3


CgdCstCgdVghlVgc+

times= then

778205040

05025

4710504040


=+

=+

timesΔ=

=++

times=Δ

gds

gdghlgc

gd

CCC

VV

VV



Data Center

Positive Driving

Negative Driving


Black(+)

White(+)

Black(-)


Positive Driving

Negative Driving


Final Vcom

Positive Driving

Negative Driving


Black(+)

White(+)

Black(-)

White(-)

Black(+)

White(+)

Black(-)

White(-)


Cs on gate

CstClc

Cgd

Cds

Scan line n

Scan line n-1

Vcom

Negative Polarity

GN-1(+)

VP

V1V2

V3


Positive Polarity

V4

V5

V6

GN(-)

GN-1(-)

GN(+)

VP

Vcom

Vblack(+)

Vblack(-)

Vg Ve+

Ve-Vg






( ) ( )

( )

( )CgdCCstCgdVeV

CgdCCstCstVeV

CgdCCstCgdVeVgV

LC

LC

LC

++timesminus=Δ

++times+=Δ

++timesminus+=Δ

)(3

)(2

)(1 ( ) ( )

( )

( )CgdCCstCgdVeV

CgdCCstCstVeV

CgdCCstCgdVeVgV

LC

LC

LC

++times+=Δ

++timesminus=Δ

++times+minus=Δ

)(6

)(5

)(4

CstCgdVgVeVe

VVVVVV



2)()(

654321Q




Data Center

Positive Driving

Negative Driving

Black(+)

White(+)White(-)


Black(-)


Data Center

Positive Driving

Negative Driving

Black(+)

White(+)White(-)

Black(-)





VVVV2-level driving

high voltage

high voltage

Lowhigh voltage

Lowhigh voltage

Output range


DotColumnRowFrame

Vcom ACDC






















Analog Data Driver


Shift Register

pixel

Qi Qi+1Video

in

pixel



Video in

control

pixel

Qi+1 Qi+2


Samplecapacitor

hold capacitor








SIPO1 phase

SISO1 phase




Pixel1

Pixel2

Pixel3

Pixel4

Pixel5

Pixel6

Pixel7

Pixel8



SR

Video in






Driver IC


Sample

Hold

Buffer

Sample

Hold

Buffer

Sample

Hold

Buffer

Sample

Hold

Buffer

SR SR SR SR


Pixel1

Pixel2

Pixel3

Pixel4

Pixel5

Pixel6

Pixel7

Pixel8


DeMUX 12



Videoin


Driver


LAAT vs PAAT







Digital Data Driver






lowhighcost






AnalogDigital



Latch Signal

Polarity Signal

Analog Part

Digital Part

To LCD data line

CLKDIO1

Out1 Out2 Out3 Outn

DIO2

HoldReg

Sample Reg

SR

Buffer

LevelShifter

HoldReg

Sample Reg

SR

Buffer

LevelShifter

HoldReg

Sample Reg

SR

Buffer

LevelShifter

HoldReg

Sample Reg

SR

Buffer

LevelShifter

HoldReg

SR

Buffer

LevelShifter

sample reg


Dat

are

ceiv

er


Datain

Output buffers

Level Shifter



Data latch

CLK

DIO1

128 CLKs


128 CLKs

DIO2

P1 P2 P3 P130P129P128P4 P5 P131 P132 P133P127





Tst

POL

Odd outputs


Positive

Tst

Vcom


LD

1K

15P

1K

15P

1K

15P

1K

15P

1K

15P

High-Z High-Z

High-Z

(CLK1)



sharing hellipetc)



720

7

4201680x3WSXGA+7206424801920x3HDTV

4804321440x3WXGA

4141366x3WXGA

512

402

12

480

420

38431224019210 9

1400x3SXGA+

1600x3UXGA

2048x3QXGA











Horizontal period

Pixel frequency

Horizontal period

Pixel frequency




DA Converter









Idea DA Converter


1 2 011 2 12 2 2 2

n nin n n








1 2 011 2 1

2 2 2 2

2


refLSB N

b b bbV V L V B

VV

minus minusminus

⎛ ⎞= + + + + = times⎜ ⎟⎝ ⎠




















Offset Error



2-bit example

00( ) outoff

LSB

VE DAC V=






LSB LSB

V VEV V





Accuracy



error


removed










DA Converter









bull Glitches






Decoder-based

Binary-weighted

Thermometer-code

Hybrid



Decoder-Based DAC








Decoder-Based DAC






R

R

R

R

R

R

R

R

R

b0 b0

b1 b1

b2

b2

Vout

VRef

2N resistors

Bin = b22-1+b12-2+b02-3


















( 1) (2 3 )

tr tr tr tr tr tr

tr tr

R C R C N R C

N N R C


= + sdot

L











R

R

R

R

R

R

R

R

R

VRef

Vout

b2

b1

b0




Decoder-Based DAC



























3 2 1

1 2 33 2 1

2 4 8 2 2 2

Fout F ref ref In

In




= + + +LL

bull 4-bit example





















R-2R-based DAC


bull 4-bit example


11 1

_2 2 2

N Nref i R iF

R out F refi ii i


= =


sum sum













Current-mode DAC


ground potential

















across RF)









bull Glitches


















current sources












Examples of DAC 2





R-String DAC

R2

R2

R

R

R

R

R

R

R

b1b1

out

5

-19

b3b2b2 b3







ROM Decoder


Gamma Correction




Gamma Correction






Low noise






Output Buffer

DAC P

DAC N


OddOutput

EvenOutput

Gamma Voltage

(+)

Gamma Voltage

(-)

To data line

Rail to rail OP-AMP

-+

+-


Output Buffer

DAC P

negativebuffer


OddOutput

EvenOutput

Gamma Voltage

(+)

Gamma Voltage

(-)

To data line


PN type OP-AMP

DAC N

positivebuffer

+-

+-




Low deviation



Optimum OP AMP area



V1V2

+

-

Vss

Vdd

+

-+

-

Vout=Av(V1-V2)+

-





stage

High-gainstage

OutputBuffer


Bias Circuitry

Vout VoutrsquoV1V2





2




Hierarchy

Current to voltage

Current to voltage

voltage to current

voltage to current

conversion



(current mirror)





MOS diodeload


Class B (push-pull)

Currentstage

1stvoltagestage

2ndvoltagestage



Examples of Op-Amp





Design of Op Amp





1 Hand calculation









V-1005(L=1um)001(L=2um)

004(L=1um)001(L=2um)




Krsquo



symbol
















A(s)

F(s)

+

-ΣVin(s) Vout(s)

















need compensation




Z1 = gmIICC

CII gtgt CI CC



loop gain F(s)=1






and the RHP zero


C

m

C

mI

Cg

CgGB 2=cong

C

m

C

mI

m

II

mII

Cm

dsdsdsds

CmII

III

Cg

Cgz

Cg

Cgp

Cggggg

CgGGp

21

2

62

6

76421

))((

=cong

minus=

minuscong

++minus=

minuscong

Unit gain bandwidth






Cm

dsdsdsds

CmII

III

Cggggg

CgGGp

6

7642

1

))(( ++minus

=minus

cong








2

62 C

gCgp m

II

mII minus=

minuscong






VsCRsCgRV

sCRRV

sCRsCRgsV

CII

CmII

CII

II

CII

CIImout 1

)1(1

1

)1()( 66

+minusminus

=⎟⎟⎠

⎞⎜⎜⎝

⎛+

+⎟⎟⎠

⎞⎜⎜⎝

⎛+

minus=

Vrsquorsquo

Vout

VDD

CC

Vrsquo

++

--

M6

RII



IC1 IC2


VocOutput offset

between chip tochip




of gray m


Offset Cancellation

Voffset

VinVo=Vin+Voffset


Phase 1

Phase 2

Caz



Caz

Vo=Vin


+-

+ -

- +

- +

- +-+



Channel 384

Channel 383

Channel 382

Channel 381

Channel 4

Channel 3

Channel 2

Channel 1

Length

Height


Channel 420

Channel 419

Channel 418

Channel 417

Channel 4

Channel 3

Channel 2

Channel 1


Channel 480

Channel 479

Channel 478

Channel 477

Channel 4

Channel 3

Channel 2

Channel 1


resistor

Gammaresistor

Gammaresistor



TSMC HV Process




LCD Panel

Start pulse










dtdVCI times=

P = fdCloadVDD2

Turn on one clock




ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

clock

clock

Clock 2Clock 1

Clock 2Clock 1



Dual edge clocking

1 2 3 4

CK1XCK1CK2XCK2


Charge Sharing

To data line

DAC P


OddOutput

EvenOutput

OP

OPDAC NData

Data

Vgmama+

Vgmama-

-+

-+









CNS for Car

4~8mA

DSC Game PDA

2~3mA

05 ~ 2 mA

Mobile-phone


Large size panel









TV application


Outline









LCD TV Electronics

LCD Control Board


SDTV 720x480

cable


DCDC power




LCD Module

TTLLVDSTMDS

γ


OSD

Scaler

MCU

ADCAnalog

RGB

VideoDecoder

DigitalDVI

TMDSRx

De-interlace

Tuner

YC

SyncSep

Compositevideo

AntennaRF in

YCbCr

YPbPr



Digital TV System


MPEG2Decoder PODCI

32MB DDRSDRAM

Scaler IC







RESETRESET


SWITCHSWITCH



DiodesDiodes

LCDLCDDRIVERDRIVER


MICONMICON



INVERTERINVERTER


LCDLCDPANELPANEL

POWERAMPPOWERAMP




LA7585LA7585LA758788LA758788

LA7565LA7565


LA426061LA426061LA426570LA426570LA428082LA428082


LA7221LA7221









LA76818LA76818LA863228LA863228

FSS140132134FSS140132134CPH33043414CPH33043414


CPH5506CPH5506

LA426642674268LA426642674268LA427642774278LA427642774278








Black Insertion





DAC

γminus18R1 string

γminus22R2 string

γminus26R3 string

switch


Vref [118] Vout

8-bit Data


V0~V255




example



Over-8 bit data







Gn-1

Gn

Gray Level



Actual Response

Gn-1

Gn

Gray Level


Gn

Overdrive Response

Voltage by Driver







Overdrive Circuits

Memory

Lookup Table

Control ckts

Data

Dn

Dn+1

Ctrl

addressReadWrite

Datarsquo




ight

ness

Normal image

brig

htne

ss

bright imagebr

ight

ness


Other Technologies






LCD TV Trends


Size

BrightnessCR

Response Time

LCD Monitor

15-20rdquo

250400

25~16ms


Resolution XGA~UXGA

2002~2003

LCD TV


400~550500~700 gt550gt2k

25~16ms 16~12ms lt 8 ms

160160 176176


2004~2008

challenge

COST


Outline








TFTTFT



Controller025 μm

Sourcedriver05 μm


Gatedriver

06 μm HV



HV

Single chipHV

4 Chip TCPCOF Type

2 Chip COGCOF Type

1 Chip COG Type


HitachiSamsung

奇景聯詠

智寶科技







PWR SRAMGAMA64

APRSRAM

Gate Driver

PWR



18

64

18


Gate control

PowerSupplyCircuit

TimingGenerator

OSCSystem Interface


Indexregister

Controlregister

graylevelgenerator




Gammaadjusting

Addresscounter

VGHVGL

VgoffGVDDVGS

AVDD

18

G17

7G

176

G17

5 G

2G

1G

0

S396

S395

S394

S3 S2 S1

SPIC

ontrol

RW

Data

VDD3VDD

Latch circuitand

Vcom


Voltage Setting


VDD(20V ~ 33V)


VCI(25V ~ 33V)

BT2-0

BT2-0

VRH3-0

VREG2OUT

VCOM4-0

VGH(+9 ~ +165V)

AVDD(+35~ +55V)


VCL

VgoffH (to -50V)


VGL (-165 to -9V)

-1 times-1 times

VREG1OUT

VDV4-0

VCI1

VC2-0

VSS(0V)

VC3=1VRL3-0

GVDD(+30~ +50V)

VC3=0VRL3-0


Voltage Waveforms


sn(source output)

VCOM

Gn (Gate output)

VGH(+9 ~ +165V)


VgoffH (~to -50V)


GVDD(+30~ +50V)VDD(20V ~ 33V)

AVDD(+35~ +55V)

VSS(0V)






OVcomOUT


OVREG2OUT


OVREG1OUT


IOREGP





IOVCI



IOAVDD



-VDD

DescriptionIOSymbol




OVgoffL


OVgoffH



voltage

OVgoffOUT


IVgoff


higher than -150 V

OVGL



OVGH



OVcomL


OVcomH



IVcomR

DescriptionIOSymbol



mA2015-IVCI



by mode


Outputs


Outputs


Outputs





V5-3GVDD

V-5--16VGOFF

V-9--165VGL

V165-9VGH


V55-35AVDD

LCD Supply Voltage







Vcom


Vcom



Vgoff






V595583571VREG1OUT









VCI2

VCI VCI

VDDVSSVCIVSS

C7

int

VGL

VGH

C1VGH

C22P

C16


C11+

C1 5REGP

VCL

C31MVCI3

C22M

C12-C12+

C11-Vci1

VCIOUT

VCOMR

VGOFFOUT

VGOFFL

C20

C19

VCOMOUT

VCOMH

VREG1OUT

VREG2OUT

C 21

C 11


(Vgoffadjustment)


adjustment)

VcomHadjustment

circuit


circuit

GVDDoutput

amplifier

VcomHoutput

amplifier

VcomLoutput

amplifier

VgoffHoutput


amplifier


circuit

C12

C9GVDD

VGOFFH

C10

Voltageadjustment

circuitRegulator

Charge-pump

circuit 1

C23PC23M

C21M

Charge-pump

circuit 2

C21P

C31P Charge-pump

circuit 3

C41-Vci4

C41+ Charge-pump

circuit 4

REGN

C14C17

AVDD

C18

C4

C3

C2

C6

VC1

C5

C3


AVDD

VGL

GVDD

VCOML





GRAMMSB LSB

PKP00PKP01PKP02

PKP10PKP11PKP12

PKP20PKP21PKP22

PKP30PKP31PKP32

PKP40PKP41PKP42

PKP50PKP51PKP52

PRP00PRP01PRP02

PRP10PRP11PRP12

VRP00VRP01VRP02

VRP10VRP11VRP12

VRP03

VRP13VRP14

PKN00PKN01PKN02

PKN10PKN11PKN12

PKN20PKN21PKN22

PKN30PKN31PKN32

PKN40PKN41PKN42

PKN50PKN51PKN52

PRN00PRN01PRN02

PRN10PRN11PRN12

VRN00VRN01VRN02

VRN10VRN11VRN12

VRN03

VRN13VRN14



GrayscaleAm plifier


ltRgt

LCD driver

64 grayscalecontrol

ltG gt

LCD driver

64 grayscalecontrol

ltBgt

LCD driver

64

V1

V0

V63

6 6 6

R G BLCD


Scan Mode

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176


11


01

G176 G175 G174 G173 hellip G4 G3 G2 G110

G1 G2 G3 G4 hellip G173 G174 G175 G17600

Scan ModeGSSM

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176


A

B

C

D

A

B

C

D






33 3 3 3 54333








G V D D

V G S


V I N P N 0

V I N P N 1

V I N P N 2

V I N P N 3

V I N P N 4

V I N P N 5

V I N P N 6

V I N P N 7

V 0

V 6 3

V 6 2

V 5 5

V 4 3

V 2 0

V 8

V 1V 2V 3

V 9

V 2 1

V 4 4

V 5 6V 5 7





Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge





8080Dummy Pad1195239742


Pad sizeum


UnitSize

Pad nameItems









Technology






25532V Process










Gat

e D

river

IC


Gat

e D

river

IC

T-Con

LTPS TFT-LCD


Source Driver IC

Gat

e D

river

IC

De-MUX






Outline









Digital vs Analog




TTL vs LVDS





XGA 325M (2 ports)

67M ( 1 port)

67M (2 ports)

SXGA 54M (2 ports)

54M (2 ports)

108M (2 ports)

Frequency

UXGA - 81M 162M LCD




6-bit ~80 ~60 ~50



RSDS Definition




8 Bit RGB RSDS Data

Start pulseR0 R1

R2 R3

R4 R5

G0 G1

G2 G3G4 G5

B0 B1

B2 B3

B4 B5

Invalid data

Invalid data

Invalid data

R6 R7

G6 G7

B6 B7



Single-end

FrontBack








Mini-LVDS

Data Bus Structure


Mini-LVDS

6 bit data 5 pairs


8 bit data 6 pairs

Mini-LVDS






TQFP100


RSDS vs Mini-LVDS













PPDSRSDSParameter



PPDSTM








PPDS Protocol





10-bit(1024灰階)


Memo


Key Specifications















256192154128768XGAXGA200150120600SVGASVGA

120480VGAVGA

33445566lines







Example


φ

φ

φ

φ

IN OUT



Shift Register


element



G1

G2

W X

Y Z



CLK

CLK

CLK

CLK

SP(L)

ENB1ENB2

S1 S2

N1 N2

US 6157361SHARP



US 6724361 B1



Vpp

GND

Vout

N2

P2

Vcc

GND

N1

P1

Vin

Vdd

GND

OUT

T2

T1

IN

Inverter Type





Vcc

GND

Vout

N2

P2

Vcc

GND

N1

P1

Vin

N3

P3

Vcc

Vdd

P4

Vdd

VccN4

Vdd

GND

M1

M2

INPUT

M3

Vdd

GND

M4

M5

M6

INPUT

OUTPUT

Latch Type


US 4486670INTERSIL


Output Buffer

IN OUT



TSMC HV Process




Source Web of TSMC





Vd 1

CLC

Vpixel

CstTFT

Vd 2 Vd 3Vg N-2

Vg N-1

Vg N

VdN-2

VdNVdN-1

VdN+1


~10us ~10us

1 frame ~16ms

Two-Line Scanning




Dual Driving


gt 40ldquo

RefIDW 00rsquo p167


Gate Driver Design







bull Cst on gate

CstClc

Cgd

Cds

Scan line n

Scan line n-1

Vcom

3-level

Vghl Vgc

Pixel voltage

V1V2

V3321 VVV Δ+Δ=Δ





+++times=Δ 1

CdsCgdCstClcCstVgcV

+++times=Δ 2

CdsCgdCstClcCgdVgcV

+++times=Δ 3


CgdCstCgdVghlVgc+

times= then

778205040

05025

4710504040


=+

=+

timesΔ=

=++

times=Δ

gds

gdghlgc

gd

CCC

VV

VV



Data Center

Positive Driving

Negative Driving


Black(+)

White(+)

Black(-)


Positive Driving

Negative Driving


Final Vcom

Positive Driving

Negative Driving


Black(+)

White(+)

Black(-)

White(-)

Black(+)

White(+)

Black(-)

White(-)


Cs on gate

CstClc

Cgd

Cds

Scan line n

Scan line n-1

Vcom

Negative Polarity

GN-1(+)

VP

V1V2

V3


Positive Polarity

V4

V5

V6

GN(-)

GN-1(-)

GN(+)

VP

Vcom

Vblack(+)

Vblack(-)

Vg Ve+

Ve-Vg






( ) ( )

( )

( )CgdCCstCgdVeV

CgdCCstCstVeV

CgdCCstCgdVeVgV

LC

LC

LC

++timesminus=Δ

++times+=Δ

++timesminus+=Δ

)(3

)(2

)(1 ( ) ( )

( )

( )CgdCCstCgdVeV

CgdCCstCstVeV

CgdCCstCgdVeVgV

LC

LC

LC

++times+=Δ

++timesminus=Δ

++times+minus=Δ

)(6

)(5

)(4

CstCgdVgVeVe

VVVVVV



2)()(

654321Q




Data Center

Positive Driving

Negative Driving

Black(+)

White(+)White(-)


Black(-)


Data Center

Positive Driving

Negative Driving

Black(+)

White(+)White(-)

Black(-)





VVVV2-level driving

high voltage

high voltage

Lowhigh voltage

Lowhigh voltage

Output range


DotColumnRowFrame

Vcom ACDC






















Analog Data Driver


Shift Register

pixel

Qi Qi+1Video

in

pixel



Video in

control

pixel

Qi+1 Qi+2


Samplecapacitor

hold capacitor








SIPO1 phase

SISO1 phase




Pixel1

Pixel2

Pixel3

Pixel4

Pixel5

Pixel6

Pixel7

Pixel8



SR

Video in






Driver IC


Sample

Hold

Buffer

Sample

Hold

Buffer

Sample

Hold

Buffer

Sample

Hold

Buffer

SR SR SR SR


Pixel1

Pixel2

Pixel3

Pixel4

Pixel5

Pixel6

Pixel7

Pixel8


DeMUX 12



Videoin


Driver


LAAT vs PAAT







Digital Data Driver






lowhighcost






AnalogDigital



Latch Signal

Polarity Signal

Analog Part

Digital Part

To LCD data line

CLKDIO1

Out1 Out2 Out3 Outn

DIO2

HoldReg

Sample Reg

SR

Buffer

LevelShifter

HoldReg

Sample Reg

SR

Buffer

LevelShifter

HoldReg

Sample Reg

SR

Buffer

LevelShifter

HoldReg

Sample Reg

SR

Buffer

LevelShifter

HoldReg

SR

Buffer

LevelShifter

sample reg


Dat

are

ceiv

er


Datain

Output buffers

Level Shifter



Data latch

CLK

DIO1

128 CLKs


128 CLKs

DIO2

P1 P2 P3 P130P129P128P4 P5 P131 P132 P133P127





Tst

POL

Odd outputs


Positive

Tst

Vcom


LD

1K

15P

1K

15P

1K

15P

1K

15P

1K

15P

High-Z High-Z

High-Z

(CLK1)



sharing hellipetc)



720

7

4201680x3WSXGA+7206424801920x3HDTV

4804321440x3WXGA

4141366x3WXGA

512

402

12

480

420

38431224019210 9

1400x3SXGA+

1600x3UXGA

2048x3QXGA











Horizontal period

Pixel frequency

Horizontal period

Pixel frequency




DA Converter









Idea DA Converter


1 2 011 2 12 2 2 2

n nin n n








1 2 011 2 1

2 2 2 2

2


refLSB N

b b bbV V L V B

VV

minus minusminus

⎛ ⎞= + + + + = times⎜ ⎟⎝ ⎠




















Offset Error



2-bit example

00( ) outoff

LSB

VE DAC V=






LSB LSB

V VEV V





Accuracy



error


removed










DA Converter









bull Glitches






Decoder-based

Binary-weighted

Thermometer-code

Hybrid



Decoder-Based DAC








Decoder-Based DAC






R

R

R

R

R

R

R

R

R

b0 b0

b1 b1

b2

b2

Vout

VRef

2N resistors

Bin = b22-1+b12-2+b02-3


















( 1) (2 3 )

tr tr tr tr tr tr

tr tr

R C R C N R C

N N R C


= + sdot

L











R

R

R

R

R

R

R

R

R

VRef

Vout

b2

b1

b0




Decoder-Based DAC



























3 2 1

1 2 33 2 1

2 4 8 2 2 2

Fout F ref ref In

In




= + + +LL

bull 4-bit example





















R-2R-based DAC


bull 4-bit example


11 1

_2 2 2

N Nref i R iF

R out F refi ii i


= =


sum sum













Current-mode DAC


ground potential

















across RF)









bull Glitches


















current sources












Examples of DAC 2





R-String DAC

R2

R2

R

R

R

R

R

R

R

b1b1

out

5

-19

b3b2b2 b3







ROM Decoder


Gamma Correction




Gamma Correction






Low noise






Output Buffer

DAC P

DAC N


OddOutput

EvenOutput

Gamma Voltage

(+)

Gamma Voltage

(-)

To data line

Rail to rail OP-AMP

-+

+-


Output Buffer

DAC P

negativebuffer


OddOutput

EvenOutput

Gamma Voltage

(+)

Gamma Voltage

(-)

To data line


PN type OP-AMP

DAC N

positivebuffer

+-

+-




Low deviation



Optimum OP AMP area



V1V2

+

-

Vss

Vdd

+

-+

-

Vout=Av(V1-V2)+

-





stage

High-gainstage

OutputBuffer


Bias Circuitry

Vout VoutrsquoV1V2





2




Hierarchy

Current to voltage

Current to voltage

voltage to current

voltage to current

conversion



(current mirror)





MOS diodeload


Class B (push-pull)

Currentstage

1stvoltagestage

2ndvoltagestage



Examples of Op-Amp





Design of Op Amp





1 Hand calculation









V-1005(L=1um)001(L=2um)

004(L=1um)001(L=2um)




Krsquo



symbol
















A(s)

F(s)

+

-ΣVin(s) Vout(s)

















need compensation




Z1 = gmIICC

CII gtgt CI CC



loop gain F(s)=1






and the RHP zero


C

m

C

mI

Cg

CgGB 2=cong

C

m

C

mI

m

II

mII

Cm

dsdsdsds

CmII

III

Cg

Cgz

Cg

Cgp

Cggggg

CgGGp

21

2

62

6

76421

))((

=cong

minus=

minuscong

++minus=

minuscong

Unit gain bandwidth






Cm

dsdsdsds

CmII

III

Cggggg

CgGGp

6

7642

1

))(( ++minus

=minus

cong








2

62 C

gCgp m

II

mII minus=

minuscong






VsCRsCgRV

sCRRV

sCRsCRgsV

CII

CmII

CII

II

CII

CIImout 1

)1(1

1

)1()( 66

+minusminus

=⎟⎟⎠

⎞⎜⎜⎝

⎛+

+⎟⎟⎠

⎞⎜⎜⎝

⎛+

minus=

Vrsquorsquo

Vout

VDD

CC

Vrsquo

++

--

M6

RII



IC1 IC2


VocOutput offset

between chip tochip




of gray m


Offset Cancellation

Voffset

VinVo=Vin+Voffset


Phase 1

Phase 2

Caz



Caz

Vo=Vin


+-

+ -

- +

- +

- +-+



Channel 384

Channel 383

Channel 382

Channel 381

Channel 4

Channel 3

Channel 2

Channel 1

Length

Height


Channel 420

Channel 419

Channel 418

Channel 417

Channel 4

Channel 3

Channel 2

Channel 1


Channel 480

Channel 479

Channel 478

Channel 477

Channel 4

Channel 3

Channel 2

Channel 1


resistor

Gammaresistor

Gammaresistor



TSMC HV Process




LCD Panel

Start pulse










dtdVCI times=

P = fdCloadVDD2

Turn on one clock




ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

clock

clock

Clock 2Clock 1

Clock 2Clock 1



Dual edge clocking

1 2 3 4

CK1XCK1CK2XCK2


Charge Sharing

To data line

DAC P


OddOutput

EvenOutput

OP

OPDAC NData

Data

Vgmama+

Vgmama-

-+

-+









CNS for Car

4~8mA

DSC Game PDA

2~3mA

05 ~ 2 mA

Mobile-phone


Large size panel









TV application


Outline









LCD TV Electronics

LCD Control Board


SDTV 720x480

cable


DCDC power




LCD Module

TTLLVDSTMDS

γ


OSD

Scaler

MCU

ADCAnalog

RGB

VideoDecoder

DigitalDVI

TMDSRx

De-interlace

Tuner

YC

SyncSep

Compositevideo

AntennaRF in

YCbCr

YPbPr



Digital TV System


MPEG2Decoder PODCI

32MB DDRSDRAM

Scaler IC







RESETRESET


SWITCHSWITCH



DiodesDiodes

LCDLCDDRIVERDRIVER


MICONMICON



INVERTERINVERTER


LCDLCDPANELPANEL

POWERAMPPOWERAMP




LA7585LA7585LA758788LA758788

LA7565LA7565


LA426061LA426061LA426570LA426570LA428082LA428082


LA7221LA7221









LA76818LA76818LA863228LA863228

FSS140132134FSS140132134CPH33043414CPH33043414


CPH5506CPH5506

LA426642674268LA426642674268LA427642774278LA427642774278








Black Insertion





DAC

γminus18R1 string

γminus22R2 string

γminus26R3 string

switch


Vref [118] Vout

8-bit Data


V0~V255




example



Over-8 bit data







Gn-1

Gn

Gray Level



Actual Response

Gn-1

Gn

Gray Level


Gn

Overdrive Response

Voltage by Driver







Overdrive Circuits

Memory

Lookup Table

Control ckts

Data

Dn

Dn+1

Ctrl

addressReadWrite

Datarsquo




ight

ness

Normal image

brig

htne

ss

bright imagebr

ight

ness


Other Technologies






LCD TV Trends


Size

BrightnessCR

Response Time

LCD Monitor

15-20rdquo

250400

25~16ms


Resolution XGA~UXGA

2002~2003

LCD TV


400~550500~700 gt550gt2k

25~16ms 16~12ms lt 8 ms

160160 176176


2004~2008

challenge

COST


Outline








TFTTFT



Controller025 μm

Sourcedriver05 μm


Gatedriver

06 μm HV



HV

Single chipHV

4 Chip TCPCOF Type

2 Chip COGCOF Type

1 Chip COG Type


HitachiSamsung

奇景聯詠

智寶科技







PWR SRAMGAMA64

APRSRAM

Gate Driver

PWR



18

64

18


Gate control

PowerSupplyCircuit

TimingGenerator

OSCSystem Interface


Indexregister

Controlregister

graylevelgenerator




Gammaadjusting

Addresscounter

VGHVGL

VgoffGVDDVGS

AVDD

18

G17

7G

176

G17

5 G

2G

1G

0

S396

S395

S394

S3 S2 S1

SPIC

ontrol

RW

Data

VDD3VDD

Latch circuitand

Vcom


Voltage Setting


VDD(20V ~ 33V)


VCI(25V ~ 33V)

BT2-0

BT2-0

VRH3-0

VREG2OUT

VCOM4-0

VGH(+9 ~ +165V)

AVDD(+35~ +55V)


VCL

VgoffH (to -50V)


VGL (-165 to -9V)

-1 times-1 times

VREG1OUT

VDV4-0

VCI1

VC2-0

VSS(0V)

VC3=1VRL3-0

GVDD(+30~ +50V)

VC3=0VRL3-0


Voltage Waveforms


sn(source output)

VCOM

Gn (Gate output)

VGH(+9 ~ +165V)


VgoffH (~to -50V)


GVDD(+30~ +50V)VDD(20V ~ 33V)

AVDD(+35~ +55V)

VSS(0V)






OVcomOUT


OVREG2OUT


OVREG1OUT


IOREGP





IOVCI



IOAVDD



-VDD

DescriptionIOSymbol




OVgoffL


OVgoffH



voltage

OVgoffOUT


IVgoff


higher than -150 V

OVGL



OVGH



OVcomL


OVcomH



IVcomR

DescriptionIOSymbol



mA2015-IVCI



by mode


Outputs


Outputs


Outputs





V5-3GVDD

V-5--16VGOFF

V-9--165VGL

V165-9VGH


V55-35AVDD

LCD Supply Voltage







Vcom


Vcom



Vgoff






V595583571VREG1OUT









VCI2

VCI VCI

VDDVSSVCIVSS

C7

int

VGL

VGH

C1VGH

C22P

C16


C11+

C1 5REGP

VCL

C31MVCI3

C22M

C12-C12+

C11-Vci1

VCIOUT

VCOMR

VGOFFOUT

VGOFFL

C20

C19

VCOMOUT

VCOMH

VREG1OUT

VREG2OUT

C 21

C 11


(Vgoffadjustment)


adjustment)

VcomHadjustment

circuit


circuit

GVDDoutput

amplifier

VcomHoutput

amplifier

VcomLoutput

amplifier

VgoffHoutput


amplifier


circuit

C12

C9GVDD

VGOFFH

C10

Voltageadjustment

circuitRegulator

Charge-pump

circuit 1

C23PC23M

C21M

Charge-pump

circuit 2

C21P

C31P Charge-pump

circuit 3

C41-Vci4

C41+ Charge-pump

circuit 4

REGN

C14C17

AVDD

C18

C4

C3

C2

C6

VC1

C5

C3


AVDD

VGL

GVDD

VCOML





GRAMMSB LSB

PKP00PKP01PKP02

PKP10PKP11PKP12

PKP20PKP21PKP22

PKP30PKP31PKP32

PKP40PKP41PKP42

PKP50PKP51PKP52

PRP00PRP01PRP02

PRP10PRP11PRP12

VRP00VRP01VRP02

VRP10VRP11VRP12

VRP03

VRP13VRP14

PKN00PKN01PKN02

PKN10PKN11PKN12

PKN20PKN21PKN22

PKN30PKN31PKN32

PKN40PKN41PKN42

PKN50PKN51PKN52

PRN00PRN01PRN02

PRN10PRN11PRN12

VRN00VRN01VRN02

VRN10VRN11VRN12

VRN03

VRN13VRN14



GrayscaleAm plifier


ltRgt

LCD driver

64 grayscalecontrol

ltG gt

LCD driver

64 grayscalecontrol

ltBgt

LCD driver

64

V1

V0

V63

6 6 6

R G BLCD


Scan Mode

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176


11


01

G176 G175 G174 G173 hellip G4 G3 G2 G110

G1 G2 G3 G4 hellip G173 G174 G175 G17600

Scan ModeGSSM

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176


A

B

C

D

A

B

C

D






33 3 3 3 54333








G V D D

V G S


V I N P N 0

V I N P N 1

V I N P N 2

V I N P N 3

V I N P N 4

V I N P N 5

V I N P N 6

V I N P N 7

V 0

V 6 3

V 6 2

V 5 5

V 4 3

V 2 0

V 8

V 1V 2V 3

V 9

V 2 1

V 4 4

V 5 6V 5 7





Gra

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le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

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le V

olta

ge





8080Dummy Pad1195239742


Pad sizeum


UnitSize

Pad nameItems









Technology






25532V Process










Gat

e D

river

IC


Gat

e D

river

IC

T-Con

LTPS TFT-LCD


Source Driver IC

Gat

e D

river

IC

De-MUX






Outline









Digital vs Analog




TTL vs LVDS





XGA 325M (2 ports)

67M ( 1 port)

67M (2 ports)

SXGA 54M (2 ports)

54M (2 ports)

108M (2 ports)

Frequency

UXGA - 81M 162M LCD




6-bit ~80 ~60 ~50



RSDS Definition




8 Bit RGB RSDS Data

Start pulseR0 R1

R2 R3

R4 R5

G0 G1

G2 G3G4 G5

B0 B1

B2 B3

B4 B5

Invalid data

Invalid data

Invalid data

R6 R7

G6 G7

B6 B7



Single-end

FrontBack








Mini-LVDS

Data Bus Structure


Mini-LVDS

6 bit data 5 pairs


8 bit data 6 pairs

Mini-LVDS






TQFP100


RSDS vs Mini-LVDS













PPDSRSDSParameter



PPDSTM








PPDS Protocol





10-bit(1024灰階)


Memo





256192154128768XGAXGA200150120600SVGASVGA

120480VGAVGA

33445566lines







Example


φ

φ

φ

φ

IN OUT



Shift Register


element



G1

G2

W X

Y Z



CLK

CLK

CLK

CLK

SP(L)

ENB1ENB2

S1 S2

N1 N2

US 6157361SHARP



US 6724361 B1



Vpp

GND

Vout

N2

P2

Vcc

GND

N1

P1

Vin

Vdd

GND

OUT

T2

T1

IN

Inverter Type





Vcc

GND

Vout

N2

P2

Vcc

GND

N1

P1

Vin

N3

P3

Vcc

Vdd

P4

Vdd

VccN4

Vdd

GND

M1

M2

INPUT

M3

Vdd

GND

M4

M5

M6

INPUT

OUTPUT

Latch Type


US 4486670INTERSIL


Output Buffer

IN OUT



TSMC HV Process




Source Web of TSMC





Vd 1

CLC

Vpixel

CstTFT

Vd 2 Vd 3Vg N-2

Vg N-1

Vg N

VdN-2

VdNVdN-1

VdN+1


~10us ~10us

1 frame ~16ms

Two-Line Scanning




Dual Driving


gt 40ldquo

RefIDW 00rsquo p167


Gate Driver Design







bull Cst on gate

CstClc

Cgd

Cds

Scan line n

Scan line n-1

Vcom

3-level

Vghl Vgc

Pixel voltage

V1V2

V3321 VVV Δ+Δ=Δ





+++times=Δ 1

CdsCgdCstClcCstVgcV

+++times=Δ 2

CdsCgdCstClcCgdVgcV

+++times=Δ 3


CgdCstCgdVghlVgc+

times= then

778205040

05025

4710504040


=+

=+

timesΔ=

=++

times=Δ

gds

gdghlgc

gd

CCC

VV

VV



Data Center

Positive Driving

Negative Driving


Black(+)

White(+)

Black(-)


Positive Driving

Negative Driving


Final Vcom

Positive Driving

Negative Driving


Black(+)

White(+)

Black(-)

White(-)

Black(+)

White(+)

Black(-)

White(-)


Cs on gate

CstClc

Cgd

Cds

Scan line n

Scan line n-1

Vcom

Negative Polarity

GN-1(+)

VP

V1V2

V3


Positive Polarity

V4

V5

V6

GN(-)

GN-1(-)

GN(+)

VP

Vcom

Vblack(+)

Vblack(-)

Vg Ve+

Ve-Vg






( ) ( )

( )

( )CgdCCstCgdVeV

CgdCCstCstVeV

CgdCCstCgdVeVgV

LC

LC

LC

++timesminus=Δ

++times+=Δ

++timesminus+=Δ

)(3

)(2

)(1 ( ) ( )

( )

( )CgdCCstCgdVeV

CgdCCstCstVeV

CgdCCstCgdVeVgV

LC

LC

LC

++times+=Δ

++timesminus=Δ

++times+minus=Δ

)(6

)(5

)(4

CstCgdVgVeVe

VVVVVV



2)()(

654321Q




Data Center

Positive Driving

Negative Driving

Black(+)

White(+)White(-)


Black(-)


Data Center

Positive Driving

Negative Driving

Black(+)

White(+)White(-)

Black(-)





VVVV2-level driving

high voltage

high voltage

Lowhigh voltage

Lowhigh voltage

Output range


DotColumnRowFrame

Vcom ACDC






















Analog Data Driver


Shift Register

pixel

Qi Qi+1Video

in

pixel



Video in

control

pixel

Qi+1 Qi+2


Samplecapacitor

hold capacitor








SIPO1 phase

SISO1 phase




Pixel1

Pixel2

Pixel3

Pixel4

Pixel5

Pixel6

Pixel7

Pixel8



SR

Video in






Driver IC


Sample

Hold

Buffer

Sample

Hold

Buffer

Sample

Hold

Buffer

Sample

Hold

Buffer

SR SR SR SR


Pixel1

Pixel2

Pixel3

Pixel4

Pixel5

Pixel6

Pixel7

Pixel8


DeMUX 12



Videoin


Driver


LAAT vs PAAT







Digital Data Driver






lowhighcost






AnalogDigital



Latch Signal

Polarity Signal

Analog Part

Digital Part

To LCD data line

CLKDIO1

Out1 Out2 Out3 Outn

DIO2

HoldReg

Sample Reg

SR

Buffer

LevelShifter

HoldReg

Sample Reg

SR

Buffer

LevelShifter

HoldReg

Sample Reg

SR

Buffer

LevelShifter

HoldReg

Sample Reg

SR

Buffer

LevelShifter

HoldReg

SR

Buffer

LevelShifter

sample reg


Dat

are

ceiv

er


Datain

Output buffers

Level Shifter



Data latch

CLK

DIO1

128 CLKs


128 CLKs

DIO2

P1 P2 P3 P130P129P128P4 P5 P131 P132 P133P127





Tst

POL

Odd outputs


Positive

Tst

Vcom


LD

1K

15P

1K

15P

1K

15P

1K

15P

1K

15P

High-Z High-Z

High-Z

(CLK1)



sharing hellipetc)



720

7

4201680x3WSXGA+7206424801920x3HDTV

4804321440x3WXGA

4141366x3WXGA

512

402

12

480

420

38431224019210 9

1400x3SXGA+

1600x3UXGA

2048x3QXGA











Horizontal period

Pixel frequency

Horizontal period

Pixel frequency




DA Converter









Idea DA Converter


1 2 011 2 12 2 2 2

n nin n n








1 2 011 2 1

2 2 2 2

2


refLSB N

b b bbV V L V B

VV

minus minusminus

⎛ ⎞= + + + + = times⎜ ⎟⎝ ⎠




















Offset Error



2-bit example

00( ) outoff

LSB

VE DAC V=






LSB LSB

V VEV V





Accuracy



error


removed










DA Converter









bull Glitches






Decoder-based

Binary-weighted

Thermometer-code

Hybrid



Decoder-Based DAC








Decoder-Based DAC






R

R

R

R

R

R

R

R

R

b0 b0

b1 b1

b2

b2

Vout

VRef

2N resistors

Bin = b22-1+b12-2+b02-3


















( 1) (2 3 )

tr tr tr tr tr tr

tr tr

R C R C N R C

N N R C


= + sdot

L











R

R

R

R

R

R

R

R

R

VRef

Vout

b2

b1

b0




Decoder-Based DAC



























3 2 1

1 2 33 2 1

2 4 8 2 2 2

Fout F ref ref In

In




= + + +LL

bull 4-bit example





















R-2R-based DAC


bull 4-bit example


11 1

_2 2 2

N Nref i R iF

R out F refi ii i


= =


sum sum













Current-mode DAC


ground potential

















across RF)









bull Glitches


















current sources












Examples of DAC 2





R-String DAC

R2

R2

R

R

R

R

R

R

R

b1b1

out

5

-19

b3b2b2 b3







ROM Decoder


Gamma Correction




Gamma Correction






Low noise






Output Buffer

DAC P

DAC N


OddOutput

EvenOutput

Gamma Voltage

(+)

Gamma Voltage

(-)

To data line

Rail to rail OP-AMP

-+

+-


Output Buffer

DAC P

negativebuffer


OddOutput

EvenOutput

Gamma Voltage

(+)

Gamma Voltage

(-)

To data line


PN type OP-AMP

DAC N

positivebuffer

+-

+-




Low deviation



Optimum OP AMP area



V1V2

+

-

Vss

Vdd

+

-+

-

Vout=Av(V1-V2)+

-





stage

High-gainstage

OutputBuffer


Bias Circuitry

Vout VoutrsquoV1V2





2




Hierarchy

Current to voltage

Current to voltage

voltage to current

voltage to current

conversion



(current mirror)





MOS diodeload


Class B (push-pull)

Currentstage

1stvoltagestage

2ndvoltagestage



Examples of Op-Amp





Design of Op Amp





1 Hand calculation









V-1005(L=1um)001(L=2um)

004(L=1um)001(L=2um)




Krsquo



symbol
















A(s)

F(s)

+

-ΣVin(s) Vout(s)

















need compensation




Z1 = gmIICC

CII gtgt CI CC



loop gain F(s)=1






and the RHP zero


C

m

C

mI

Cg

CgGB 2=cong

C

m

C

mI

m

II

mII

Cm

dsdsdsds

CmII

III

Cg

Cgz

Cg

Cgp

Cggggg

CgGGp

21

2

62

6

76421

))((

=cong

minus=

minuscong

++minus=

minuscong

Unit gain bandwidth






Cm

dsdsdsds

CmII

III

Cggggg

CgGGp

6

7642

1

))(( ++minus

=minus

cong








2

62 C

gCgp m

II

mII minus=

minuscong






VsCRsCgRV

sCRRV

sCRsCRgsV

CII

CmII

CII

II

CII

CIImout 1

)1(1

1

)1()( 66

+minusminus

=⎟⎟⎠

⎞⎜⎜⎝

⎛+

+⎟⎟⎠

⎞⎜⎜⎝

⎛+

minus=

Vrsquorsquo

Vout

VDD

CC

Vrsquo

++

--

M6

RII



IC1 IC2


VocOutput offset

between chip tochip




of gray m


Offset Cancellation

Voffset

VinVo=Vin+Voffset


Phase 1

Phase 2

Caz



Caz

Vo=Vin


+-

+ -

- +

- +

- +-+



Channel 384

Channel 383

Channel 382

Channel 381

Channel 4

Channel 3

Channel 2

Channel 1

Length

Height


Channel 420

Channel 419

Channel 418

Channel 417

Channel 4

Channel 3

Channel 2

Channel 1


Channel 480

Channel 479

Channel 478

Channel 477

Channel 4

Channel 3

Channel 2

Channel 1


resistor

Gammaresistor

Gammaresistor



TSMC HV Process




LCD Panel

Start pulse










dtdVCI times=

P = fdCloadVDD2

Turn on one clock




ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

clock

clock

Clock 2Clock 1

Clock 2Clock 1



Dual edge clocking

1 2 3 4

CK1XCK1CK2XCK2


Charge Sharing

To data line

DAC P


OddOutput

EvenOutput

OP

OPDAC NData

Data

Vgmama+

Vgmama-

-+

-+









CNS for Car

4~8mA

DSC Game PDA

2~3mA

05 ~ 2 mA

Mobile-phone


Large size panel









TV application


Outline









LCD TV Electronics

LCD Control Board


SDTV 720x480

cable


DCDC power




LCD Module

TTLLVDSTMDS

γ


OSD

Scaler

MCU

ADCAnalog

RGB

VideoDecoder

DigitalDVI

TMDSRx

De-interlace

Tuner

YC

SyncSep

Compositevideo

AntennaRF in

YCbCr

YPbPr



Digital TV System


MPEG2Decoder PODCI

32MB DDRSDRAM

Scaler IC







RESETRESET


SWITCHSWITCH



DiodesDiodes

LCDLCDDRIVERDRIVER


MICONMICON



INVERTERINVERTER


LCDLCDPANELPANEL

POWERAMPPOWERAMP




LA7585LA7585LA758788LA758788

LA7565LA7565


LA426061LA426061LA426570LA426570LA428082LA428082


LA7221LA7221









LA76818LA76818LA863228LA863228

FSS140132134FSS140132134CPH33043414CPH33043414


CPH5506CPH5506

LA426642674268LA426642674268LA427642774278LA427642774278








Black Insertion





DAC

γminus18R1 string

γminus22R2 string

γminus26R3 string

switch


Vref [118] Vout

8-bit Data


V0~V255




example



Over-8 bit data







Gn-1

Gn

Gray Level



Actual Response

Gn-1

Gn

Gray Level


Gn

Overdrive Response

Voltage by Driver







Overdrive Circuits

Memory

Lookup Table

Control ckts

Data

Dn

Dn+1

Ctrl

addressReadWrite

Datarsquo




ight

ness

Normal image

brig

htne

ss

bright imagebr

ight

ness


Other Technologies






LCD TV Trends


Size

BrightnessCR

Response Time

LCD Monitor

15-20rdquo

250400

25~16ms


Resolution XGA~UXGA

2002~2003

LCD TV


400~550500~700 gt550gt2k

25~16ms 16~12ms lt 8 ms

160160 176176


2004~2008

challenge

COST


Outline








TFTTFT



Controller025 μm

Sourcedriver05 μm


Gatedriver

06 μm HV



HV

Single chipHV

4 Chip TCPCOF Type

2 Chip COGCOF Type

1 Chip COG Type


HitachiSamsung

奇景聯詠

智寶科技







PWR SRAMGAMA64

APRSRAM

Gate Driver

PWR



18

64

18


Gate control

PowerSupplyCircuit

TimingGenerator

OSCSystem Interface


Indexregister

Controlregister

graylevelgenerator




Gammaadjusting

Addresscounter

VGHVGL

VgoffGVDDVGS

AVDD

18

G17

7G

176

G17

5 G

2G

1G

0

S396

S395

S394

S3 S2 S1

SPIC

ontrol

RW

Data

VDD3VDD

Latch circuitand

Vcom


Voltage Setting


VDD(20V ~ 33V)


VCI(25V ~ 33V)

BT2-0

BT2-0

VRH3-0

VREG2OUT

VCOM4-0

VGH(+9 ~ +165V)

AVDD(+35~ +55V)


VCL

VgoffH (to -50V)


VGL (-165 to -9V)

-1 times-1 times

VREG1OUT

VDV4-0

VCI1

VC2-0

VSS(0V)

VC3=1VRL3-0

GVDD(+30~ +50V)

VC3=0VRL3-0


Voltage Waveforms


sn(source output)

VCOM

Gn (Gate output)

VGH(+9 ~ +165V)


VgoffH (~to -50V)


GVDD(+30~ +50V)VDD(20V ~ 33V)

AVDD(+35~ +55V)

VSS(0V)






OVcomOUT


OVREG2OUT


OVREG1OUT


IOREGP





IOVCI



IOAVDD



-VDD

DescriptionIOSymbol




OVgoffL


OVgoffH



voltage

OVgoffOUT


IVgoff


higher than -150 V

OVGL



OVGH



OVcomL


OVcomH



IVcomR

DescriptionIOSymbol



mA2015-IVCI



by mode


Outputs


Outputs


Outputs





V5-3GVDD

V-5--16VGOFF

V-9--165VGL

V165-9VGH


V55-35AVDD

LCD Supply Voltage







Vcom


Vcom



Vgoff






V595583571VREG1OUT









VCI2

VCI VCI

VDDVSSVCIVSS

C7

int

VGL

VGH

C1VGH

C22P

C16


C11+

C1 5REGP

VCL

C31MVCI3

C22M

C12-C12+

C11-Vci1

VCIOUT

VCOMR

VGOFFOUT

VGOFFL

C20

C19

VCOMOUT

VCOMH

VREG1OUT

VREG2OUT

C 21

C 11


(Vgoffadjustment)


adjustment)

VcomHadjustment

circuit


circuit

GVDDoutput

amplifier

VcomHoutput

amplifier

VcomLoutput

amplifier

VgoffHoutput


amplifier


circuit

C12

C9GVDD

VGOFFH

C10

Voltageadjustment

circuitRegulator

Charge-pump

circuit 1

C23PC23M

C21M

Charge-pump

circuit 2

C21P

C31P Charge-pump

circuit 3

C41-Vci4

C41+ Charge-pump

circuit 4

REGN

C14C17

AVDD

C18

C4

C3

C2

C6

VC1

C5

C3


AVDD

VGL

GVDD

VCOML





GRAMMSB LSB

PKP00PKP01PKP02

PKP10PKP11PKP12

PKP20PKP21PKP22

PKP30PKP31PKP32

PKP40PKP41PKP42

PKP50PKP51PKP52

PRP00PRP01PRP02

PRP10PRP11PRP12

VRP00VRP01VRP02

VRP10VRP11VRP12

VRP03

VRP13VRP14

PKN00PKN01PKN02

PKN10PKN11PKN12

PKN20PKN21PKN22

PKN30PKN31PKN32

PKN40PKN41PKN42

PKN50PKN51PKN52

PRN00PRN01PRN02

PRN10PRN11PRN12

VRN00VRN01VRN02

VRN10VRN11VRN12

VRN03

VRN13VRN14



GrayscaleAm plifier


ltRgt

LCD driver

64 grayscalecontrol

ltG gt

LCD driver

64 grayscalecontrol

ltBgt

LCD driver

64

V1

V0

V63

6 6 6

R G BLCD


Scan Mode

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176


11


01

G176 G175 G174 G173 hellip G4 G3 G2 G110

G1 G2 G3 G4 hellip G173 G174 G175 G17600

Scan ModeGSSM

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176


A

B

C

D

A

B

C

D






33 3 3 3 54333








G V D D

V G S


V I N P N 0

V I N P N 1

V I N P N 2

V I N P N 3

V I N P N 4

V I N P N 5

V I N P N 6

V I N P N 7

V 0

V 6 3

V 6 2

V 5 5

V 4 3

V 2 0

V 8

V 1V 2V 3

V 9

V 2 1

V 4 4

V 5 6V 5 7





Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge





8080Dummy Pad1195239742


Pad sizeum


UnitSize

Pad nameItems









Technology






25532V Process










Gat

e D

river

IC


Gat

e D

river

IC

T-Con

LTPS TFT-LCD


Source Driver IC

Gat

e D

river

IC

De-MUX






Outline









Digital vs Analog




TTL vs LVDS





XGA 325M (2 ports)

67M ( 1 port)

67M (2 ports)

SXGA 54M (2 ports)

54M (2 ports)

108M (2 ports)

Frequency

UXGA - 81M 162M LCD




6-bit ~80 ~60 ~50



RSDS Definition




8 Bit RGB RSDS Data

Start pulseR0 R1

R2 R3

R4 R5

G0 G1

G2 G3G4 G5

B0 B1

B2 B3

B4 B5

Invalid data

Invalid data

Invalid data

R6 R7

G6 G7

B6 B7



Single-end

FrontBack








Mini-LVDS

Data Bus Structure


Mini-LVDS

6 bit data 5 pairs


8 bit data 6 pairs

Mini-LVDS






TQFP100


RSDS vs Mini-LVDS













PPDSRSDSParameter



PPDSTM








PPDS Protocol





10-bit(1024灰階)


Memo


Shift Register


element



G1

G2

W X

Y Z



CLK

CLK

CLK

CLK

SP(L)

ENB1ENB2

S1 S2

N1 N2

US 6157361SHARP



US 6724361 B1



Vpp

GND

Vout

N2

P2

Vcc

GND

N1

P1

Vin

Vdd

GND

OUT

T2

T1

IN

Inverter Type





Vcc

GND

Vout

N2

P2

Vcc

GND

N1

P1

Vin

N3

P3

Vcc

Vdd

P4

Vdd

VccN4

Vdd

GND

M1

M2

INPUT

M3

Vdd

GND

M4

M5

M6

INPUT

OUTPUT

Latch Type


US 4486670INTERSIL


Output Buffer

IN OUT



TSMC HV Process




Source Web of TSMC





Vd 1

CLC

Vpixel

CstTFT

Vd 2 Vd 3Vg N-2

Vg N-1

Vg N

VdN-2

VdNVdN-1

VdN+1


~10us ~10us

1 frame ~16ms

Two-Line Scanning




Dual Driving


gt 40ldquo

RefIDW 00rsquo p167


Gate Driver Design







bull Cst on gate

CstClc

Cgd

Cds

Scan line n

Scan line n-1

Vcom

3-level

Vghl Vgc

Pixel voltage

V1V2

V3321 VVV Δ+Δ=Δ





+++times=Δ 1

CdsCgdCstClcCstVgcV

+++times=Δ 2

CdsCgdCstClcCgdVgcV

+++times=Δ 3


CgdCstCgdVghlVgc+

times= then

778205040

05025

4710504040


=+

=+

timesΔ=

=++

times=Δ

gds

gdghlgc

gd

CCC

VV

VV



Data Center

Positive Driving

Negative Driving


Black(+)

White(+)

Black(-)


Positive Driving

Negative Driving


Final Vcom

Positive Driving

Negative Driving


Black(+)

White(+)

Black(-)

White(-)

Black(+)

White(+)

Black(-)

White(-)


Cs on gate

CstClc

Cgd

Cds

Scan line n

Scan line n-1

Vcom

Negative Polarity

GN-1(+)

VP

V1V2

V3


Positive Polarity

V4

V5

V6

GN(-)

GN-1(-)

GN(+)

VP

Vcom

Vblack(+)

Vblack(-)

Vg Ve+

Ve-Vg






( ) ( )

( )

( )CgdCCstCgdVeV

CgdCCstCstVeV

CgdCCstCgdVeVgV

LC

LC

LC

++timesminus=Δ

++times+=Δ

++timesminus+=Δ

)(3

)(2

)(1 ( ) ( )

( )

( )CgdCCstCgdVeV

CgdCCstCstVeV

CgdCCstCgdVeVgV

LC

LC

LC

++times+=Δ

++timesminus=Δ

++times+minus=Δ

)(6

)(5

)(4

CstCgdVgVeVe

VVVVVV



2)()(

654321Q




Data Center

Positive Driving

Negative Driving

Black(+)

White(+)White(-)


Black(-)


Data Center

Positive Driving

Negative Driving

Black(+)

White(+)White(-)

Black(-)





VVVV2-level driving

high voltage

high voltage

Lowhigh voltage

Lowhigh voltage

Output range


DotColumnRowFrame

Vcom ACDC






















Analog Data Driver


Shift Register

pixel

Qi Qi+1Video

in

pixel



Video in

control

pixel

Qi+1 Qi+2


Samplecapacitor

hold capacitor








SIPO1 phase

SISO1 phase




Pixel1

Pixel2

Pixel3

Pixel4

Pixel5

Pixel6

Pixel7

Pixel8



SR

Video in






Driver IC


Sample

Hold

Buffer

Sample

Hold

Buffer

Sample

Hold

Buffer

Sample

Hold

Buffer

SR SR SR SR


Pixel1

Pixel2

Pixel3

Pixel4

Pixel5

Pixel6

Pixel7

Pixel8


DeMUX 12



Videoin


Driver


LAAT vs PAAT







Digital Data Driver






lowhighcost






AnalogDigital



Latch Signal

Polarity Signal

Analog Part

Digital Part

To LCD data line

CLKDIO1

Out1 Out2 Out3 Outn

DIO2

HoldReg

Sample Reg

SR

Buffer

LevelShifter

HoldReg

Sample Reg

SR

Buffer

LevelShifter

HoldReg

Sample Reg

SR

Buffer

LevelShifter

HoldReg

Sample Reg

SR

Buffer

LevelShifter

HoldReg

SR

Buffer

LevelShifter

sample reg


Dat

are

ceiv

er


Datain

Output buffers

Level Shifter



Data latch

CLK

DIO1

128 CLKs


128 CLKs

DIO2

P1 P2 P3 P130P129P128P4 P5 P131 P132 P133P127





Tst

POL

Odd outputs


Positive

Tst

Vcom


LD

1K

15P

1K

15P

1K

15P

1K

15P

1K

15P

High-Z High-Z

High-Z

(CLK1)



sharing hellipetc)



720

7

4201680x3WSXGA+7206424801920x3HDTV

4804321440x3WXGA

4141366x3WXGA

512

402

12

480

420

38431224019210 9

1400x3SXGA+

1600x3UXGA

2048x3QXGA











Horizontal period

Pixel frequency

Horizontal period

Pixel frequency




DA Converter









Idea DA Converter


1 2 011 2 12 2 2 2

n nin n n








1 2 011 2 1

2 2 2 2

2


refLSB N

b b bbV V L V B

VV

minus minusminus

⎛ ⎞= + + + + = times⎜ ⎟⎝ ⎠




















Offset Error



2-bit example

00( ) outoff

LSB

VE DAC V=






LSB LSB

V VEV V





Accuracy



error


removed










DA Converter









bull Glitches






Decoder-based

Binary-weighted

Thermometer-code

Hybrid



Decoder-Based DAC








Decoder-Based DAC






R

R

R

R

R

R

R

R

R

b0 b0

b1 b1

b2

b2

Vout

VRef

2N resistors

Bin = b22-1+b12-2+b02-3


















( 1) (2 3 )

tr tr tr tr tr tr

tr tr

R C R C N R C

N N R C


= + sdot

L











R

R

R

R

R

R

R

R

R

VRef

Vout

b2

b1

b0




Decoder-Based DAC



























3 2 1

1 2 33 2 1

2 4 8 2 2 2

Fout F ref ref In

In




= + + +LL

bull 4-bit example





















R-2R-based DAC


bull 4-bit example


11 1

_2 2 2

N Nref i R iF

R out F refi ii i


= =


sum sum













Current-mode DAC


ground potential

















across RF)









bull Glitches


















current sources












Examples of DAC 2





R-String DAC

R2

R2

R

R

R

R

R

R

R

b1b1

out

5

-19

b3b2b2 b3







ROM Decoder


Gamma Correction




Gamma Correction






Low noise






Output Buffer

DAC P

DAC N


OddOutput

EvenOutput

Gamma Voltage

(+)

Gamma Voltage

(-)

To data line

Rail to rail OP-AMP

-+

+-


Output Buffer

DAC P

negativebuffer


OddOutput

EvenOutput

Gamma Voltage

(+)

Gamma Voltage

(-)

To data line


PN type OP-AMP

DAC N

positivebuffer

+-

+-




Low deviation



Optimum OP AMP area



V1V2

+

-

Vss

Vdd

+

-+

-

Vout=Av(V1-V2)+

-





stage

High-gainstage

OutputBuffer


Bias Circuitry

Vout VoutrsquoV1V2





2




Hierarchy

Current to voltage

Current to voltage

voltage to current

voltage to current

conversion



(current mirror)





MOS diodeload


Class B (push-pull)

Currentstage

1stvoltagestage

2ndvoltagestage



Examples of Op-Amp





Design of Op Amp





1 Hand calculation









V-1005(L=1um)001(L=2um)

004(L=1um)001(L=2um)




Krsquo



symbol
















A(s)

F(s)

+

-ΣVin(s) Vout(s)

















need compensation




Z1 = gmIICC

CII gtgt CI CC



loop gain F(s)=1






and the RHP zero


C

m

C

mI

Cg

CgGB 2=cong

C

m

C

mI

m

II

mII

Cm

dsdsdsds

CmII

III

Cg

Cgz

Cg

Cgp

Cggggg

CgGGp

21

2

62

6

76421

))((

=cong

minus=

minuscong

++minus=

minuscong

Unit gain bandwidth






Cm

dsdsdsds

CmII

III

Cggggg

CgGGp

6

7642

1

))(( ++minus

=minus

cong








2

62 C

gCgp m

II

mII minus=

minuscong






VsCRsCgRV

sCRRV

sCRsCRgsV

CII

CmII

CII

II

CII

CIImout 1

)1(1

1

)1()( 66

+minusminus

=⎟⎟⎠

⎞⎜⎜⎝

⎛+

+⎟⎟⎠

⎞⎜⎜⎝

⎛+

minus=

Vrsquorsquo

Vout

VDD

CC

Vrsquo

++

--

M6

RII



IC1 IC2


VocOutput offset

between chip tochip




of gray m


Offset Cancellation

Voffset

VinVo=Vin+Voffset


Phase 1

Phase 2

Caz



Caz

Vo=Vin


+-

+ -

- +

- +

- +-+



Channel 384

Channel 383

Channel 382

Channel 381

Channel 4

Channel 3

Channel 2

Channel 1

Length

Height


Channel 420

Channel 419

Channel 418

Channel 417

Channel 4

Channel 3

Channel 2

Channel 1


Channel 480

Channel 479

Channel 478

Channel 477

Channel 4

Channel 3

Channel 2

Channel 1


resistor

Gammaresistor

Gammaresistor



TSMC HV Process




LCD Panel

Start pulse










dtdVCI times=

P = fdCloadVDD2

Turn on one clock




ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

clock

clock

Clock 2Clock 1

Clock 2Clock 1



Dual edge clocking

1 2 3 4

CK1XCK1CK2XCK2


Charge Sharing

To data line

DAC P


OddOutput

EvenOutput

OP

OPDAC NData

Data

Vgmama+

Vgmama-

-+

-+









CNS for Car

4~8mA

DSC Game PDA

2~3mA

05 ~ 2 mA

Mobile-phone


Large size panel









TV application


Outline









LCD TV Electronics

LCD Control Board


SDTV 720x480

cable


DCDC power




LCD Module

TTLLVDSTMDS

γ


OSD

Scaler

MCU

ADCAnalog

RGB

VideoDecoder

DigitalDVI

TMDSRx

De-interlace

Tuner

YC

SyncSep

Compositevideo

AntennaRF in

YCbCr

YPbPr



Digital TV System


MPEG2Decoder PODCI

32MB DDRSDRAM

Scaler IC







RESETRESET


SWITCHSWITCH



DiodesDiodes

LCDLCDDRIVERDRIVER


MICONMICON



INVERTERINVERTER


LCDLCDPANELPANEL

POWERAMPPOWERAMP




LA7585LA7585LA758788LA758788

LA7565LA7565


LA426061LA426061LA426570LA426570LA428082LA428082


LA7221LA7221









LA76818LA76818LA863228LA863228

FSS140132134FSS140132134CPH33043414CPH33043414


CPH5506CPH5506

LA426642674268LA426642674268LA427642774278LA427642774278








Black Insertion





DAC

γminus18R1 string

γminus22R2 string

γminus26R3 string

switch


Vref [118] Vout

8-bit Data


V0~V255




example



Over-8 bit data







Gn-1

Gn

Gray Level



Actual Response

Gn-1

Gn

Gray Level


Gn

Overdrive Response

Voltage by Driver







Overdrive Circuits

Memory

Lookup Table

Control ckts

Data

Dn

Dn+1

Ctrl

addressReadWrite

Datarsquo




ight

ness

Normal image

brig

htne

ss

bright imagebr

ight

ness


Other Technologies






LCD TV Trends


Size

BrightnessCR

Response Time

LCD Monitor

15-20rdquo

250400

25~16ms


Resolution XGA~UXGA

2002~2003

LCD TV


400~550500~700 gt550gt2k

25~16ms 16~12ms lt 8 ms

160160 176176


2004~2008

challenge

COST


Outline








TFTTFT



Controller025 μm

Sourcedriver05 μm


Gatedriver

06 μm HV



HV

Single chipHV

4 Chip TCPCOF Type

2 Chip COGCOF Type

1 Chip COG Type


HitachiSamsung

奇景聯詠

智寶科技







PWR SRAMGAMA64

APRSRAM

Gate Driver

PWR



18

64

18


Gate control

PowerSupplyCircuit

TimingGenerator

OSCSystem Interface


Indexregister

Controlregister

graylevelgenerator




Gammaadjusting

Addresscounter

VGHVGL

VgoffGVDDVGS

AVDD

18

G17

7G

176

G17

5 G

2G

1G

0

S396

S395

S394

S3 S2 S1

SPIC

ontrol

RW

Data

VDD3VDD

Latch circuitand

Vcom


Voltage Setting


VDD(20V ~ 33V)


VCI(25V ~ 33V)

BT2-0

BT2-0

VRH3-0

VREG2OUT

VCOM4-0

VGH(+9 ~ +165V)

AVDD(+35~ +55V)


VCL

VgoffH (to -50V)


VGL (-165 to -9V)

-1 times-1 times

VREG1OUT

VDV4-0

VCI1

VC2-0

VSS(0V)

VC3=1VRL3-0

GVDD(+30~ +50V)

VC3=0VRL3-0


Voltage Waveforms


sn(source output)

VCOM

Gn (Gate output)

VGH(+9 ~ +165V)


VgoffH (~to -50V)


GVDD(+30~ +50V)VDD(20V ~ 33V)

AVDD(+35~ +55V)

VSS(0V)






OVcomOUT


OVREG2OUT


OVREG1OUT


IOREGP





IOVCI



IOAVDD



-VDD

DescriptionIOSymbol




OVgoffL


OVgoffH



voltage

OVgoffOUT


IVgoff


higher than -150 V

OVGL



OVGH



OVcomL


OVcomH



IVcomR

DescriptionIOSymbol



mA2015-IVCI



by mode


Outputs


Outputs


Outputs





V5-3GVDD

V-5--16VGOFF

V-9--165VGL

V165-9VGH


V55-35AVDD

LCD Supply Voltage







Vcom


Vcom



Vgoff






V595583571VREG1OUT









VCI2

VCI VCI

VDDVSSVCIVSS

C7

int

VGL

VGH

C1VGH

C22P

C16


C11+

C1 5REGP

VCL

C31MVCI3

C22M

C12-C12+

C11-Vci1

VCIOUT

VCOMR

VGOFFOUT

VGOFFL

C20

C19

VCOMOUT

VCOMH

VREG1OUT

VREG2OUT

C 21

C 11


(Vgoffadjustment)


adjustment)

VcomHadjustment

circuit


circuit

GVDDoutput

amplifier

VcomHoutput

amplifier

VcomLoutput

amplifier

VgoffHoutput


amplifier


circuit

C12

C9GVDD

VGOFFH

C10

Voltageadjustment

circuitRegulator

Charge-pump

circuit 1

C23PC23M

C21M

Charge-pump

circuit 2

C21P

C31P Charge-pump

circuit 3

C41-Vci4

C41+ Charge-pump

circuit 4

REGN

C14C17

AVDD

C18

C4

C3

C2

C6

VC1

C5

C3


AVDD

VGL

GVDD

VCOML





GRAMMSB LSB

PKP00PKP01PKP02

PKP10PKP11PKP12

PKP20PKP21PKP22

PKP30PKP31PKP32

PKP40PKP41PKP42

PKP50PKP51PKP52

PRP00PRP01PRP02

PRP10PRP11PRP12

VRP00VRP01VRP02

VRP10VRP11VRP12

VRP03

VRP13VRP14

PKN00PKN01PKN02

PKN10PKN11PKN12

PKN20PKN21PKN22

PKN30PKN31PKN32

PKN40PKN41PKN42

PKN50PKN51PKN52

PRN00PRN01PRN02

PRN10PRN11PRN12

VRN00VRN01VRN02

VRN10VRN11VRN12

VRN03

VRN13VRN14



GrayscaleAm plifier


ltRgt

LCD driver

64 grayscalecontrol

ltG gt

LCD driver

64 grayscalecontrol

ltBgt

LCD driver

64

V1

V0

V63

6 6 6

R G BLCD


Scan Mode

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176


11


01

G176 G175 G174 G173 hellip G4 G3 G2 G110

G1 G2 G3 G4 hellip G173 G174 G175 G17600

Scan ModeGSSM

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176


A

B

C

D

A

B

C

D






33 3 3 3 54333








G V D D

V G S


V I N P N 0

V I N P N 1

V I N P N 2

V I N P N 3

V I N P N 4

V I N P N 5

V I N P N 6

V I N P N 7

V 0

V 6 3

V 6 2

V 5 5

V 4 3

V 2 0

V 8

V 1V 2V 3

V 9

V 2 1

V 4 4

V 5 6V 5 7





Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge





8080Dummy Pad1195239742


Pad sizeum


UnitSize

Pad nameItems









Technology






25532V Process










Gat

e D

river

IC


Gat

e D

river

IC

T-Con

LTPS TFT-LCD


Source Driver IC

Gat

e D

river

IC

De-MUX






Outline









Digital vs Analog




TTL vs LVDS





XGA 325M (2 ports)

67M ( 1 port)

67M (2 ports)

SXGA 54M (2 ports)

54M (2 ports)

108M (2 ports)

Frequency

UXGA - 81M 162M LCD




6-bit ~80 ~60 ~50



RSDS Definition




8 Bit RGB RSDS Data

Start pulseR0 R1

R2 R3

R4 R5

G0 G1

G2 G3G4 G5

B0 B1

B2 B3

B4 B5

Invalid data

Invalid data

Invalid data

R6 R7

G6 G7

B6 B7



Single-end

FrontBack








Mini-LVDS

Data Bus Structure


Mini-LVDS

6 bit data 5 pairs


8 bit data 6 pairs

Mini-LVDS






TQFP100


RSDS vs Mini-LVDS













PPDSRSDSParameter



PPDSTM








PPDS Protocol





10-bit(1024灰階)


Memo



Vcc

GND

Vout

N2

P2

Vcc

GND

N1

P1

Vin

N3

P3

Vcc

Vdd

P4

Vdd

VccN4

Vdd

GND

M1

M2

INPUT

M3

Vdd

GND

M4

M5

M6

INPUT

OUTPUT

Latch Type


US 4486670INTERSIL


Output Buffer

IN OUT



TSMC HV Process




Source Web of TSMC





Vd 1

CLC

Vpixel

CstTFT

Vd 2 Vd 3Vg N-2

Vg N-1

Vg N

VdN-2

VdNVdN-1

VdN+1


~10us ~10us

1 frame ~16ms

Two-Line Scanning




Dual Driving


gt 40ldquo

RefIDW 00rsquo p167


Gate Driver Design







bull Cst on gate

CstClc

Cgd

Cds

Scan line n

Scan line n-1

Vcom

3-level

Vghl Vgc

Pixel voltage

V1V2

V3321 VVV Δ+Δ=Δ





+++times=Δ 1

CdsCgdCstClcCstVgcV

+++times=Δ 2

CdsCgdCstClcCgdVgcV

+++times=Δ 3


CgdCstCgdVghlVgc+

times= then

778205040

05025

4710504040


=+

=+

timesΔ=

=++

times=Δ

gds

gdghlgc

gd

CCC

VV

VV



Data Center

Positive Driving

Negative Driving


Black(+)

White(+)

Black(-)


Positive Driving

Negative Driving


Final Vcom

Positive Driving

Negative Driving


Black(+)

White(+)

Black(-)

White(-)

Black(+)

White(+)

Black(-)

White(-)


Cs on gate

CstClc

Cgd

Cds

Scan line n

Scan line n-1

Vcom

Negative Polarity

GN-1(+)

VP

V1V2

V3


Positive Polarity

V4

V5

V6

GN(-)

GN-1(-)

GN(+)

VP

Vcom

Vblack(+)

Vblack(-)

Vg Ve+

Ve-Vg






( ) ( )

( )

( )CgdCCstCgdVeV

CgdCCstCstVeV

CgdCCstCgdVeVgV

LC

LC

LC

++timesminus=Δ

++times+=Δ

++timesminus+=Δ

)(3

)(2

)(1 ( ) ( )

( )

( )CgdCCstCgdVeV

CgdCCstCstVeV

CgdCCstCgdVeVgV

LC

LC

LC

++times+=Δ

++timesminus=Δ

++times+minus=Δ

)(6

)(5

)(4

CstCgdVgVeVe

VVVVVV



2)()(

654321Q




Data Center

Positive Driving

Negative Driving

Black(+)

White(+)White(-)


Black(-)


Data Center

Positive Driving

Negative Driving

Black(+)

White(+)White(-)

Black(-)





VVVV2-level driving

high voltage

high voltage

Lowhigh voltage

Lowhigh voltage

Output range


DotColumnRowFrame

Vcom ACDC






















Analog Data Driver


Shift Register

pixel

Qi Qi+1Video

in

pixel



Video in

control

pixel

Qi+1 Qi+2


Samplecapacitor

hold capacitor








SIPO1 phase

SISO1 phase




Pixel1

Pixel2

Pixel3

Pixel4

Pixel5

Pixel6

Pixel7

Pixel8



SR

Video in






Driver IC


Sample

Hold

Buffer

Sample

Hold

Buffer

Sample

Hold

Buffer

Sample

Hold

Buffer

SR SR SR SR


Pixel1

Pixel2

Pixel3

Pixel4

Pixel5

Pixel6

Pixel7

Pixel8


DeMUX 12



Videoin


Driver


LAAT vs PAAT







Digital Data Driver






lowhighcost






AnalogDigital



Latch Signal

Polarity Signal

Analog Part

Digital Part

To LCD data line

CLKDIO1

Out1 Out2 Out3 Outn

DIO2

HoldReg

Sample Reg

SR

Buffer

LevelShifter

HoldReg

Sample Reg

SR

Buffer

LevelShifter

HoldReg

Sample Reg

SR

Buffer

LevelShifter

HoldReg

Sample Reg

SR

Buffer

LevelShifter

HoldReg

SR

Buffer

LevelShifter

sample reg


Dat

are

ceiv

er


Datain

Output buffers

Level Shifter



Data latch

CLK

DIO1

128 CLKs


128 CLKs

DIO2

P1 P2 P3 P130P129P128P4 P5 P131 P132 P133P127





Tst

POL

Odd outputs


Positive

Tst

Vcom


LD

1K

15P

1K

15P

1K

15P

1K

15P

1K

15P

High-Z High-Z

High-Z

(CLK1)



sharing hellipetc)



720

7

4201680x3WSXGA+7206424801920x3HDTV

4804321440x3WXGA

4141366x3WXGA

512

402

12

480

420

38431224019210 9

1400x3SXGA+

1600x3UXGA

2048x3QXGA











Horizontal period

Pixel frequency

Horizontal period

Pixel frequency




DA Converter









Idea DA Converter


1 2 011 2 12 2 2 2

n nin n n








1 2 011 2 1

2 2 2 2

2


refLSB N

b b bbV V L V B

VV

minus minusminus

⎛ ⎞= + + + + = times⎜ ⎟⎝ ⎠




















Offset Error



2-bit example

00( ) outoff

LSB

VE DAC V=






LSB LSB

V VEV V





Accuracy



error


removed










DA Converter









bull Glitches






Decoder-based

Binary-weighted

Thermometer-code

Hybrid



Decoder-Based DAC








Decoder-Based DAC






R

R

R

R

R

R

R

R

R

b0 b0

b1 b1

b2

b2

Vout

VRef

2N resistors

Bin = b22-1+b12-2+b02-3


















( 1) (2 3 )

tr tr tr tr tr tr

tr tr

R C R C N R C

N N R C


= + sdot

L











R

R

R

R

R

R

R

R

R

VRef

Vout

b2

b1

b0




Decoder-Based DAC



























3 2 1

1 2 33 2 1

2 4 8 2 2 2

Fout F ref ref In

In




= + + +LL

bull 4-bit example





















R-2R-based DAC


bull 4-bit example


11 1

_2 2 2

N Nref i R iF

R out F refi ii i


= =


sum sum













Current-mode DAC


ground potential

















across RF)









bull Glitches


















current sources












Examples of DAC 2





R-String DAC

R2

R2

R

R

R

R

R

R

R

b1b1

out

5

-19

b3b2b2 b3







ROM Decoder


Gamma Correction




Gamma Correction






Low noise






Output Buffer

DAC P

DAC N


OddOutput

EvenOutput

Gamma Voltage

(+)

Gamma Voltage

(-)

To data line

Rail to rail OP-AMP

-+

+-


Output Buffer

DAC P

negativebuffer


OddOutput

EvenOutput

Gamma Voltage

(+)

Gamma Voltage

(-)

To data line


PN type OP-AMP

DAC N

positivebuffer

+-

+-




Low deviation



Optimum OP AMP area



V1V2

+

-

Vss

Vdd

+

-+

-

Vout=Av(V1-V2)+

-





stage

High-gainstage

OutputBuffer


Bias Circuitry

Vout VoutrsquoV1V2





2




Hierarchy

Current to voltage

Current to voltage

voltage to current

voltage to current

conversion



(current mirror)





MOS diodeload


Class B (push-pull)

Currentstage

1stvoltagestage

2ndvoltagestage



Examples of Op-Amp





Design of Op Amp





1 Hand calculation









V-1005(L=1um)001(L=2um)

004(L=1um)001(L=2um)




Krsquo



symbol
















A(s)

F(s)

+

-ΣVin(s) Vout(s)

















need compensation




Z1 = gmIICC

CII gtgt CI CC



loop gain F(s)=1






and the RHP zero


C

m

C

mI

Cg

CgGB 2=cong

C

m

C

mI

m

II

mII

Cm

dsdsdsds

CmII

III

Cg

Cgz

Cg

Cgp

Cggggg

CgGGp

21

2

62

6

76421

))((

=cong

minus=

minuscong

++minus=

minuscong

Unit gain bandwidth






Cm

dsdsdsds

CmII

III

Cggggg

CgGGp

6

7642

1

))(( ++minus

=minus

cong








2

62 C

gCgp m

II

mII minus=

minuscong






VsCRsCgRV

sCRRV

sCRsCRgsV

CII

CmII

CII

II

CII

CIImout 1

)1(1

1

)1()( 66

+minusminus

=⎟⎟⎠

⎞⎜⎜⎝

⎛+

+⎟⎟⎠

⎞⎜⎜⎝

⎛+

minus=

Vrsquorsquo

Vout

VDD

CC

Vrsquo

++

--

M6

RII



IC1 IC2


VocOutput offset

between chip tochip




of gray m


Offset Cancellation

Voffset

VinVo=Vin+Voffset


Phase 1

Phase 2

Caz



Caz

Vo=Vin


+-

+ -

- +

- +

- +-+



Channel 384

Channel 383

Channel 382

Channel 381

Channel 4

Channel 3

Channel 2

Channel 1

Length

Height


Channel 420

Channel 419

Channel 418

Channel 417

Channel 4

Channel 3

Channel 2

Channel 1


Channel 480

Channel 479

Channel 478

Channel 477

Channel 4

Channel 3

Channel 2

Channel 1


resistor

Gammaresistor

Gammaresistor



TSMC HV Process




LCD Panel

Start pulse










dtdVCI times=

P = fdCloadVDD2

Turn on one clock




ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

clock

clock

Clock 2Clock 1

Clock 2Clock 1



Dual edge clocking

1 2 3 4

CK1XCK1CK2XCK2


Charge Sharing

To data line

DAC P


OddOutput

EvenOutput

OP

OPDAC NData

Data

Vgmama+

Vgmama-

-+

-+









CNS for Car

4~8mA

DSC Game PDA

2~3mA

05 ~ 2 mA

Mobile-phone


Large size panel









TV application


Outline









LCD TV Electronics

LCD Control Board


SDTV 720x480

cable


DCDC power




LCD Module

TTLLVDSTMDS

γ


OSD

Scaler

MCU

ADCAnalog

RGB

VideoDecoder

DigitalDVI

TMDSRx

De-interlace

Tuner

YC

SyncSep

Compositevideo

AntennaRF in

YCbCr

YPbPr



Digital TV System


MPEG2Decoder PODCI

32MB DDRSDRAM

Scaler IC







RESETRESET


SWITCHSWITCH



DiodesDiodes

LCDLCDDRIVERDRIVER


MICONMICON



INVERTERINVERTER


LCDLCDPANELPANEL

POWERAMPPOWERAMP




LA7585LA7585LA758788LA758788

LA7565LA7565


LA426061LA426061LA426570LA426570LA428082LA428082


LA7221LA7221









LA76818LA76818LA863228LA863228

FSS140132134FSS140132134CPH33043414CPH33043414


CPH5506CPH5506

LA426642674268LA426642674268LA427642774278LA427642774278








Black Insertion





DAC

γminus18R1 string

γminus22R2 string

γminus26R3 string

switch


Vref [118] Vout

8-bit Data


V0~V255




example



Over-8 bit data







Gn-1

Gn

Gray Level



Actual Response

Gn-1

Gn

Gray Level


Gn

Overdrive Response

Voltage by Driver







Overdrive Circuits

Memory

Lookup Table

Control ckts

Data

Dn

Dn+1

Ctrl

addressReadWrite

Datarsquo




ight

ness

Normal image

brig

htne

ss

bright imagebr

ight

ness


Other Technologies






LCD TV Trends


Size

BrightnessCR

Response Time

LCD Monitor

15-20rdquo

250400

25~16ms


Resolution XGA~UXGA

2002~2003

LCD TV


400~550500~700 gt550gt2k

25~16ms 16~12ms lt 8 ms

160160 176176


2004~2008

challenge

COST


Outline








TFTTFT



Controller025 μm

Sourcedriver05 μm


Gatedriver

06 μm HV



HV

Single chipHV

4 Chip TCPCOF Type

2 Chip COGCOF Type

1 Chip COG Type


HitachiSamsung

奇景聯詠

智寶科技







PWR SRAMGAMA64

APRSRAM

Gate Driver

PWR



18

64

18


Gate control

PowerSupplyCircuit

TimingGenerator

OSCSystem Interface


Indexregister

Controlregister

graylevelgenerator




Gammaadjusting

Addresscounter

VGHVGL

VgoffGVDDVGS

AVDD

18

G17

7G

176

G17

5 G

2G

1G

0

S396

S395

S394

S3 S2 S1

SPIC

ontrol

RW

Data

VDD3VDD

Latch circuitand

Vcom


Voltage Setting


VDD(20V ~ 33V)


VCI(25V ~ 33V)

BT2-0

BT2-0

VRH3-0

VREG2OUT

VCOM4-0

VGH(+9 ~ +165V)

AVDD(+35~ +55V)


VCL

VgoffH (to -50V)


VGL (-165 to -9V)

-1 times-1 times

VREG1OUT

VDV4-0

VCI1

VC2-0

VSS(0V)

VC3=1VRL3-0

GVDD(+30~ +50V)

VC3=0VRL3-0


Voltage Waveforms


sn(source output)

VCOM

Gn (Gate output)

VGH(+9 ~ +165V)


VgoffH (~to -50V)


GVDD(+30~ +50V)VDD(20V ~ 33V)

AVDD(+35~ +55V)

VSS(0V)






OVcomOUT


OVREG2OUT


OVREG1OUT


IOREGP





IOVCI



IOAVDD



-VDD

DescriptionIOSymbol




OVgoffL


OVgoffH



voltage

OVgoffOUT


IVgoff


higher than -150 V

OVGL



OVGH



OVcomL


OVcomH



IVcomR

DescriptionIOSymbol



mA2015-IVCI



by mode


Outputs


Outputs


Outputs





V5-3GVDD

V-5--16VGOFF

V-9--165VGL

V165-9VGH


V55-35AVDD

LCD Supply Voltage







Vcom


Vcom



Vgoff






V595583571VREG1OUT









VCI2

VCI VCI

VDDVSSVCIVSS

C7

int

VGL

VGH

C1VGH

C22P

C16


C11+

C1 5REGP

VCL

C31MVCI3

C22M

C12-C12+

C11-Vci1

VCIOUT

VCOMR

VGOFFOUT

VGOFFL

C20

C19

VCOMOUT

VCOMH

VREG1OUT

VREG2OUT

C 21

C 11


(Vgoffadjustment)


adjustment)

VcomHadjustment

circuit


circuit

GVDDoutput

amplifier

VcomHoutput

amplifier

VcomLoutput

amplifier

VgoffHoutput


amplifier


circuit

C12

C9GVDD

VGOFFH

C10

Voltageadjustment

circuitRegulator

Charge-pump

circuit 1

C23PC23M

C21M

Charge-pump

circuit 2

C21P

C31P Charge-pump

circuit 3

C41-Vci4

C41+ Charge-pump

circuit 4

REGN

C14C17

AVDD

C18

C4

C3

C2

C6

VC1

C5

C3


AVDD

VGL

GVDD

VCOML





GRAMMSB LSB

PKP00PKP01PKP02

PKP10PKP11PKP12

PKP20PKP21PKP22

PKP30PKP31PKP32

PKP40PKP41PKP42

PKP50PKP51PKP52

PRP00PRP01PRP02

PRP10PRP11PRP12

VRP00VRP01VRP02

VRP10VRP11VRP12

VRP03

VRP13VRP14

PKN00PKN01PKN02

PKN10PKN11PKN12

PKN20PKN21PKN22

PKN30PKN31PKN32

PKN40PKN41PKN42

PKN50PKN51PKN52

PRN00PRN01PRN02

PRN10PRN11PRN12

VRN00VRN01VRN02

VRN10VRN11VRN12

VRN03

VRN13VRN14



GrayscaleAm plifier


ltRgt

LCD driver

64 grayscalecontrol

ltG gt

LCD driver

64 grayscalecontrol

ltBgt

LCD driver

64

V1

V0

V63

6 6 6

R G BLCD


Scan Mode

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176


11


01

G176 G175 G174 G173 hellip G4 G3 G2 G110

G1 G2 G3 G4 hellip G173 G174 G175 G17600

Scan ModeGSSM

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176


A

B

C

D

A

B

C

D






33 3 3 3 54333








G V D D

V G S


V I N P N 0

V I N P N 1

V I N P N 2

V I N P N 3

V I N P N 4

V I N P N 5

V I N P N 6

V I N P N 7

V 0

V 6 3

V 6 2

V 5 5

V 4 3

V 2 0

V 8

V 1V 2V 3

V 9

V 2 1

V 4 4

V 5 6V 5 7





Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge





8080Dummy Pad1195239742


Pad sizeum


UnitSize

Pad nameItems









Technology






25532V Process










Gat

e D

river

IC


Gat

e D

river

IC

T-Con

LTPS TFT-LCD


Source Driver IC

Gat

e D

river

IC

De-MUX






Outline









Digital vs Analog




TTL vs LVDS





XGA 325M (2 ports)

67M ( 1 port)

67M (2 ports)

SXGA 54M (2 ports)

54M (2 ports)

108M (2 ports)

Frequency

UXGA - 81M 162M LCD




6-bit ~80 ~60 ~50



RSDS Definition




8 Bit RGB RSDS Data

Start pulseR0 R1

R2 R3

R4 R5

G0 G1

G2 G3G4 G5

B0 B1

B2 B3

B4 B5

Invalid data

Invalid data

Invalid data

R6 R7

G6 G7

B6 B7



Single-end

FrontBack








Mini-LVDS

Data Bus Structure


Mini-LVDS

6 bit data 5 pairs


8 bit data 6 pairs

Mini-LVDS






TQFP100


RSDS vs Mini-LVDS













PPDSRSDSParameter



PPDSTM








PPDS Protocol





10-bit(1024灰階)


Memo





Vd 1

CLC

Vpixel

CstTFT

Vd 2 Vd 3Vg N-2

Vg N-1

Vg N

VdN-2

VdNVdN-1

VdN+1


~10us ~10us

1 frame ~16ms

Two-Line Scanning




Dual Driving


gt 40ldquo

RefIDW 00rsquo p167


Gate Driver Design







bull Cst on gate

CstClc

Cgd

Cds

Scan line n

Scan line n-1

Vcom

3-level

Vghl Vgc

Pixel voltage

V1V2

V3321 VVV Δ+Δ=Δ





+++times=Δ 1

CdsCgdCstClcCstVgcV

+++times=Δ 2

CdsCgdCstClcCgdVgcV

+++times=Δ 3


CgdCstCgdVghlVgc+

times= then

778205040

05025

4710504040


=+

=+

timesΔ=

=++

times=Δ

gds

gdghlgc

gd

CCC

VV

VV



Data Center

Positive Driving

Negative Driving


Black(+)

White(+)

Black(-)


Positive Driving

Negative Driving


Final Vcom

Positive Driving

Negative Driving


Black(+)

White(+)

Black(-)

White(-)

Black(+)

White(+)

Black(-)

White(-)


Cs on gate

CstClc

Cgd

Cds

Scan line n

Scan line n-1

Vcom

Negative Polarity

GN-1(+)

VP

V1V2

V3


Positive Polarity

V4

V5

V6

GN(-)

GN-1(-)

GN(+)

VP

Vcom

Vblack(+)

Vblack(-)

Vg Ve+

Ve-Vg






( ) ( )

( )

( )CgdCCstCgdVeV

CgdCCstCstVeV

CgdCCstCgdVeVgV

LC

LC

LC

++timesminus=Δ

++times+=Δ

++timesminus+=Δ

)(3

)(2

)(1 ( ) ( )

( )

( )CgdCCstCgdVeV

CgdCCstCstVeV

CgdCCstCgdVeVgV

LC

LC

LC

++times+=Δ

++timesminus=Δ

++times+minus=Δ

)(6

)(5

)(4

CstCgdVgVeVe

VVVVVV



2)()(

654321Q




Data Center

Positive Driving

Negative Driving

Black(+)

White(+)White(-)


Black(-)


Data Center

Positive Driving

Negative Driving

Black(+)

White(+)White(-)

Black(-)





VVVV2-level driving

high voltage

high voltage

Lowhigh voltage

Lowhigh voltage

Output range


DotColumnRowFrame

Vcom ACDC






















Analog Data Driver


Shift Register

pixel

Qi Qi+1Video

in

pixel



Video in

control

pixel

Qi+1 Qi+2


Samplecapacitor

hold capacitor








SIPO1 phase

SISO1 phase




Pixel1

Pixel2

Pixel3

Pixel4

Pixel5

Pixel6

Pixel7

Pixel8



SR

Video in






Driver IC


Sample

Hold

Buffer

Sample

Hold

Buffer

Sample

Hold

Buffer

Sample

Hold

Buffer

SR SR SR SR


Pixel1

Pixel2

Pixel3

Pixel4

Pixel5

Pixel6

Pixel7

Pixel8


DeMUX 12



Videoin


Driver


LAAT vs PAAT







Digital Data Driver






lowhighcost






AnalogDigital



Latch Signal

Polarity Signal

Analog Part

Digital Part

To LCD data line

CLKDIO1

Out1 Out2 Out3 Outn

DIO2

HoldReg

Sample Reg

SR

Buffer

LevelShifter

HoldReg

Sample Reg

SR

Buffer

LevelShifter

HoldReg

Sample Reg

SR

Buffer

LevelShifter

HoldReg

Sample Reg

SR

Buffer

LevelShifter

HoldReg

SR

Buffer

LevelShifter

sample reg


Dat

are

ceiv

er


Datain

Output buffers

Level Shifter



Data latch

CLK

DIO1

128 CLKs


128 CLKs

DIO2

P1 P2 P3 P130P129P128P4 P5 P131 P132 P133P127





Tst

POL

Odd outputs


Positive

Tst

Vcom


LD

1K

15P

1K

15P

1K

15P

1K

15P

1K

15P

High-Z High-Z

High-Z

(CLK1)



sharing hellipetc)



720

7

4201680x3WSXGA+7206424801920x3HDTV

4804321440x3WXGA

4141366x3WXGA

512

402

12

480

420

38431224019210 9

1400x3SXGA+

1600x3UXGA

2048x3QXGA











Horizontal period

Pixel frequency

Horizontal period

Pixel frequency




DA Converter









Idea DA Converter


1 2 011 2 12 2 2 2

n nin n n








1 2 011 2 1

2 2 2 2

2


refLSB N

b b bbV V L V B

VV

minus minusminus

⎛ ⎞= + + + + = times⎜ ⎟⎝ ⎠




















Offset Error



2-bit example

00( ) outoff

LSB

VE DAC V=






LSB LSB

V VEV V





Accuracy



error


removed










DA Converter









bull Glitches






Decoder-based

Binary-weighted

Thermometer-code

Hybrid



Decoder-Based DAC








Decoder-Based DAC






R

R

R

R

R

R

R

R

R

b0 b0

b1 b1

b2

b2

Vout

VRef

2N resistors

Bin = b22-1+b12-2+b02-3


















( 1) (2 3 )

tr tr tr tr tr tr

tr tr

R C R C N R C

N N R C


= + sdot

L











R

R

R

R

R

R

R

R

R

VRef

Vout

b2

b1

b0




Decoder-Based DAC



























3 2 1

1 2 33 2 1

2 4 8 2 2 2

Fout F ref ref In

In




= + + +LL

bull 4-bit example





















R-2R-based DAC


bull 4-bit example


11 1

_2 2 2

N Nref i R iF

R out F refi ii i


= =


sum sum













Current-mode DAC


ground potential

















across RF)









bull Glitches


















current sources












Examples of DAC 2





R-String DAC

R2

R2

R

R

R

R

R

R

R

b1b1

out

5

-19

b3b2b2 b3







ROM Decoder


Gamma Correction




Gamma Correction






Low noise






Output Buffer

DAC P

DAC N


OddOutput

EvenOutput

Gamma Voltage

(+)

Gamma Voltage

(-)

To data line

Rail to rail OP-AMP

-+

+-


Output Buffer

DAC P

negativebuffer


OddOutput

EvenOutput

Gamma Voltage

(+)

Gamma Voltage

(-)

To data line


PN type OP-AMP

DAC N

positivebuffer

+-

+-




Low deviation



Optimum OP AMP area



V1V2

+

-

Vss

Vdd

+

-+

-

Vout=Av(V1-V2)+

-





stage

High-gainstage

OutputBuffer


Bias Circuitry

Vout VoutrsquoV1V2





2




Hierarchy

Current to voltage

Current to voltage

voltage to current

voltage to current

conversion



(current mirror)





MOS diodeload


Class B (push-pull)

Currentstage

1stvoltagestage

2ndvoltagestage



Examples of Op-Amp





Design of Op Amp





1 Hand calculation









V-1005(L=1um)001(L=2um)

004(L=1um)001(L=2um)




Krsquo



symbol
















A(s)

F(s)

+

-ΣVin(s) Vout(s)

















need compensation




Z1 = gmIICC

CII gtgt CI CC



loop gain F(s)=1






and the RHP zero


C

m

C

mI

Cg

CgGB 2=cong

C

m

C

mI

m

II

mII

Cm

dsdsdsds

CmII

III

Cg

Cgz

Cg

Cgp

Cggggg

CgGGp

21

2

62

6

76421

))((

=cong

minus=

minuscong

++minus=

minuscong

Unit gain bandwidth






Cm

dsdsdsds

CmII

III

Cggggg

CgGGp

6

7642

1

))(( ++minus

=minus

cong








2

62 C

gCgp m

II

mII minus=

minuscong






VsCRsCgRV

sCRRV

sCRsCRgsV

CII

CmII

CII

II

CII

CIImout 1

)1(1

1

)1()( 66

+minusminus

=⎟⎟⎠

⎞⎜⎜⎝

⎛+

+⎟⎟⎠

⎞⎜⎜⎝

⎛+

minus=

Vrsquorsquo

Vout

VDD

CC

Vrsquo

++

--

M6

RII



IC1 IC2


VocOutput offset

between chip tochip




of gray m


Offset Cancellation

Voffset

VinVo=Vin+Voffset


Phase 1

Phase 2

Caz



Caz

Vo=Vin


+-

+ -

- +

- +

- +-+



Channel 384

Channel 383

Channel 382

Channel 381

Channel 4

Channel 3

Channel 2

Channel 1

Length

Height


Channel 420

Channel 419

Channel 418

Channel 417

Channel 4

Channel 3

Channel 2

Channel 1


Channel 480

Channel 479

Channel 478

Channel 477

Channel 4

Channel 3

Channel 2

Channel 1


resistor

Gammaresistor

Gammaresistor



TSMC HV Process




LCD Panel

Start pulse










dtdVCI times=

P = fdCloadVDD2

Turn on one clock




ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

clock

clock

Clock 2Clock 1

Clock 2Clock 1



Dual edge clocking

1 2 3 4

CK1XCK1CK2XCK2


Charge Sharing

To data line

DAC P


OddOutput

EvenOutput

OP

OPDAC NData

Data

Vgmama+

Vgmama-

-+

-+









CNS for Car

4~8mA

DSC Game PDA

2~3mA

05 ~ 2 mA

Mobile-phone


Large size panel









TV application


Outline









LCD TV Electronics

LCD Control Board


SDTV 720x480

cable


DCDC power




LCD Module

TTLLVDSTMDS

γ


OSD

Scaler

MCU

ADCAnalog

RGB

VideoDecoder

DigitalDVI

TMDSRx

De-interlace

Tuner

YC

SyncSep

Compositevideo

AntennaRF in

YCbCr

YPbPr



Digital TV System


MPEG2Decoder PODCI

32MB DDRSDRAM

Scaler IC







RESETRESET


SWITCHSWITCH



DiodesDiodes

LCDLCDDRIVERDRIVER


MICONMICON



INVERTERINVERTER


LCDLCDPANELPANEL

POWERAMPPOWERAMP




LA7585LA7585LA758788LA758788

LA7565LA7565


LA426061LA426061LA426570LA426570LA428082LA428082


LA7221LA7221









LA76818LA76818LA863228LA863228

FSS140132134FSS140132134CPH33043414CPH33043414


CPH5506CPH5506

LA426642674268LA426642674268LA427642774278LA427642774278








Black Insertion





DAC

γminus18R1 string

γminus22R2 string

γminus26R3 string

switch


Vref [118] Vout

8-bit Data


V0~V255




example



Over-8 bit data







Gn-1

Gn

Gray Level



Actual Response

Gn-1

Gn

Gray Level


Gn

Overdrive Response

Voltage by Driver







Overdrive Circuits

Memory

Lookup Table

Control ckts

Data

Dn

Dn+1

Ctrl

addressReadWrite

Datarsquo




ight

ness

Normal image

brig

htne

ss

bright imagebr

ight

ness


Other Technologies






LCD TV Trends


Size

BrightnessCR

Response Time

LCD Monitor

15-20rdquo

250400

25~16ms


Resolution XGA~UXGA

2002~2003

LCD TV


400~550500~700 gt550gt2k

25~16ms 16~12ms lt 8 ms

160160 176176


2004~2008

challenge

COST


Outline








TFTTFT



Controller025 μm

Sourcedriver05 μm


Gatedriver

06 μm HV



HV

Single chipHV

4 Chip TCPCOF Type

2 Chip COGCOF Type

1 Chip COG Type


HitachiSamsung

奇景聯詠

智寶科技







PWR SRAMGAMA64

APRSRAM

Gate Driver

PWR



18

64

18


Gate control

PowerSupplyCircuit

TimingGenerator

OSCSystem Interface


Indexregister

Controlregister

graylevelgenerator




Gammaadjusting

Addresscounter

VGHVGL

VgoffGVDDVGS

AVDD

18

G17

7G

176

G17

5 G

2G

1G

0

S396

S395

S394

S3 S2 S1

SPIC

ontrol

RW

Data

VDD3VDD

Latch circuitand

Vcom


Voltage Setting


VDD(20V ~ 33V)


VCI(25V ~ 33V)

BT2-0

BT2-0

VRH3-0

VREG2OUT

VCOM4-0

VGH(+9 ~ +165V)

AVDD(+35~ +55V)


VCL

VgoffH (to -50V)


VGL (-165 to -9V)

-1 times-1 times

VREG1OUT

VDV4-0

VCI1

VC2-0

VSS(0V)

VC3=1VRL3-0

GVDD(+30~ +50V)

VC3=0VRL3-0


Voltage Waveforms


sn(source output)

VCOM

Gn (Gate output)

VGH(+9 ~ +165V)


VgoffH (~to -50V)


GVDD(+30~ +50V)VDD(20V ~ 33V)

AVDD(+35~ +55V)

VSS(0V)






OVcomOUT


OVREG2OUT


OVREG1OUT


IOREGP





IOVCI



IOAVDD



-VDD

DescriptionIOSymbol




OVgoffL


OVgoffH



voltage

OVgoffOUT


IVgoff


higher than -150 V

OVGL



OVGH



OVcomL


OVcomH



IVcomR

DescriptionIOSymbol



mA2015-IVCI



by mode


Outputs


Outputs


Outputs





V5-3GVDD

V-5--16VGOFF

V-9--165VGL

V165-9VGH


V55-35AVDD

LCD Supply Voltage







Vcom


Vcom



Vgoff






V595583571VREG1OUT









VCI2

VCI VCI

VDDVSSVCIVSS

C7

int

VGL

VGH

C1VGH

C22P

C16


C11+

C1 5REGP

VCL

C31MVCI3

C22M

C12-C12+

C11-Vci1

VCIOUT

VCOMR

VGOFFOUT

VGOFFL

C20

C19

VCOMOUT

VCOMH

VREG1OUT

VREG2OUT

C 21

C 11


(Vgoffadjustment)


adjustment)

VcomHadjustment

circuit


circuit

GVDDoutput

amplifier

VcomHoutput

amplifier

VcomLoutput

amplifier

VgoffHoutput


amplifier


circuit

C12

C9GVDD

VGOFFH

C10

Voltageadjustment

circuitRegulator

Charge-pump

circuit 1

C23PC23M

C21M

Charge-pump

circuit 2

C21P

C31P Charge-pump

circuit 3

C41-Vci4

C41+ Charge-pump

circuit 4

REGN

C14C17

AVDD

C18

C4

C3

C2

C6

VC1

C5

C3


AVDD

VGL

GVDD

VCOML





GRAMMSB LSB

PKP00PKP01PKP02

PKP10PKP11PKP12

PKP20PKP21PKP22

PKP30PKP31PKP32

PKP40PKP41PKP42

PKP50PKP51PKP52

PRP00PRP01PRP02

PRP10PRP11PRP12

VRP00VRP01VRP02

VRP10VRP11VRP12

VRP03

VRP13VRP14

PKN00PKN01PKN02

PKN10PKN11PKN12

PKN20PKN21PKN22

PKN30PKN31PKN32

PKN40PKN41PKN42

PKN50PKN51PKN52

PRN00PRN01PRN02

PRN10PRN11PRN12

VRN00VRN01VRN02

VRN10VRN11VRN12

VRN03

VRN13VRN14



GrayscaleAm plifier


ltRgt

LCD driver

64 grayscalecontrol

ltG gt

LCD driver

64 grayscalecontrol

ltBgt

LCD driver

64

V1

V0

V63

6 6 6

R G BLCD


Scan Mode

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176


11


01

G176 G175 G174 G173 hellip G4 G3 G2 G110

G1 G2 G3 G4 hellip G173 G174 G175 G17600

Scan ModeGSSM

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176


A

B

C

D

A

B

C

D






33 3 3 3 54333








G V D D

V G S


V I N P N 0

V I N P N 1

V I N P N 2

V I N P N 3

V I N P N 4

V I N P N 5

V I N P N 6

V I N P N 7

V 0

V 6 3

V 6 2

V 5 5

V 4 3

V 2 0

V 8

V 1V 2V 3

V 9

V 2 1

V 4 4

V 5 6V 5 7





Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge





8080Dummy Pad1195239742


Pad sizeum


UnitSize

Pad nameItems









Technology






25532V Process










Gat

e D

river

IC


Gat

e D

river

IC

T-Con

LTPS TFT-LCD


Source Driver IC

Gat

e D

river

IC

De-MUX






Outline









Digital vs Analog




TTL vs LVDS





XGA 325M (2 ports)

67M ( 1 port)

67M (2 ports)

SXGA 54M (2 ports)

54M (2 ports)

108M (2 ports)

Frequency

UXGA - 81M 162M LCD




6-bit ~80 ~60 ~50



RSDS Definition




8 Bit RGB RSDS Data

Start pulseR0 R1

R2 R3

R4 R5

G0 G1

G2 G3G4 G5

B0 B1

B2 B3

B4 B5

Invalid data

Invalid data

Invalid data

R6 R7

G6 G7

B6 B7



Single-end

FrontBack








Mini-LVDS

Data Bus Structure


Mini-LVDS

6 bit data 5 pairs


8 bit data 6 pairs

Mini-LVDS






TQFP100


RSDS vs Mini-LVDS













PPDSRSDSParameter



PPDSTM








PPDS Protocol





10-bit(1024灰階)


Memo



bull Cst on gate

CstClc

Cgd

Cds

Scan line n

Scan line n-1

Vcom

3-level

Vghl Vgc

Pixel voltage

V1V2

V3321 VVV Δ+Δ=Δ





+++times=Δ 1

CdsCgdCstClcCstVgcV

+++times=Δ 2

CdsCgdCstClcCgdVgcV

+++times=Δ 3


CgdCstCgdVghlVgc+

times= then

778205040

05025

4710504040


=+

=+

timesΔ=

=++

times=Δ

gds

gdghlgc

gd

CCC

VV

VV



Data Center

Positive Driving

Negative Driving


Black(+)

White(+)

Black(-)


Positive Driving

Negative Driving


Final Vcom

Positive Driving

Negative Driving


Black(+)

White(+)

Black(-)

White(-)

Black(+)

White(+)

Black(-)

White(-)


Cs on gate

CstClc

Cgd

Cds

Scan line n

Scan line n-1

Vcom

Negative Polarity

GN-1(+)

VP

V1V2

V3


Positive Polarity

V4

V5

V6

GN(-)

GN-1(-)

GN(+)

VP

Vcom

Vblack(+)

Vblack(-)

Vg Ve+

Ve-Vg






( ) ( )

( )

( )CgdCCstCgdVeV

CgdCCstCstVeV

CgdCCstCgdVeVgV

LC

LC

LC

++timesminus=Δ

++times+=Δ

++timesminus+=Δ

)(3

)(2

)(1 ( ) ( )

( )

( )CgdCCstCgdVeV

CgdCCstCstVeV

CgdCCstCgdVeVgV

LC

LC

LC

++times+=Δ

++timesminus=Δ

++times+minus=Δ

)(6

)(5

)(4

CstCgdVgVeVe

VVVVVV



2)()(

654321Q




Data Center

Positive Driving

Negative Driving

Black(+)

White(+)White(-)


Black(-)


Data Center

Positive Driving

Negative Driving

Black(+)

White(+)White(-)

Black(-)





VVVV2-level driving

high voltage

high voltage

Lowhigh voltage

Lowhigh voltage

Output range


DotColumnRowFrame

Vcom ACDC






















Analog Data Driver


Shift Register

pixel

Qi Qi+1Video

in

pixel



Video in

control

pixel

Qi+1 Qi+2


Samplecapacitor

hold capacitor








SIPO1 phase

SISO1 phase




Pixel1

Pixel2

Pixel3

Pixel4

Pixel5

Pixel6

Pixel7

Pixel8



SR

Video in






Driver IC


Sample

Hold

Buffer

Sample

Hold

Buffer

Sample

Hold

Buffer

Sample

Hold

Buffer

SR SR SR SR


Pixel1

Pixel2

Pixel3

Pixel4

Pixel5

Pixel6

Pixel7

Pixel8


DeMUX 12



Videoin


Driver


LAAT vs PAAT







Digital Data Driver






lowhighcost






AnalogDigital



Latch Signal

Polarity Signal

Analog Part

Digital Part

To LCD data line

CLKDIO1

Out1 Out2 Out3 Outn

DIO2

HoldReg

Sample Reg

SR

Buffer

LevelShifter

HoldReg

Sample Reg

SR

Buffer

LevelShifter

HoldReg

Sample Reg

SR

Buffer

LevelShifter

HoldReg

Sample Reg

SR

Buffer

LevelShifter

HoldReg

SR

Buffer

LevelShifter

sample reg


Dat

are

ceiv

er


Datain

Output buffers

Level Shifter



Data latch

CLK

DIO1

128 CLKs


128 CLKs

DIO2

P1 P2 P3 P130P129P128P4 P5 P131 P132 P133P127





Tst

POL

Odd outputs


Positive

Tst

Vcom


LD

1K

15P

1K

15P

1K

15P

1K

15P

1K

15P

High-Z High-Z

High-Z

(CLK1)



sharing hellipetc)



720

7

4201680x3WSXGA+7206424801920x3HDTV

4804321440x3WXGA

4141366x3WXGA

512

402

12

480

420

38431224019210 9

1400x3SXGA+

1600x3UXGA

2048x3QXGA











Horizontal period

Pixel frequency

Horizontal period

Pixel frequency




DA Converter









Idea DA Converter


1 2 011 2 12 2 2 2

n nin n n








1 2 011 2 1

2 2 2 2

2


refLSB N

b b bbV V L V B

VV

minus minusminus

⎛ ⎞= + + + + = times⎜ ⎟⎝ ⎠




















Offset Error



2-bit example

00( ) outoff

LSB

VE DAC V=






LSB LSB

V VEV V





Accuracy



error


removed










DA Converter









bull Glitches






Decoder-based

Binary-weighted

Thermometer-code

Hybrid



Decoder-Based DAC








Decoder-Based DAC






R

R

R

R

R

R

R

R

R

b0 b0

b1 b1

b2

b2

Vout

VRef

2N resistors

Bin = b22-1+b12-2+b02-3


















( 1) (2 3 )

tr tr tr tr tr tr

tr tr

R C R C N R C

N N R C


= + sdot

L











R

R

R

R

R

R

R

R

R

VRef

Vout

b2

b1

b0




Decoder-Based DAC



























3 2 1

1 2 33 2 1

2 4 8 2 2 2

Fout F ref ref In

In




= + + +LL

bull 4-bit example





















R-2R-based DAC


bull 4-bit example


11 1

_2 2 2

N Nref i R iF

R out F refi ii i


= =


sum sum













Current-mode DAC


ground potential

















across RF)









bull Glitches


















current sources












Examples of DAC 2





R-String DAC

R2

R2

R

R

R

R

R

R

R

b1b1

out

5

-19

b3b2b2 b3







ROM Decoder


Gamma Correction




Gamma Correction






Low noise






Output Buffer

DAC P

DAC N


OddOutput

EvenOutput

Gamma Voltage

(+)

Gamma Voltage

(-)

To data line

Rail to rail OP-AMP

-+

+-


Output Buffer

DAC P

negativebuffer


OddOutput

EvenOutput

Gamma Voltage

(+)

Gamma Voltage

(-)

To data line


PN type OP-AMP

DAC N

positivebuffer

+-

+-




Low deviation



Optimum OP AMP area



V1V2

+

-

Vss

Vdd

+

-+

-

Vout=Av(V1-V2)+

-





stage

High-gainstage

OutputBuffer


Bias Circuitry

Vout VoutrsquoV1V2





2




Hierarchy

Current to voltage

Current to voltage

voltage to current

voltage to current

conversion



(current mirror)





MOS diodeload


Class B (push-pull)

Currentstage

1stvoltagestage

2ndvoltagestage



Examples of Op-Amp





Design of Op Amp





1 Hand calculation









V-1005(L=1um)001(L=2um)

004(L=1um)001(L=2um)




Krsquo



symbol
















A(s)

F(s)

+

-ΣVin(s) Vout(s)

















need compensation




Z1 = gmIICC

CII gtgt CI CC



loop gain F(s)=1






and the RHP zero


C

m

C

mI

Cg

CgGB 2=cong

C

m

C

mI

m

II

mII

Cm

dsdsdsds

CmII

III

Cg

Cgz

Cg

Cgp

Cggggg

CgGGp

21

2

62

6

76421

))((

=cong

minus=

minuscong

++minus=

minuscong

Unit gain bandwidth






Cm

dsdsdsds

CmII

III

Cggggg

CgGGp

6

7642

1

))(( ++minus

=minus

cong








2

62 C

gCgp m

II

mII minus=

minuscong






VsCRsCgRV

sCRRV

sCRsCRgsV

CII

CmII

CII

II

CII

CIImout 1

)1(1

1

)1()( 66

+minusminus

=⎟⎟⎠

⎞⎜⎜⎝

⎛+

+⎟⎟⎠

⎞⎜⎜⎝

⎛+

minus=

Vrsquorsquo

Vout

VDD

CC

Vrsquo

++

--

M6

RII



IC1 IC2


VocOutput offset

between chip tochip




of gray m


Offset Cancellation

Voffset

VinVo=Vin+Voffset


Phase 1

Phase 2

Caz



Caz

Vo=Vin


+-

+ -

- +

- +

- +-+



Channel 384

Channel 383

Channel 382

Channel 381

Channel 4

Channel 3

Channel 2

Channel 1

Length

Height


Channel 420

Channel 419

Channel 418

Channel 417

Channel 4

Channel 3

Channel 2

Channel 1


Channel 480

Channel 479

Channel 478

Channel 477

Channel 4

Channel 3

Channel 2

Channel 1


resistor

Gammaresistor

Gammaresistor



TSMC HV Process




LCD Panel

Start pulse










dtdVCI times=

P = fdCloadVDD2

Turn on one clock




ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

clock

clock

Clock 2Clock 1

Clock 2Clock 1



Dual edge clocking

1 2 3 4

CK1XCK1CK2XCK2


Charge Sharing

To data line

DAC P


OddOutput

EvenOutput

OP

OPDAC NData

Data

Vgmama+

Vgmama-

-+

-+









CNS for Car

4~8mA

DSC Game PDA

2~3mA

05 ~ 2 mA

Mobile-phone


Large size panel









TV application


Outline









LCD TV Electronics

LCD Control Board


SDTV 720x480

cable


DCDC power




LCD Module

TTLLVDSTMDS

γ


OSD

Scaler

MCU

ADCAnalog

RGB

VideoDecoder

DigitalDVI

TMDSRx

De-interlace

Tuner

YC

SyncSep

Compositevideo

AntennaRF in

YCbCr

YPbPr



Digital TV System


MPEG2Decoder PODCI

32MB DDRSDRAM

Scaler IC







RESETRESET


SWITCHSWITCH



DiodesDiodes

LCDLCDDRIVERDRIVER


MICONMICON



INVERTERINVERTER


LCDLCDPANELPANEL

POWERAMPPOWERAMP




LA7585LA7585LA758788LA758788

LA7565LA7565


LA426061LA426061LA426570LA426570LA428082LA428082


LA7221LA7221









LA76818LA76818LA863228LA863228

FSS140132134FSS140132134CPH33043414CPH33043414


CPH5506CPH5506

LA426642674268LA426642674268LA427642774278LA427642774278








Black Insertion





DAC

γminus18R1 string

γminus22R2 string

γminus26R3 string

switch


Vref [118] Vout

8-bit Data


V0~V255




example



Over-8 bit data







Gn-1

Gn

Gray Level



Actual Response

Gn-1

Gn

Gray Level


Gn

Overdrive Response

Voltage by Driver







Overdrive Circuits

Memory

Lookup Table

Control ckts

Data

Dn

Dn+1

Ctrl

addressReadWrite

Datarsquo




ight

ness

Normal image

brig

htne

ss

bright imagebr

ight

ness


Other Technologies






LCD TV Trends


Size

BrightnessCR

Response Time

LCD Monitor

15-20rdquo

250400

25~16ms


Resolution XGA~UXGA

2002~2003

LCD TV


400~550500~700 gt550gt2k

25~16ms 16~12ms lt 8 ms

160160 176176


2004~2008

challenge

COST


Outline








TFTTFT



Controller025 μm

Sourcedriver05 μm


Gatedriver

06 μm HV



HV

Single chipHV

4 Chip TCPCOF Type

2 Chip COGCOF Type

1 Chip COG Type


HitachiSamsung

奇景聯詠

智寶科技







PWR SRAMGAMA64

APRSRAM

Gate Driver

PWR



18

64

18


Gate control

PowerSupplyCircuit

TimingGenerator

OSCSystem Interface


Indexregister

Controlregister

graylevelgenerator




Gammaadjusting

Addresscounter

VGHVGL

VgoffGVDDVGS

AVDD

18

G17

7G

176

G17

5 G

2G

1G

0

S396

S395

S394

S3 S2 S1

SPIC

ontrol

RW

Data

VDD3VDD

Latch circuitand

Vcom


Voltage Setting


VDD(20V ~ 33V)


VCI(25V ~ 33V)

BT2-0

BT2-0

VRH3-0

VREG2OUT

VCOM4-0

VGH(+9 ~ +165V)

AVDD(+35~ +55V)


VCL

VgoffH (to -50V)


VGL (-165 to -9V)

-1 times-1 times

VREG1OUT

VDV4-0

VCI1

VC2-0

VSS(0V)

VC3=1VRL3-0

GVDD(+30~ +50V)

VC3=0VRL3-0


Voltage Waveforms


sn(source output)

VCOM

Gn (Gate output)

VGH(+9 ~ +165V)


VgoffH (~to -50V)


GVDD(+30~ +50V)VDD(20V ~ 33V)

AVDD(+35~ +55V)

VSS(0V)






OVcomOUT


OVREG2OUT


OVREG1OUT


IOREGP





IOVCI



IOAVDD



-VDD

DescriptionIOSymbol




OVgoffL


OVgoffH



voltage

OVgoffOUT


IVgoff


higher than -150 V

OVGL



OVGH



OVcomL


OVcomH



IVcomR

DescriptionIOSymbol



mA2015-IVCI



by mode


Outputs


Outputs


Outputs





V5-3GVDD

V-5--16VGOFF

V-9--165VGL

V165-9VGH


V55-35AVDD

LCD Supply Voltage







Vcom


Vcom



Vgoff






V595583571VREG1OUT









VCI2

VCI VCI

VDDVSSVCIVSS

C7

int

VGL

VGH

C1VGH

C22P

C16


C11+

C1 5REGP

VCL

C31MVCI3

C22M

C12-C12+

C11-Vci1

VCIOUT

VCOMR

VGOFFOUT

VGOFFL

C20

C19

VCOMOUT

VCOMH

VREG1OUT

VREG2OUT

C 21

C 11


(Vgoffadjustment)


adjustment)

VcomHadjustment

circuit


circuit

GVDDoutput

amplifier

VcomHoutput

amplifier

VcomLoutput

amplifier

VgoffHoutput


amplifier


circuit

C12

C9GVDD

VGOFFH

C10

Voltageadjustment

circuitRegulator

Charge-pump

circuit 1

C23PC23M

C21M

Charge-pump

circuit 2

C21P

C31P Charge-pump

circuit 3

C41-Vci4

C41+ Charge-pump

circuit 4

REGN

C14C17

AVDD

C18

C4

C3

C2

C6

VC1

C5

C3


AVDD

VGL

GVDD

VCOML





GRAMMSB LSB

PKP00PKP01PKP02

PKP10PKP11PKP12

PKP20PKP21PKP22

PKP30PKP31PKP32

PKP40PKP41PKP42

PKP50PKP51PKP52

PRP00PRP01PRP02

PRP10PRP11PRP12

VRP00VRP01VRP02

VRP10VRP11VRP12

VRP03

VRP13VRP14

PKN00PKN01PKN02

PKN10PKN11PKN12

PKN20PKN21PKN22

PKN30PKN31PKN32

PKN40PKN41PKN42

PKN50PKN51PKN52

PRN00PRN01PRN02

PRN10PRN11PRN12

VRN00VRN01VRN02

VRN10VRN11VRN12

VRN03

VRN13VRN14



GrayscaleAm plifier


ltRgt

LCD driver

64 grayscalecontrol

ltG gt

LCD driver

64 grayscalecontrol

ltBgt

LCD driver

64

V1

V0

V63

6 6 6

R G BLCD


Scan Mode

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176


11


01

G176 G175 G174 G173 hellip G4 G3 G2 G110

G1 G2 G3 G4 hellip G173 G174 G175 G17600

Scan ModeGSSM

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176


A

B

C

D

A

B

C

D






33 3 3 3 54333








G V D D

V G S


V I N P N 0

V I N P N 1

V I N P N 2

V I N P N 3

V I N P N 4

V I N P N 5

V I N P N 6

V I N P N 7

V 0

V 6 3

V 6 2

V 5 5

V 4 3

V 2 0

V 8

V 1V 2V 3

V 9

V 2 1

V 4 4

V 5 6V 5 7





Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge





8080Dummy Pad1195239742


Pad sizeum


UnitSize

Pad nameItems









Technology






25532V Process










Gat

e D

river

IC


Gat

e D

river

IC

T-Con

LTPS TFT-LCD


Source Driver IC

Gat

e D

river

IC

De-MUX






Outline









Digital vs Analog




TTL vs LVDS





XGA 325M (2 ports)

67M ( 1 port)

67M (2 ports)

SXGA 54M (2 ports)

54M (2 ports)

108M (2 ports)

Frequency

UXGA - 81M 162M LCD




6-bit ~80 ~60 ~50



RSDS Definition




8 Bit RGB RSDS Data

Start pulseR0 R1

R2 R3

R4 R5

G0 G1

G2 G3G4 G5

B0 B1

B2 B3

B4 B5

Invalid data

Invalid data

Invalid data

R6 R7

G6 G7

B6 B7



Single-end

FrontBack








Mini-LVDS

Data Bus Structure


Mini-LVDS

6 bit data 5 pairs


8 bit data 6 pairs

Mini-LVDS






TQFP100


RSDS vs Mini-LVDS













PPDSRSDSParameter



PPDSTM








PPDS Protocol





10-bit(1024灰階)


Memo




( ) ( )

( )

( )CgdCCstCgdVeV

CgdCCstCstVeV

CgdCCstCgdVeVgV

LC

LC

LC

++timesminus=Δ

++times+=Δ

++timesminus+=Δ

)(3

)(2

)(1 ( ) ( )

( )

( )CgdCCstCgdVeV

CgdCCstCstVeV

CgdCCstCgdVeVgV

LC

LC

LC

++times+=Δ

++timesminus=Δ

++times+minus=Δ

)(6

)(5

)(4

CstCgdVgVeVe

VVVVVV



2)()(

654321Q




Data Center

Positive Driving

Negative Driving

Black(+)

White(+)White(-)


Black(-)


Data Center

Positive Driving

Negative Driving

Black(+)

White(+)White(-)

Black(-)





VVVV2-level driving

high voltage

high voltage

Lowhigh voltage

Lowhigh voltage

Output range


DotColumnRowFrame

Vcom ACDC






















Analog Data Driver


Shift Register

pixel

Qi Qi+1Video

in

pixel



Video in

control

pixel

Qi+1 Qi+2


Samplecapacitor

hold capacitor








SIPO1 phase

SISO1 phase




Pixel1

Pixel2

Pixel3

Pixel4

Pixel5

Pixel6

Pixel7

Pixel8



SR

Video in






Driver IC


Sample

Hold

Buffer

Sample

Hold

Buffer

Sample

Hold

Buffer

Sample

Hold

Buffer

SR SR SR SR


Pixel1

Pixel2

Pixel3

Pixel4

Pixel5

Pixel6

Pixel7

Pixel8


DeMUX 12



Videoin


Driver


LAAT vs PAAT







Digital Data Driver






lowhighcost






AnalogDigital



Latch Signal

Polarity Signal

Analog Part

Digital Part

To LCD data line

CLKDIO1

Out1 Out2 Out3 Outn

DIO2

HoldReg

Sample Reg

SR

Buffer

LevelShifter

HoldReg

Sample Reg

SR

Buffer

LevelShifter

HoldReg

Sample Reg

SR

Buffer

LevelShifter

HoldReg

Sample Reg

SR

Buffer

LevelShifter

HoldReg

SR

Buffer

LevelShifter

sample reg


Dat

are

ceiv

er


Datain

Output buffers

Level Shifter



Data latch

CLK

DIO1

128 CLKs


128 CLKs

DIO2

P1 P2 P3 P130P129P128P4 P5 P131 P132 P133P127





Tst

POL

Odd outputs


Positive

Tst

Vcom


LD

1K

15P

1K

15P

1K

15P

1K

15P

1K

15P

High-Z High-Z

High-Z

(CLK1)



sharing hellipetc)



720

7

4201680x3WSXGA+7206424801920x3HDTV

4804321440x3WXGA

4141366x3WXGA

512

402

12

480

420

38431224019210 9

1400x3SXGA+

1600x3UXGA

2048x3QXGA











Horizontal period

Pixel frequency

Horizontal period

Pixel frequency




DA Converter









Idea DA Converter


1 2 011 2 12 2 2 2

n nin n n








1 2 011 2 1

2 2 2 2

2


refLSB N

b b bbV V L V B

VV

minus minusminus

⎛ ⎞= + + + + = times⎜ ⎟⎝ ⎠




















Offset Error



2-bit example

00( ) outoff

LSB

VE DAC V=






LSB LSB

V VEV V





Accuracy



error


removed










DA Converter









bull Glitches






Decoder-based

Binary-weighted

Thermometer-code

Hybrid



Decoder-Based DAC








Decoder-Based DAC






R

R

R

R

R

R

R

R

R

b0 b0

b1 b1

b2

b2

Vout

VRef

2N resistors

Bin = b22-1+b12-2+b02-3


















( 1) (2 3 )

tr tr tr tr tr tr

tr tr

R C R C N R C

N N R C


= + sdot

L











R

R

R

R

R

R

R

R

R

VRef

Vout

b2

b1

b0




Decoder-Based DAC



























3 2 1

1 2 33 2 1

2 4 8 2 2 2

Fout F ref ref In

In




= + + +LL

bull 4-bit example





















R-2R-based DAC


bull 4-bit example


11 1

_2 2 2

N Nref i R iF

R out F refi ii i


= =


sum sum













Current-mode DAC


ground potential

















across RF)









bull Glitches


















current sources












Examples of DAC 2





R-String DAC

R2

R2

R

R

R

R

R

R

R

b1b1

out

5

-19

b3b2b2 b3







ROM Decoder


Gamma Correction




Gamma Correction






Low noise






Output Buffer

DAC P

DAC N


OddOutput

EvenOutput

Gamma Voltage

(+)

Gamma Voltage

(-)

To data line

Rail to rail OP-AMP

-+

+-


Output Buffer

DAC P

negativebuffer


OddOutput

EvenOutput

Gamma Voltage

(+)

Gamma Voltage

(-)

To data line


PN type OP-AMP

DAC N

positivebuffer

+-

+-




Low deviation



Optimum OP AMP area



V1V2

+

-

Vss

Vdd

+

-+

-

Vout=Av(V1-V2)+

-





stage

High-gainstage

OutputBuffer


Bias Circuitry

Vout VoutrsquoV1V2





2




Hierarchy

Current to voltage

Current to voltage

voltage to current

voltage to current

conversion



(current mirror)





MOS diodeload


Class B (push-pull)

Currentstage

1stvoltagestage

2ndvoltagestage



Examples of Op-Amp





Design of Op Amp





1 Hand calculation









V-1005(L=1um)001(L=2um)

004(L=1um)001(L=2um)




Krsquo



symbol
















A(s)

F(s)

+

-ΣVin(s) Vout(s)

















need compensation




Z1 = gmIICC

CII gtgt CI CC



loop gain F(s)=1






and the RHP zero


C

m

C

mI

Cg

CgGB 2=cong

C

m

C

mI

m

II

mII

Cm

dsdsdsds

CmII

III

Cg

Cgz

Cg

Cgp

Cggggg

CgGGp

21

2

62

6

76421

))((

=cong

minus=

minuscong

++minus=

minuscong

Unit gain bandwidth






Cm

dsdsdsds

CmII

III

Cggggg

CgGGp

6

7642

1

))(( ++minus

=minus

cong








2

62 C

gCgp m

II

mII minus=

minuscong






VsCRsCgRV

sCRRV

sCRsCRgsV

CII

CmII

CII

II

CII

CIImout 1

)1(1

1

)1()( 66

+minusminus

=⎟⎟⎠

⎞⎜⎜⎝

⎛+

+⎟⎟⎠

⎞⎜⎜⎝

⎛+

minus=

Vrsquorsquo

Vout

VDD

CC

Vrsquo

++

--

M6

RII



IC1 IC2


VocOutput offset

between chip tochip




of gray m


Offset Cancellation

Voffset

VinVo=Vin+Voffset


Phase 1

Phase 2

Caz



Caz

Vo=Vin


+-

+ -

- +

- +

- +-+



Channel 384

Channel 383

Channel 382

Channel 381

Channel 4

Channel 3

Channel 2

Channel 1

Length

Height


Channel 420

Channel 419

Channel 418

Channel 417

Channel 4

Channel 3

Channel 2

Channel 1


Channel 480

Channel 479

Channel 478

Channel 477

Channel 4

Channel 3

Channel 2

Channel 1


resistor

Gammaresistor

Gammaresistor



TSMC HV Process




LCD Panel

Start pulse










dtdVCI times=

P = fdCloadVDD2

Turn on one clock




ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

clock

clock

Clock 2Clock 1

Clock 2Clock 1



Dual edge clocking

1 2 3 4

CK1XCK1CK2XCK2


Charge Sharing

To data line

DAC P


OddOutput

EvenOutput

OP

OPDAC NData

Data

Vgmama+

Vgmama-

-+

-+









CNS for Car

4~8mA

DSC Game PDA

2~3mA

05 ~ 2 mA

Mobile-phone


Large size panel









TV application


Outline









LCD TV Electronics

LCD Control Board


SDTV 720x480

cable


DCDC power




LCD Module

TTLLVDSTMDS

γ


OSD

Scaler

MCU

ADCAnalog

RGB

VideoDecoder

DigitalDVI

TMDSRx

De-interlace

Tuner

YC

SyncSep

Compositevideo

AntennaRF in

YCbCr

YPbPr



Digital TV System


MPEG2Decoder PODCI

32MB DDRSDRAM

Scaler IC







RESETRESET


SWITCHSWITCH



DiodesDiodes

LCDLCDDRIVERDRIVER


MICONMICON



INVERTERINVERTER


LCDLCDPANELPANEL

POWERAMPPOWERAMP




LA7585LA7585LA758788LA758788

LA7565LA7565


LA426061LA426061LA426570LA426570LA428082LA428082


LA7221LA7221









LA76818LA76818LA863228LA863228

FSS140132134FSS140132134CPH33043414CPH33043414


CPH5506CPH5506

LA426642674268LA426642674268LA427642774278LA427642774278








Black Insertion





DAC

γminus18R1 string

γminus22R2 string

γminus26R3 string

switch


Vref [118] Vout

8-bit Data


V0~V255




example



Over-8 bit data







Gn-1

Gn

Gray Level



Actual Response

Gn-1

Gn

Gray Level


Gn

Overdrive Response

Voltage by Driver







Overdrive Circuits

Memory

Lookup Table

Control ckts

Data

Dn

Dn+1

Ctrl

addressReadWrite

Datarsquo




ight

ness

Normal image

brig

htne

ss

bright imagebr

ight

ness


Other Technologies






LCD TV Trends


Size

BrightnessCR

Response Time

LCD Monitor

15-20rdquo

250400

25~16ms


Resolution XGA~UXGA

2002~2003

LCD TV


400~550500~700 gt550gt2k

25~16ms 16~12ms lt 8 ms

160160 176176


2004~2008

challenge

COST


Outline








TFTTFT



Controller025 μm

Sourcedriver05 μm


Gatedriver

06 μm HV



HV

Single chipHV

4 Chip TCPCOF Type

2 Chip COGCOF Type

1 Chip COG Type


HitachiSamsung

奇景聯詠

智寶科技







PWR SRAMGAMA64

APRSRAM

Gate Driver

PWR



18

64

18


Gate control

PowerSupplyCircuit

TimingGenerator

OSCSystem Interface


Indexregister

Controlregister

graylevelgenerator




Gammaadjusting

Addresscounter

VGHVGL

VgoffGVDDVGS

AVDD

18

G17

7G

176

G17

5 G

2G

1G

0

S396

S395

S394

S3 S2 S1

SPIC

ontrol

RW

Data

VDD3VDD

Latch circuitand

Vcom


Voltage Setting


VDD(20V ~ 33V)


VCI(25V ~ 33V)

BT2-0

BT2-0

VRH3-0

VREG2OUT

VCOM4-0

VGH(+9 ~ +165V)

AVDD(+35~ +55V)


VCL

VgoffH (to -50V)


VGL (-165 to -9V)

-1 times-1 times

VREG1OUT

VDV4-0

VCI1

VC2-0

VSS(0V)

VC3=1VRL3-0

GVDD(+30~ +50V)

VC3=0VRL3-0


Voltage Waveforms


sn(source output)

VCOM

Gn (Gate output)

VGH(+9 ~ +165V)


VgoffH (~to -50V)


GVDD(+30~ +50V)VDD(20V ~ 33V)

AVDD(+35~ +55V)

VSS(0V)






OVcomOUT


OVREG2OUT


OVREG1OUT


IOREGP





IOVCI



IOAVDD



-VDD

DescriptionIOSymbol




OVgoffL


OVgoffH



voltage

OVgoffOUT


IVgoff


higher than -150 V

OVGL



OVGH



OVcomL


OVcomH



IVcomR

DescriptionIOSymbol



mA2015-IVCI



by mode


Outputs


Outputs


Outputs





V5-3GVDD

V-5--16VGOFF

V-9--165VGL

V165-9VGH


V55-35AVDD

LCD Supply Voltage







Vcom


Vcom



Vgoff






V595583571VREG1OUT









VCI2

VCI VCI

VDDVSSVCIVSS

C7

int

VGL

VGH

C1VGH

C22P

C16


C11+

C1 5REGP

VCL

C31MVCI3

C22M

C12-C12+

C11-Vci1

VCIOUT

VCOMR

VGOFFOUT

VGOFFL

C20

C19

VCOMOUT

VCOMH

VREG1OUT

VREG2OUT

C 21

C 11


(Vgoffadjustment)


adjustment)

VcomHadjustment

circuit


circuit

GVDDoutput

amplifier

VcomHoutput

amplifier

VcomLoutput

amplifier

VgoffHoutput


amplifier


circuit

C12

C9GVDD

VGOFFH

C10

Voltageadjustment

circuitRegulator

Charge-pump

circuit 1

C23PC23M

C21M

Charge-pump

circuit 2

C21P

C31P Charge-pump

circuit 3

C41-Vci4

C41+ Charge-pump

circuit 4

REGN

C14C17

AVDD

C18

C4

C3

C2

C6

VC1

C5

C3


AVDD

VGL

GVDD

VCOML





GRAMMSB LSB

PKP00PKP01PKP02

PKP10PKP11PKP12

PKP20PKP21PKP22

PKP30PKP31PKP32

PKP40PKP41PKP42

PKP50PKP51PKP52

PRP00PRP01PRP02

PRP10PRP11PRP12

VRP00VRP01VRP02

VRP10VRP11VRP12

VRP03

VRP13VRP14

PKN00PKN01PKN02

PKN10PKN11PKN12

PKN20PKN21PKN22

PKN30PKN31PKN32

PKN40PKN41PKN42

PKN50PKN51PKN52

PRN00PRN01PRN02

PRN10PRN11PRN12

VRN00VRN01VRN02

VRN10VRN11VRN12

VRN03

VRN13VRN14



GrayscaleAm plifier


ltRgt

LCD driver

64 grayscalecontrol

ltG gt

LCD driver

64 grayscalecontrol

ltBgt

LCD driver

64

V1

V0

V63

6 6 6

R G BLCD


Scan Mode

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176


11


01

G176 G175 G174 G173 hellip G4 G3 G2 G110

G1 G2 G3 G4 hellip G173 G174 G175 G17600

Scan ModeGSSM

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176


A

B

C

D

A

B

C

D






33 3 3 3 54333








G V D D

V G S


V I N P N 0

V I N P N 1

V I N P N 2

V I N P N 3

V I N P N 4

V I N P N 5

V I N P N 6

V I N P N 7

V 0

V 6 3

V 6 2

V 5 5

V 4 3

V 2 0

V 8

V 1V 2V 3

V 9

V 2 1

V 4 4

V 5 6V 5 7





Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge





8080Dummy Pad1195239742


Pad sizeum


UnitSize

Pad nameItems









Technology






25532V Process










Gat

e D

river

IC


Gat

e D

river

IC

T-Con

LTPS TFT-LCD


Source Driver IC

Gat

e D

river

IC

De-MUX






Outline









Digital vs Analog




TTL vs LVDS





XGA 325M (2 ports)

67M ( 1 port)

67M (2 ports)

SXGA 54M (2 ports)

54M (2 ports)

108M (2 ports)

Frequency

UXGA - 81M 162M LCD




6-bit ~80 ~60 ~50



RSDS Definition




8 Bit RGB RSDS Data

Start pulseR0 R1

R2 R3

R4 R5

G0 G1

G2 G3G4 G5

B0 B1

B2 B3

B4 B5

Invalid data

Invalid data

Invalid data

R6 R7

G6 G7

B6 B7



Single-end

FrontBack








Mini-LVDS

Data Bus Structure


Mini-LVDS

6 bit data 5 pairs


8 bit data 6 pairs

Mini-LVDS






TQFP100


RSDS vs Mini-LVDS













PPDSRSDSParameter



PPDSTM








PPDS Protocol





10-bit(1024灰階)


Memo
















Analog Data Driver


Shift Register

pixel

Qi Qi+1Video

in

pixel



Video in

control

pixel

Qi+1 Qi+2


Samplecapacitor

hold capacitor








SIPO1 phase

SISO1 phase




Pixel1

Pixel2

Pixel3

Pixel4

Pixel5

Pixel6

Pixel7

Pixel8



SR

Video in






Driver IC


Sample

Hold

Buffer

Sample

Hold

Buffer

Sample

Hold

Buffer

Sample

Hold

Buffer

SR SR SR SR


Pixel1

Pixel2

Pixel3

Pixel4

Pixel5

Pixel6

Pixel7

Pixel8


DeMUX 12



Videoin


Driver


LAAT vs PAAT







Digital Data Driver






lowhighcost






AnalogDigital



Latch Signal

Polarity Signal

Analog Part

Digital Part

To LCD data line

CLKDIO1

Out1 Out2 Out3 Outn

DIO2

HoldReg

Sample Reg

SR

Buffer

LevelShifter

HoldReg

Sample Reg

SR

Buffer

LevelShifter

HoldReg

Sample Reg

SR

Buffer

LevelShifter

HoldReg

Sample Reg

SR

Buffer

LevelShifter

HoldReg

SR

Buffer

LevelShifter

sample reg


Dat

are

ceiv

er


Datain

Output buffers

Level Shifter



Data latch

CLK

DIO1

128 CLKs


128 CLKs

DIO2

P1 P2 P3 P130P129P128P4 P5 P131 P132 P133P127





Tst

POL

Odd outputs


Positive

Tst

Vcom


LD

1K

15P

1K

15P

1K

15P

1K

15P

1K

15P

High-Z High-Z

High-Z

(CLK1)



sharing hellipetc)



720

7

4201680x3WSXGA+7206424801920x3HDTV

4804321440x3WXGA

4141366x3WXGA

512

402

12

480

420

38431224019210 9

1400x3SXGA+

1600x3UXGA

2048x3QXGA











Horizontal period

Pixel frequency

Horizontal period

Pixel frequency




DA Converter









Idea DA Converter


1 2 011 2 12 2 2 2

n nin n n








1 2 011 2 1

2 2 2 2

2


refLSB N

b b bbV V L V B

VV

minus minusminus

⎛ ⎞= + + + + = times⎜ ⎟⎝ ⎠




















Offset Error



2-bit example

00( ) outoff

LSB

VE DAC V=






LSB LSB

V VEV V





Accuracy



error


removed










DA Converter









bull Glitches






Decoder-based

Binary-weighted

Thermometer-code

Hybrid



Decoder-Based DAC








Decoder-Based DAC






R

R

R

R

R

R

R

R

R

b0 b0

b1 b1

b2

b2

Vout

VRef

2N resistors

Bin = b22-1+b12-2+b02-3


















( 1) (2 3 )

tr tr tr tr tr tr

tr tr

R C R C N R C

N N R C


= + sdot

L











R

R

R

R

R

R

R

R

R

VRef

Vout

b2

b1

b0




Decoder-Based DAC



























3 2 1

1 2 33 2 1

2 4 8 2 2 2

Fout F ref ref In

In




= + + +LL

bull 4-bit example





















R-2R-based DAC


bull 4-bit example


11 1

_2 2 2

N Nref i R iF

R out F refi ii i


= =


sum sum













Current-mode DAC


ground potential

















across RF)









bull Glitches


















current sources












Examples of DAC 2





R-String DAC

R2

R2

R

R

R

R

R

R

R

b1b1

out

5

-19

b3b2b2 b3







ROM Decoder


Gamma Correction




Gamma Correction






Low noise






Output Buffer

DAC P

DAC N


OddOutput

EvenOutput

Gamma Voltage

(+)

Gamma Voltage

(-)

To data line

Rail to rail OP-AMP

-+

+-


Output Buffer

DAC P

negativebuffer


OddOutput

EvenOutput

Gamma Voltage

(+)

Gamma Voltage

(-)

To data line


PN type OP-AMP

DAC N

positivebuffer

+-

+-




Low deviation



Optimum OP AMP area



V1V2

+

-

Vss

Vdd

+

-+

-

Vout=Av(V1-V2)+

-





stage

High-gainstage

OutputBuffer


Bias Circuitry

Vout VoutrsquoV1V2





2




Hierarchy

Current to voltage

Current to voltage

voltage to current

voltage to current

conversion



(current mirror)





MOS diodeload


Class B (push-pull)

Currentstage

1stvoltagestage

2ndvoltagestage



Examples of Op-Amp





Design of Op Amp





1 Hand calculation









V-1005(L=1um)001(L=2um)

004(L=1um)001(L=2um)




Krsquo



symbol
















A(s)

F(s)

+

-ΣVin(s) Vout(s)

















need compensation




Z1 = gmIICC

CII gtgt CI CC



loop gain F(s)=1






and the RHP zero


C

m

C

mI

Cg

CgGB 2=cong

C

m

C

mI

m

II

mII

Cm

dsdsdsds

CmII

III

Cg

Cgz

Cg

Cgp

Cggggg

CgGGp

21

2

62

6

76421

))((

=cong

minus=

minuscong

++minus=

minuscong

Unit gain bandwidth






Cm

dsdsdsds

CmII

III

Cggggg

CgGGp

6

7642

1

))(( ++minus

=minus

cong








2

62 C

gCgp m

II

mII minus=

minuscong






VsCRsCgRV

sCRRV

sCRsCRgsV

CII

CmII

CII

II

CII

CIImout 1

)1(1

1

)1()( 66

+minusminus

=⎟⎟⎠

⎞⎜⎜⎝

⎛+

+⎟⎟⎠

⎞⎜⎜⎝

⎛+

minus=

Vrsquorsquo

Vout

VDD

CC

Vrsquo

++

--

M6

RII



IC1 IC2


VocOutput offset

between chip tochip




of gray m


Offset Cancellation

Voffset

VinVo=Vin+Voffset


Phase 1

Phase 2

Caz



Caz

Vo=Vin


+-

+ -

- +

- +

- +-+



Channel 384

Channel 383

Channel 382

Channel 381

Channel 4

Channel 3

Channel 2

Channel 1

Length

Height


Channel 420

Channel 419

Channel 418

Channel 417

Channel 4

Channel 3

Channel 2

Channel 1


Channel 480

Channel 479

Channel 478

Channel 477

Channel 4

Channel 3

Channel 2

Channel 1


resistor

Gammaresistor

Gammaresistor



TSMC HV Process




LCD Panel

Start pulse










dtdVCI times=

P = fdCloadVDD2

Turn on one clock




ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

clock

clock

Clock 2Clock 1

Clock 2Clock 1



Dual edge clocking

1 2 3 4

CK1XCK1CK2XCK2


Charge Sharing

To data line

DAC P


OddOutput

EvenOutput

OP

OPDAC NData

Data

Vgmama+

Vgmama-

-+

-+









CNS for Car

4~8mA

DSC Game PDA

2~3mA

05 ~ 2 mA

Mobile-phone


Large size panel









TV application


Outline









LCD TV Electronics

LCD Control Board


SDTV 720x480

cable


DCDC power




LCD Module

TTLLVDSTMDS

γ


OSD

Scaler

MCU

ADCAnalog

RGB

VideoDecoder

DigitalDVI

TMDSRx

De-interlace

Tuner

YC

SyncSep

Compositevideo

AntennaRF in

YCbCr

YPbPr



Digital TV System


MPEG2Decoder PODCI

32MB DDRSDRAM

Scaler IC







RESETRESET


SWITCHSWITCH



DiodesDiodes

LCDLCDDRIVERDRIVER


MICONMICON



INVERTERINVERTER


LCDLCDPANELPANEL

POWERAMPPOWERAMP




LA7585LA7585LA758788LA758788

LA7565LA7565


LA426061LA426061LA426570LA426570LA428082LA428082


LA7221LA7221









LA76818LA76818LA863228LA863228

FSS140132134FSS140132134CPH33043414CPH33043414


CPH5506CPH5506

LA426642674268LA426642674268LA427642774278LA427642774278








Black Insertion





DAC

γminus18R1 string

γminus22R2 string

γminus26R3 string

switch


Vref [118] Vout

8-bit Data


V0~V255




example



Over-8 bit data







Gn-1

Gn

Gray Level



Actual Response

Gn-1

Gn

Gray Level


Gn

Overdrive Response

Voltage by Driver







Overdrive Circuits

Memory

Lookup Table

Control ckts

Data

Dn

Dn+1

Ctrl

addressReadWrite

Datarsquo




ight

ness

Normal image

brig

htne

ss

bright imagebr

ight

ness


Other Technologies






LCD TV Trends


Size

BrightnessCR

Response Time

LCD Monitor

15-20rdquo

250400

25~16ms


Resolution XGA~UXGA

2002~2003

LCD TV


400~550500~700 gt550gt2k

25~16ms 16~12ms lt 8 ms

160160 176176


2004~2008

challenge

COST


Outline








TFTTFT



Controller025 μm

Sourcedriver05 μm


Gatedriver

06 μm HV



HV

Single chipHV

4 Chip TCPCOF Type

2 Chip COGCOF Type

1 Chip COG Type


HitachiSamsung

奇景聯詠

智寶科技







PWR SRAMGAMA64

APRSRAM

Gate Driver

PWR



18

64

18


Gate control

PowerSupplyCircuit

TimingGenerator

OSCSystem Interface


Indexregister

Controlregister

graylevelgenerator




Gammaadjusting

Addresscounter

VGHVGL

VgoffGVDDVGS

AVDD

18

G17

7G

176

G17

5 G

2G

1G

0

S396

S395

S394

S3 S2 S1

SPIC

ontrol

RW

Data

VDD3VDD

Latch circuitand

Vcom


Voltage Setting


VDD(20V ~ 33V)


VCI(25V ~ 33V)

BT2-0

BT2-0

VRH3-0

VREG2OUT

VCOM4-0

VGH(+9 ~ +165V)

AVDD(+35~ +55V)


VCL

VgoffH (to -50V)


VGL (-165 to -9V)

-1 times-1 times

VREG1OUT

VDV4-0

VCI1

VC2-0

VSS(0V)

VC3=1VRL3-0

GVDD(+30~ +50V)

VC3=0VRL3-0


Voltage Waveforms


sn(source output)

VCOM

Gn (Gate output)

VGH(+9 ~ +165V)


VgoffH (~to -50V)


GVDD(+30~ +50V)VDD(20V ~ 33V)

AVDD(+35~ +55V)

VSS(0V)






OVcomOUT


OVREG2OUT


OVREG1OUT


IOREGP





IOVCI



IOAVDD



-VDD

DescriptionIOSymbol




OVgoffL


OVgoffH



voltage

OVgoffOUT


IVgoff


higher than -150 V

OVGL



OVGH



OVcomL


OVcomH



IVcomR

DescriptionIOSymbol



mA2015-IVCI



by mode


Outputs


Outputs


Outputs





V5-3GVDD

V-5--16VGOFF

V-9--165VGL

V165-9VGH


V55-35AVDD

LCD Supply Voltage







Vcom


Vcom



Vgoff






V595583571VREG1OUT









VCI2

VCI VCI

VDDVSSVCIVSS

C7

int

VGL

VGH

C1VGH

C22P

C16


C11+

C1 5REGP

VCL

C31MVCI3

C22M

C12-C12+

C11-Vci1

VCIOUT

VCOMR

VGOFFOUT

VGOFFL

C20

C19

VCOMOUT

VCOMH

VREG1OUT

VREG2OUT

C 21

C 11


(Vgoffadjustment)


adjustment)

VcomHadjustment

circuit


circuit

GVDDoutput

amplifier

VcomHoutput

amplifier

VcomLoutput

amplifier

VgoffHoutput


amplifier


circuit

C12

C9GVDD

VGOFFH

C10

Voltageadjustment

circuitRegulator

Charge-pump

circuit 1

C23PC23M

C21M

Charge-pump

circuit 2

C21P

C31P Charge-pump

circuit 3

C41-Vci4

C41+ Charge-pump

circuit 4

REGN

C14C17

AVDD

C18

C4

C3

C2

C6

VC1

C5

C3


AVDD

VGL

GVDD

VCOML





GRAMMSB LSB

PKP00PKP01PKP02

PKP10PKP11PKP12

PKP20PKP21PKP22

PKP30PKP31PKP32

PKP40PKP41PKP42

PKP50PKP51PKP52

PRP00PRP01PRP02

PRP10PRP11PRP12

VRP00VRP01VRP02

VRP10VRP11VRP12

VRP03

VRP13VRP14

PKN00PKN01PKN02

PKN10PKN11PKN12

PKN20PKN21PKN22

PKN30PKN31PKN32

PKN40PKN41PKN42

PKN50PKN51PKN52

PRN00PRN01PRN02

PRN10PRN11PRN12

VRN00VRN01VRN02

VRN10VRN11VRN12

VRN03

VRN13VRN14



GrayscaleAm plifier


ltRgt

LCD driver

64 grayscalecontrol

ltG gt

LCD driver

64 grayscalecontrol

ltBgt

LCD driver

64

V1

V0

V63

6 6 6

R G BLCD


Scan Mode

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176


11


01

G176 G175 G174 G173 hellip G4 G3 G2 G110

G1 G2 G3 G4 hellip G173 G174 G175 G17600

Scan ModeGSSM

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176


A

B

C

D

A

B

C

D






33 3 3 3 54333








G V D D

V G S


V I N P N 0

V I N P N 1

V I N P N 2

V I N P N 3

V I N P N 4

V I N P N 5

V I N P N 6

V I N P N 7

V 0

V 6 3

V 6 2

V 5 5

V 4 3

V 2 0

V 8

V 1V 2V 3

V 9

V 2 1

V 4 4

V 5 6V 5 7





Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge





8080Dummy Pad1195239742


Pad sizeum


UnitSize

Pad nameItems









Technology






25532V Process










Gat

e D

river

IC


Gat

e D

river

IC

T-Con

LTPS TFT-LCD


Source Driver IC

Gat

e D

river

IC

De-MUX






Outline









Digital vs Analog




TTL vs LVDS





XGA 325M (2 ports)

67M ( 1 port)

67M (2 ports)

SXGA 54M (2 ports)

54M (2 ports)

108M (2 ports)

Frequency

UXGA - 81M 162M LCD




6-bit ~80 ~60 ~50



RSDS Definition




8 Bit RGB RSDS Data

Start pulseR0 R1

R2 R3

R4 R5

G0 G1

G2 G3G4 G5

B0 B1

B2 B3

B4 B5

Invalid data

Invalid data

Invalid data

R6 R7

G6 G7

B6 B7



Single-end

FrontBack








Mini-LVDS

Data Bus Structure


Mini-LVDS

6 bit data 5 pairs


8 bit data 6 pairs

Mini-LVDS






TQFP100


RSDS vs Mini-LVDS













PPDSRSDSParameter



PPDSTM








PPDS Protocol





10-bit(1024灰階)


Memo








SIPO1 phase

SISO1 phase




Pixel1

Pixel2

Pixel3

Pixel4

Pixel5

Pixel6

Pixel7

Pixel8



SR

Video in






Driver IC


Sample

Hold

Buffer

Sample

Hold

Buffer

Sample

Hold

Buffer

Sample

Hold

Buffer

SR SR SR SR


Pixel1

Pixel2

Pixel3

Pixel4

Pixel5

Pixel6

Pixel7

Pixel8


DeMUX 12



Videoin


Driver


LAAT vs PAAT







Digital Data Driver






lowhighcost






AnalogDigital



Latch Signal

Polarity Signal

Analog Part

Digital Part

To LCD data line

CLKDIO1

Out1 Out2 Out3 Outn

DIO2

HoldReg

Sample Reg

SR

Buffer

LevelShifter

HoldReg

Sample Reg

SR

Buffer

LevelShifter

HoldReg

Sample Reg

SR

Buffer

LevelShifter

HoldReg

Sample Reg

SR

Buffer

LevelShifter

HoldReg

SR

Buffer

LevelShifter

sample reg


Dat

are

ceiv

er


Datain

Output buffers

Level Shifter



Data latch

CLK

DIO1

128 CLKs


128 CLKs

DIO2

P1 P2 P3 P130P129P128P4 P5 P131 P132 P133P127





Tst

POL

Odd outputs


Positive

Tst

Vcom


LD

1K

15P

1K

15P

1K

15P

1K

15P

1K

15P

High-Z High-Z

High-Z

(CLK1)



sharing hellipetc)



720

7

4201680x3WSXGA+7206424801920x3HDTV

4804321440x3WXGA

4141366x3WXGA

512

402

12

480

420

38431224019210 9

1400x3SXGA+

1600x3UXGA

2048x3QXGA











Horizontal period

Pixel frequency

Horizontal period

Pixel frequency




DA Converter









Idea DA Converter


1 2 011 2 12 2 2 2

n nin n n








1 2 011 2 1

2 2 2 2

2


refLSB N

b b bbV V L V B

VV

minus minusminus

⎛ ⎞= + + + + = times⎜ ⎟⎝ ⎠




















Offset Error



2-bit example

00( ) outoff

LSB

VE DAC V=






LSB LSB

V VEV V





Accuracy



error


removed










DA Converter









bull Glitches






Decoder-based

Binary-weighted

Thermometer-code

Hybrid



Decoder-Based DAC








Decoder-Based DAC






R

R

R

R

R

R

R

R

R

b0 b0

b1 b1

b2

b2

Vout

VRef

2N resistors

Bin = b22-1+b12-2+b02-3


















( 1) (2 3 )

tr tr tr tr tr tr

tr tr

R C R C N R C

N N R C


= + sdot

L











R

R

R

R

R

R

R

R

R

VRef

Vout

b2

b1

b0




Decoder-Based DAC



























3 2 1

1 2 33 2 1

2 4 8 2 2 2

Fout F ref ref In

In




= + + +LL

bull 4-bit example





















R-2R-based DAC


bull 4-bit example


11 1

_2 2 2

N Nref i R iF

R out F refi ii i


= =


sum sum













Current-mode DAC


ground potential

















across RF)









bull Glitches


















current sources












Examples of DAC 2





R-String DAC

R2

R2

R

R

R

R

R

R

R

b1b1

out

5

-19

b3b2b2 b3







ROM Decoder


Gamma Correction




Gamma Correction






Low noise






Output Buffer

DAC P

DAC N


OddOutput

EvenOutput

Gamma Voltage

(+)

Gamma Voltage

(-)

To data line

Rail to rail OP-AMP

-+

+-


Output Buffer

DAC P

negativebuffer


OddOutput

EvenOutput

Gamma Voltage

(+)

Gamma Voltage

(-)

To data line


PN type OP-AMP

DAC N

positivebuffer

+-

+-




Low deviation



Optimum OP AMP area



V1V2

+

-

Vss

Vdd

+

-+

-

Vout=Av(V1-V2)+

-





stage

High-gainstage

OutputBuffer


Bias Circuitry

Vout VoutrsquoV1V2





2


Ref P E Allen D R Holberg ldquoCMOS Analog Circuit Designrdquo 2nd Ed Oxford 2002 0 19598(上) NCHU EE 汪芳興 fansendragonnchuedutw


Hierarchy

Current to voltage

Current to voltage

voltage to current

voltage to current

conversion



(current mirror)





MOS diodeload


Class B (push-pull)

Currentstage

1stvoltagestage

2ndvoltagestage



Examples of Op-Amp





Design of Op Amp





1 Hand calculation









V-1005(L=1um)001(L=2um)

004(L=1um)001(L=2um)




Krsquo



symbol
















A(s)

F(s)

+

-ΣVin(s) Vout(s)

















need compensation




Z1 = gmIICC

CII gtgt CI CC



loop gain F(s)=1






and the RHP zero


C

m

C

mI

Cg

CgGB 2=cong

C

m

C

mI

m

II

mII

Cm

dsdsdsds

CmII

III

Cg

Cgz

Cg

Cgp

Cggggg

CgGGp

21

2

62

6

76421

))((

=cong

minus=

minuscong

++minus=

minuscong

Unit gain bandwidth






Cm

dsdsdsds

CmII

III

Cggggg

CgGGp

6

7642

1

))(( ++minus

=minus

cong








2

62 C

gCgp m

II

mII minus=

minuscong






VsCRsCgRV

sCRRV

sCRsCRgsV

CII

CmII

CII

II

CII

CIImout 1

)1(1

1

)1()( 66

+minusminus

=⎟⎟⎠

⎞⎜⎜⎝

⎛+

+⎟⎟⎠

⎞⎜⎜⎝

⎛+

minus=

Vrsquorsquo

Vout

VDD

CC

Vrsquo

++

--

M6

RII



IC1 IC2


VocOutput offset

between chip tochip




of gray m


Offset Cancellation

Voffset

VinVo=Vin+Voffset


Phase 1

Phase 2

Caz



Caz

Vo=Vin


+-

+ -

- +

- +

- +-+



Channel 384

Channel 383

Channel 382

Channel 381

Channel 4

Channel 3

Channel 2

Channel 1

Length

Height


Channel 420

Channel 419

Channel 418

Channel 417

Channel 4

Channel 3

Channel 2

Channel 1


Channel 480

Channel 479

Channel 478

Channel 477

Channel 4

Channel 3

Channel 2

Channel 1


resistor

Gammaresistor

Gammaresistor



TSMC HV Process




LCD Panel

Start pulse










dtdVCI times=

P = fdCloadVDD2

Turn on one clock




ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

clock

clock

Clock 2Clock 1

Clock 2Clock 1



Dual edge clocking

1 2 3 4

CK1XCK1CK2XCK2


Charge Sharing

To data line

DAC P


OddOutput

EvenOutput

OP

OPDAC NData

Data

Vgmama+

Vgmama-

-+

-+









CNS for Car

4~8mA

DSC Game PDA

2~3mA

05 ~ 2 mA

Mobile-phone


Large size panel









TV application


Outline









LCD TV Electronics

LCD Control Board


SDTV 720x480

cable


DCDC power




LCD Module

TTLLVDSTMDS

γ


OSD

Scaler

MCU

ADCAnalog

RGB

VideoDecoder

DigitalDVI

TMDSRx

De-interlace

Tuner

YC

SyncSep

Compositevideo

AntennaRF in

YCbCr

YPbPr



Digital TV System


MPEG2Decoder PODCI

32MB DDRSDRAM

Scaler IC







RESETRESET


SWITCHSWITCH



DiodesDiodes

LCDLCDDRIVERDRIVER


MICONMICON



INVERTERINVERTER


LCDLCDPANELPANEL

POWERAMPPOWERAMP




LA7585LA7585LA758788LA758788

LA7565LA7565


LA426061LA426061LA426570LA426570LA428082LA428082


LA7221LA7221









LA76818LA76818LA863228LA863228

FSS140132134FSS140132134CPH33043414CPH33043414


CPH5506CPH5506

LA426642674268LA426642674268LA427642774278LA427642774278








Black Insertion





DAC

γminus18R1 string

γminus22R2 string

γminus26R3 string

switch


Vref [118] Vout

8-bit Data


V0~V255




example



Over-8 bit data







Gn-1

Gn

Gray Level



Actual Response

Gn-1

Gn

Gray Level


Gn

Overdrive Response

Voltage by Driver







Overdrive Circuits

Memory

Lookup Table

Control ckts

Data

Dn

Dn+1

Ctrl

addressReadWrite

Datarsquo




ight

ness

Normal image

brig

htne

ss

bright imagebr

ight

ness


Other Technologies






LCD TV Trends


Size

BrightnessCR

Response Time

LCD Monitor

15-20rdquo

250400

25~16ms


Resolution XGA~UXGA

2002~2003

LCD TV


400~550500~700 gt550gt2k

25~16ms 16~12ms lt 8 ms

160160 176176


2004~2008

challenge

COST


Outline








TFTTFT



Controller025 μm

Sourcedriver05 μm


Gatedriver

06 μm HV



HV

Single chipHV

4 Chip TCPCOF Type

2 Chip COGCOF Type

1 Chip COG Type


HitachiSamsung

奇景聯詠

智寶科技







PWR SRAMGAMA64

APRSRAM

Gate Driver

PWR



18

64

18


Gate control

PowerSupplyCircuit

TimingGenerator

OSCSystem Interface


Indexregister

Controlregister

graylevelgenerator




Gammaadjusting

Addresscounter

VGHVGL

VgoffGVDDVGS

AVDD

18

G17

7G

176

G17

5 G

2G

1G

0

S396

S395

S394

S3 S2 S1

SPIC

ontrol

RW

Data

VDD3VDD

Latch circuitand

Vcom


Voltage Setting


VDD(20V ~ 33V)


VCI(25V ~ 33V)

BT2-0

BT2-0

VRH3-0

VREG2OUT

VCOM4-0

VGH(+9 ~ +165V)

AVDD(+35~ +55V)


VCL

VgoffH (to -50V)


VGL (-165 to -9V)

-1 times-1 times

VREG1OUT

VDV4-0

VCI1

VC2-0

VSS(0V)

VC3=1VRL3-0

GVDD(+30~ +50V)

VC3=0VRL3-0


Voltage Waveforms


sn(source output)

VCOM

Gn (Gate output)

VGH(+9 ~ +165V)


VgoffH (~to -50V)


GVDD(+30~ +50V)VDD(20V ~ 33V)

AVDD(+35~ +55V)

VSS(0V)






OVcomOUT


OVREG2OUT


OVREG1OUT


IOREGP





IOVCI



IOAVDD



-VDD

DescriptionIOSymbol




OVgoffL


OVgoffH



voltage

OVgoffOUT


IVgoff


higher than -150 V

OVGL



OVGH



OVcomL


OVcomH



IVcomR

DescriptionIOSymbol



mA2015-IVCI



by mode


Outputs


Outputs


Outputs





V5-3GVDD

V-5--16VGOFF

V-9--165VGL

V165-9VGH


V55-35AVDD

LCD Supply Voltage







Vcom


Vcom



Vgoff






V595583571VREG1OUT









VCI2

VCI VCI

VDDVSSVCIVSS

C7

int

VGL

VGH

C1VGH

C22P

C16


C11+

C1 5REGP

VCL

C31MVCI3

C22M

C12-C12+

C11-Vci1

VCIOUT

VCOMR

VGOFFOUT

VGOFFL

C20

C19

VCOMOUT

VCOMH

VREG1OUT

VREG2OUT

C 21

C 11


(Vgoffadjustment)


adjustment)

VcomHadjustment

circuit


circuit

GVDDoutput

amplifier

VcomHoutput

amplifier

VcomLoutput

amplifier

VgoffHoutput


amplifier


circuit

C12

C9GVDD

VGOFFH

C10

Voltageadjustment

circuitRegulator

Charge-pump

circuit 1

C23PC23M

C21M

Charge-pump

circuit 2

C21P

C31P Charge-pump

circuit 3

C41-Vci4

C41+ Charge-pump

circuit 4

REGN

C14C17

AVDD

C18

C4

C3

C2

C6

VC1

C5

C3


AVDD

VGL

GVDD

VCOML





GRAMMSB LSB

PKP00PKP01PKP02

PKP10PKP11PKP12

PKP20PKP21PKP22

PKP30PKP31PKP32

PKP40PKP41PKP42

PKP50PKP51PKP52

PRP00PRP01PRP02

PRP10PRP11PRP12

VRP00VRP01VRP02

VRP10VRP11VRP12

VRP03

VRP13VRP14

PKN00PKN01PKN02

PKN10PKN11PKN12

PKN20PKN21PKN22

PKN30PKN31PKN32

PKN40PKN41PKN42

PKN50PKN51PKN52

PRN00PRN01PRN02

PRN10PRN11PRN12

VRN00VRN01VRN02

VRN10VRN11VRN12

VRN03

VRN13VRN14



GrayscaleAm plifier


ltRgt

LCD driver

64 grayscalecontrol

ltG gt

LCD driver

64 grayscalecontrol

ltBgt

LCD driver

64

V1

V0

V63

6 6 6

R G BLCD


Scan Mode

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176


11


01

G176 G175 G174 G173 hellip G4 G3 G2 G110

G1 G2 G3 G4 hellip G173 G174 G175 G17600

Scan ModeGSSM

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176


A

B

C

D

A

B

C

D






33 3 3 3 54333








G V D D

V G S


V I N P N 0

V I N P N 1

V I N P N 2

V I N P N 3

V I N P N 4

V I N P N 5

V I N P N 6

V I N P N 7

V 0

V 6 3

V 6 2

V 5 5

V 4 3

V 2 0

V 8

V 1V 2V 3

V 9

V 2 1

V 4 4

V 5 6V 5 7





Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

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le V

olta

ge

Gra

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le V

olta

ge





8080Dummy Pad1195239742


Pad sizeum


UnitSize

Pad nameItems









Technology






25532V Process










Gat

e D

river

IC


Gat

e D

river

IC

T-Con

LTPS TFT-LCD


Source Driver IC

Gat

e D

river

IC

De-MUX






Outline









Digital vs Analog




TTL vs LVDS





XGA 325M (2 ports)

67M ( 1 port)

67M (2 ports)

SXGA 54M (2 ports)

54M (2 ports)

108M (2 ports)

Frequency

UXGA - 81M 162M LCD




6-bit ~80 ~60 ~50



RSDS Definition




8 Bit RGB RSDS Data

Start pulseR0 R1

R2 R3

R4 R5

G0 G1

G2 G3G4 G5

B0 B1

B2 B3

B4 B5

Invalid data

Invalid data

Invalid data

R6 R7

G6 G7

B6 B7



Single-end

FrontBack








Mini-LVDS

Data Bus Structure


Mini-LVDS

6 bit data 5 pairs


8 bit data 6 pairs

Mini-LVDS






TQFP100


RSDS vs Mini-LVDS













PPDSRSDSParameter



PPDSTM








PPDS Protocol





10-bit(1024灰階)


Memo





Digital Data Driver






lowhighcost






AnalogDigital



Latch Signal

Polarity Signal

Analog Part

Digital Part

To LCD data line

CLKDIO1

Out1 Out2 Out3 Outn

DIO2

HoldReg

Sample Reg

SR

Buffer

LevelShifter

HoldReg

Sample Reg

SR

Buffer

LevelShifter

HoldReg

Sample Reg

SR

Buffer

LevelShifter

HoldReg

Sample Reg

SR

Buffer

LevelShifter

HoldReg

SR

Buffer

LevelShifter

sample reg


Dat

are

ceiv

er


Datain

Output buffers

Level Shifter



Data latch

CLK

DIO1

128 CLKs


128 CLKs

DIO2

P1 P2 P3 P130P129P128P4 P5 P131 P132 P133P127





Tst

POL

Odd outputs


Positive

Tst

Vcom


LD

1K

15P

1K

15P

1K

15P

1K

15P

1K

15P

High-Z High-Z

High-Z

(CLK1)



sharing hellipetc)



720

7

4201680x3WSXGA+7206424801920x3HDTV

4804321440x3WXGA

4141366x3WXGA

512

402

12

480

420

38431224019210 9

1400x3SXGA+

1600x3UXGA

2048x3QXGA











Horizontal period

Pixel frequency

Horizontal period

Pixel frequency




DA Converter









Idea DA Converter


1 2 011 2 12 2 2 2

n nin n n








1 2 011 2 1

2 2 2 2

2


refLSB N

b b bbV V L V B

VV

minus minusminus

⎛ ⎞= + + + + = times⎜ ⎟⎝ ⎠




















Offset Error



2-bit example

00( ) outoff

LSB

VE DAC V=






LSB LSB

V VEV V





Accuracy



error


removed










DA Converter









bull Glitches






Decoder-based

Binary-weighted

Thermometer-code

Hybrid



Decoder-Based DAC








Decoder-Based DAC






R

R

R

R

R

R

R

R

R

b0 b0

b1 b1

b2

b2

Vout

VRef

2N resistors

Bin = b22-1+b12-2+b02-3


















( 1) (2 3 )

tr tr tr tr tr tr

tr tr

R C R C N R C

N N R C


= + sdot

L











R

R

R

R

R

R

R

R

R

VRef

Vout

b2

b1

b0




Decoder-Based DAC



























3 2 1

1 2 33 2 1

2 4 8 2 2 2

Fout F ref ref In

In




= + + +LL

bull 4-bit example





















R-2R-based DAC


bull 4-bit example


11 1

_2 2 2

N Nref i R iF

R out F refi ii i


= =


sum sum













Current-mode DAC


ground potential

















across RF)









bull Glitches


















current sources












Examples of DAC 2





R-String DAC

R2

R2

R

R

R

R

R

R

R

b1b1

out

5

-19

b3b2b2 b3







ROM Decoder


Gamma Correction




Gamma Correction






Low noise






Output Buffer

DAC P

DAC N


OddOutput

EvenOutput

Gamma Voltage

(+)

Gamma Voltage

(-)

To data line

Rail to rail OP-AMP

-+

+-


Output Buffer

DAC P

negativebuffer


OddOutput

EvenOutput

Gamma Voltage

(+)

Gamma Voltage

(-)

To data line


PN type OP-AMP

DAC N

positivebuffer

+-

+-




Low deviation



Optimum OP AMP area



V1V2

+

-

Vss

Vdd

+

-+

-

Vout=Av(V1-V2)+

-





stage

High-gainstage

OutputBuffer


Bias Circuitry

Vout VoutrsquoV1V2





2




Hierarchy

Current to voltage

Current to voltage

voltage to current

voltage to current

conversion



(current mirror)





MOS diodeload


Class B (push-pull)

Currentstage

1stvoltagestage

2ndvoltagestage



Examples of Op-Amp





Design of Op Amp





1 Hand calculation









V-1005(L=1um)001(L=2um)

004(L=1um)001(L=2um)




Krsquo



symbol
















A(s)

F(s)

+

-ΣVin(s) Vout(s)

















need compensation




Z1 = gmIICC

CII gtgt CI CC



loop gain F(s)=1






and the RHP zero


C

m

C

mI

Cg

CgGB 2=cong

C

m

C

mI

m

II

mII

Cm

dsdsdsds

CmII

III

Cg

Cgz

Cg

Cgp

Cggggg

CgGGp

21

2

62

6

76421

))((

=cong

minus=

minuscong

++minus=

minuscong

Unit gain bandwidth






Cm

dsdsdsds

CmII

III

Cggggg

CgGGp

6

7642

1

))(( ++minus

=minus

cong








2

62 C

gCgp m

II

mII minus=

minuscong






VsCRsCgRV

sCRRV

sCRsCRgsV

CII

CmII

CII

II

CII

CIImout 1

)1(1

1

)1()( 66

+minusminus

=⎟⎟⎠

⎞⎜⎜⎝

⎛+

+⎟⎟⎠

⎞⎜⎜⎝

⎛+

minus=

Vrsquorsquo

Vout

VDD

CC

Vrsquo

++

--

M6

RII



IC1 IC2


VocOutput offset

between chip tochip




of gray m


Offset Cancellation

Voffset

VinVo=Vin+Voffset


Phase 1

Phase 2

Caz



Caz

Vo=Vin


+-

+ -

- +

- +

- +-+



Channel 384

Channel 383

Channel 382

Channel 381

Channel 4

Channel 3

Channel 2

Channel 1

Length

Height


Channel 420

Channel 419

Channel 418

Channel 417

Channel 4

Channel 3

Channel 2

Channel 1


Channel 480

Channel 479

Channel 478

Channel 477

Channel 4

Channel 3

Channel 2

Channel 1


resistor

Gammaresistor

Gammaresistor



TSMC HV Process




LCD Panel

Start pulse










dtdVCI times=

P = fdCloadVDD2

Turn on one clock




ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

clock

clock

Clock 2Clock 1

Clock 2Clock 1



Dual edge clocking

1 2 3 4

CK1XCK1CK2XCK2


Charge Sharing

To data line

DAC P


OddOutput

EvenOutput

OP

OPDAC NData

Data

Vgmama+

Vgmama-

-+

-+









CNS for Car

4~8mA

DSC Game PDA

2~3mA

05 ~ 2 mA

Mobile-phone


Large size panel









TV application


Outline









LCD TV Electronics

LCD Control Board


SDTV 720x480

cable


DCDC power




LCD Module

TTLLVDSTMDS

γ


OSD

Scaler

MCU

ADCAnalog

RGB

VideoDecoder

DigitalDVI

TMDSRx

De-interlace

Tuner

YC

SyncSep

Compositevideo

AntennaRF in

YCbCr

YPbPr



Digital TV System


MPEG2Decoder PODCI

32MB DDRSDRAM

Scaler IC







RESETRESET


SWITCHSWITCH



DiodesDiodes

LCDLCDDRIVERDRIVER


MICONMICON



INVERTERINVERTER


LCDLCDPANELPANEL

POWERAMPPOWERAMP




LA7585LA7585LA758788LA758788

LA7565LA7565


LA426061LA426061LA426570LA426570LA428082LA428082


LA7221LA7221









LA76818LA76818LA863228LA863228

FSS140132134FSS140132134CPH33043414CPH33043414


CPH5506CPH5506

LA426642674268LA426642674268LA427642774278LA427642774278








Black Insertion





DAC

γminus18R1 string

γminus22R2 string

γminus26R3 string

switch


Vref [118] Vout

8-bit Data


V0~V255




example



Over-8 bit data







Gn-1

Gn

Gray Level



Actual Response

Gn-1

Gn

Gray Level


Gn

Overdrive Response

Voltage by Driver







Overdrive Circuits

Memory

Lookup Table

Control ckts

Data

Dn

Dn+1

Ctrl

addressReadWrite

Datarsquo




ight

ness

Normal image

brig

htne

ss

bright imagebr

ight

ness


Other Technologies






LCD TV Trends


Size

BrightnessCR

Response Time

LCD Monitor

15-20rdquo

250400

25~16ms


Resolution XGA~UXGA

2002~2003

LCD TV


400~550500~700 gt550gt2k

25~16ms 16~12ms lt 8 ms

160160 176176


2004~2008

challenge

COST


Outline








TFTTFT



Controller025 μm

Sourcedriver05 μm


Gatedriver

06 μm HV



HV

Single chipHV

4 Chip TCPCOF Type

2 Chip COGCOF Type

1 Chip COG Type


HitachiSamsung

奇景聯詠

智寶科技







PWR SRAMGAMA64

APRSRAM

Gate Driver

PWR



18

64

18


Gate control

PowerSupplyCircuit

TimingGenerator

OSCSystem Interface


Indexregister

Controlregister

graylevelgenerator




Gammaadjusting

Addresscounter

VGHVGL

VgoffGVDDVGS

AVDD

18

G17

7G

176

G17

5 G

2G

1G

0

S396

S395

S394

S3 S2 S1

SPIC

ontrol

RW

Data

VDD3VDD

Latch circuitand

Vcom


Voltage Setting


VDD(20V ~ 33V)


VCI(25V ~ 33V)

BT2-0

BT2-0

VRH3-0

VREG2OUT

VCOM4-0

VGH(+9 ~ +165V)

AVDD(+35~ +55V)


VCL

VgoffH (to -50V)


VGL (-165 to -9V)

-1 times-1 times

VREG1OUT

VDV4-0

VCI1

VC2-0

VSS(0V)

VC3=1VRL3-0

GVDD(+30~ +50V)

VC3=0VRL3-0


Voltage Waveforms


sn(source output)

VCOM

Gn (Gate output)

VGH(+9 ~ +165V)


VgoffH (~to -50V)


GVDD(+30~ +50V)VDD(20V ~ 33V)

AVDD(+35~ +55V)

VSS(0V)






OVcomOUT


OVREG2OUT


OVREG1OUT


IOREGP





IOVCI



IOAVDD



-VDD

DescriptionIOSymbol




OVgoffL


OVgoffH



voltage

OVgoffOUT


IVgoff


higher than -150 V

OVGL



OVGH



OVcomL


OVcomH



IVcomR

DescriptionIOSymbol



mA2015-IVCI



by mode


Outputs


Outputs


Outputs





V5-3GVDD

V-5--16VGOFF

V-9--165VGL

V165-9VGH


V55-35AVDD

LCD Supply Voltage







Vcom


Vcom



Vgoff






V595583571VREG1OUT









VCI2

VCI VCI

VDDVSSVCIVSS

C7

int

VGL

VGH

C1VGH

C22P

C16


C11+

C1 5REGP

VCL

C31MVCI3

C22M

C12-C12+

C11-Vci1

VCIOUT

VCOMR

VGOFFOUT

VGOFFL

C20

C19

VCOMOUT

VCOMH

VREG1OUT

VREG2OUT

C 21

C 11


(Vgoffadjustment)


adjustment)

VcomHadjustment

circuit


circuit

GVDDoutput

amplifier

VcomHoutput

amplifier

VcomLoutput

amplifier

VgoffHoutput


amplifier


circuit

C12

C9GVDD

VGOFFH

C10

Voltageadjustment

circuitRegulator

Charge-pump

circuit 1

C23PC23M

C21M

Charge-pump

circuit 2

C21P

C31P Charge-pump

circuit 3

C41-Vci4

C41+ Charge-pump

circuit 4

REGN

C14C17

AVDD

C18

C4

C3

C2

C6

VC1

C5

C3


AVDD

VGL

GVDD

VCOML





GRAMMSB LSB

PKP00PKP01PKP02

PKP10PKP11PKP12

PKP20PKP21PKP22

PKP30PKP31PKP32

PKP40PKP41PKP42

PKP50PKP51PKP52

PRP00PRP01PRP02

PRP10PRP11PRP12

VRP00VRP01VRP02

VRP10VRP11VRP12

VRP03

VRP13VRP14

PKN00PKN01PKN02

PKN10PKN11PKN12

PKN20PKN21PKN22

PKN30PKN31PKN32

PKN40PKN41PKN42

PKN50PKN51PKN52

PRN00PRN01PRN02

PRN10PRN11PRN12

VRN00VRN01VRN02

VRN10VRN11VRN12

VRN03

VRN13VRN14



GrayscaleAm plifier


ltRgt

LCD driver

64 grayscalecontrol

ltG gt

LCD driver

64 grayscalecontrol

ltBgt

LCD driver

64

V1

V0

V63

6 6 6

R G BLCD


Scan Mode

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176


11


01

G176 G175 G174 G173 hellip G4 G3 G2 G110

G1 G2 G3 G4 hellip G173 G174 G175 G17600

Scan ModeGSSM

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176


A

B

C

D

A

B

C

D






33 3 3 3 54333








G V D D

V G S


V I N P N 0

V I N P N 1

V I N P N 2

V I N P N 3

V I N P N 4

V I N P N 5

V I N P N 6

V I N P N 7

V 0

V 6 3

V 6 2

V 5 5

V 4 3

V 2 0

V 8

V 1V 2V 3

V 9

V 2 1

V 4 4

V 5 6V 5 7





Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge





8080Dummy Pad1195239742


Pad sizeum


UnitSize

Pad nameItems









Technology






25532V Process










Gat

e D

river

IC


Gat

e D

river

IC

T-Con

LTPS TFT-LCD


Source Driver IC

Gat

e D

river

IC

De-MUX






Outline









Digital vs Analog




TTL vs LVDS





XGA 325M (2 ports)

67M ( 1 port)

67M (2 ports)

SXGA 54M (2 ports)

54M (2 ports)

108M (2 ports)

Frequency

UXGA - 81M 162M LCD




6-bit ~80 ~60 ~50



RSDS Definition




8 Bit RGB RSDS Data

Start pulseR0 R1

R2 R3

R4 R5

G0 G1

G2 G3G4 G5

B0 B1

B2 B3

B4 B5

Invalid data

Invalid data

Invalid data

R6 R7

G6 G7

B6 B7



Single-end

FrontBack








Mini-LVDS

Data Bus Structure


Mini-LVDS

6 bit data 5 pairs


8 bit data 6 pairs

Mini-LVDS






TQFP100


RSDS vs Mini-LVDS













PPDSRSDSParameter



PPDSTM








PPDS Protocol





10-bit(1024灰階)


Memo



Data latch

CLK

DIO1

128 CLKs


128 CLKs

DIO2

P1 P2 P3 P130P129P128P4 P5 P131 P132 P133P127





Tst

POL

Odd outputs


Positive

Tst

Vcom


LD

1K

15P

1K

15P

1K

15P

1K

15P

1K

15P

High-Z High-Z

High-Z

(CLK1)



sharing hellipetc)



720

7

4201680x3WSXGA+7206424801920x3HDTV

4804321440x3WXGA

4141366x3WXGA

512

402

12

480

420

38431224019210 9

1400x3SXGA+

1600x3UXGA

2048x3QXGA











Horizontal period

Pixel frequency

Horizontal period

Pixel frequency




DA Converter









Idea DA Converter


1 2 011 2 12 2 2 2

n nin n n








1 2 011 2 1

2 2 2 2

2


refLSB N

b b bbV V L V B

VV

minus minusminus

⎛ ⎞= + + + + = times⎜ ⎟⎝ ⎠




















Offset Error



2-bit example

00( ) outoff

LSB

VE DAC V=






LSB LSB

V VEV V





Accuracy



error


removed










DA Converter









bull Glitches






Decoder-based

Binary-weighted

Thermometer-code

Hybrid



Decoder-Based DAC








Decoder-Based DAC






R

R

R

R

R

R

R

R

R

b0 b0

b1 b1

b2

b2

Vout

VRef

2N resistors

Bin = b22-1+b12-2+b02-3


















( 1) (2 3 )

tr tr tr tr tr tr

tr tr

R C R C N R C

N N R C


= + sdot

L











R

R

R

R

R

R

R

R

R

VRef

Vout

b2

b1

b0




Decoder-Based DAC



























3 2 1

1 2 33 2 1

2 4 8 2 2 2

Fout F ref ref In

In




= + + +LL

bull 4-bit example





















R-2R-based DAC


bull 4-bit example


11 1

_2 2 2

N Nref i R iF

R out F refi ii i


= =


sum sum













Current-mode DAC


ground potential

















across RF)









bull Glitches


















current sources












Examples of DAC 2





R-String DAC

R2

R2

R

R

R

R

R

R

R

b1b1

out

5

-19

b3b2b2 b3







ROM Decoder


Gamma Correction




Gamma Correction






Low noise






Output Buffer

DAC P

DAC N


OddOutput

EvenOutput

Gamma Voltage

(+)

Gamma Voltage

(-)

To data line

Rail to rail OP-AMP

-+

+-


Output Buffer

DAC P

negativebuffer


OddOutput

EvenOutput

Gamma Voltage

(+)

Gamma Voltage

(-)

To data line


PN type OP-AMP

DAC N

positivebuffer

+-

+-




Low deviation



Optimum OP AMP area



V1V2

+

-

Vss

Vdd

+

-+

-

Vout=Av(V1-V2)+

-





stage

High-gainstage

OutputBuffer


Bias Circuitry

Vout VoutrsquoV1V2





2




Hierarchy

Current to voltage

Current to voltage

voltage to current

voltage to current

conversion



(current mirror)





MOS diodeload


Class B (push-pull)

Currentstage

1stvoltagestage

2ndvoltagestage



Examples of Op-Amp





Design of Op Amp





1 Hand calculation









V-1005(L=1um)001(L=2um)

004(L=1um)001(L=2um)




Krsquo



symbol
















A(s)

F(s)

+

-ΣVin(s) Vout(s)

















need compensation




Z1 = gmIICC

CII gtgt CI CC



loop gain F(s)=1






and the RHP zero


C

m

C

mI

Cg

CgGB 2=cong

C

m

C

mI

m

II

mII

Cm

dsdsdsds

CmII

III

Cg

Cgz

Cg

Cgp

Cggggg

CgGGp

21

2

62

6

76421

))((

=cong

minus=

minuscong

++minus=

minuscong

Unit gain bandwidth






Cm

dsdsdsds

CmII

III

Cggggg

CgGGp

6

7642

1

))(( ++minus

=minus

cong








2

62 C

gCgp m

II

mII minus=

minuscong






VsCRsCgRV

sCRRV

sCRsCRgsV

CII

CmII

CII

II

CII

CIImout 1

)1(1

1

)1()( 66

+minusminus

=⎟⎟⎠

⎞⎜⎜⎝

⎛+

+⎟⎟⎠

⎞⎜⎜⎝

⎛+

minus=

Vrsquorsquo

Vout

VDD

CC

Vrsquo

++

--

M6

RII



IC1 IC2


VocOutput offset

between chip tochip




of gray m


Offset Cancellation

Voffset

VinVo=Vin+Voffset


Phase 1

Phase 2

Caz



Caz

Vo=Vin


+-

+ -

- +

- +

- +-+



Channel 384

Channel 383

Channel 382

Channel 381

Channel 4

Channel 3

Channel 2

Channel 1

Length

Height


Channel 420

Channel 419

Channel 418

Channel 417

Channel 4

Channel 3

Channel 2

Channel 1


Channel 480

Channel 479

Channel 478

Channel 477

Channel 4

Channel 3

Channel 2

Channel 1


resistor

Gammaresistor

Gammaresistor



TSMC HV Process




LCD Panel

Start pulse










dtdVCI times=

P = fdCloadVDD2

Turn on one clock




ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

clock

clock

Clock 2Clock 1

Clock 2Clock 1



Dual edge clocking

1 2 3 4

CK1XCK1CK2XCK2


Charge Sharing

To data line

DAC P


OddOutput

EvenOutput

OP

OPDAC NData

Data

Vgmama+

Vgmama-

-+

-+









CNS for Car

4~8mA

DSC Game PDA

2~3mA

05 ~ 2 mA

Mobile-phone


Large size panel









TV application


Outline









LCD TV Electronics

LCD Control Board


SDTV 720x480

cable


DCDC power




LCD Module

TTLLVDSTMDS

γ


OSD

Scaler

MCU

ADCAnalog

RGB

VideoDecoder

DigitalDVI

TMDSRx

De-interlace

Tuner

YC

SyncSep

Compositevideo

AntennaRF in

YCbCr

YPbPr



Digital TV System


MPEG2Decoder PODCI

32MB DDRSDRAM

Scaler IC







RESETRESET


SWITCHSWITCH



DiodesDiodes

LCDLCDDRIVERDRIVER


MICONMICON



INVERTERINVERTER


LCDLCDPANELPANEL

POWERAMPPOWERAMP




LA7585LA7585LA758788LA758788

LA7565LA7565


LA426061LA426061LA426570LA426570LA428082LA428082


LA7221LA7221









LA76818LA76818LA863228LA863228

FSS140132134FSS140132134CPH33043414CPH33043414


CPH5506CPH5506

LA426642674268LA426642674268LA427642774278LA427642774278








Black Insertion





DAC

γminus18R1 string

γminus22R2 string

γminus26R3 string

switch


Vref [118] Vout

8-bit Data


V0~V255




example



Over-8 bit data







Gn-1

Gn

Gray Level



Actual Response

Gn-1

Gn

Gray Level


Gn

Overdrive Response

Voltage by Driver







Overdrive Circuits

Memory

Lookup Table

Control ckts

Data

Dn

Dn+1

Ctrl

addressReadWrite

Datarsquo




ight

ness

Normal image

brig

htne

ss

bright imagebr

ight

ness


Other Technologies






LCD TV Trends


Size

BrightnessCR

Response Time

LCD Monitor

15-20rdquo

250400

25~16ms


Resolution XGA~UXGA

2002~2003

LCD TV


400~550500~700 gt550gt2k

25~16ms 16~12ms lt 8 ms

160160 176176


2004~2008

challenge

COST


Outline








TFTTFT



Controller025 μm

Sourcedriver05 μm


Gatedriver

06 μm HV



HV

Single chipHV

4 Chip TCPCOF Type

2 Chip COGCOF Type

1 Chip COG Type


HitachiSamsung

奇景聯詠

智寶科技







PWR SRAMGAMA64

APRSRAM

Gate Driver

PWR



18

64

18


Gate control

PowerSupplyCircuit

TimingGenerator

OSCSystem Interface


Indexregister

Controlregister

graylevelgenerator




Gammaadjusting

Addresscounter

VGHVGL

VgoffGVDDVGS

AVDD

18

G17

7G

176

G17

5 G

2G

1G

0

S396

S395

S394

S3 S2 S1

SPIC

ontrol

RW

Data

VDD3VDD

Latch circuitand

Vcom


Voltage Setting


VDD(20V ~ 33V)


VCI(25V ~ 33V)

BT2-0

BT2-0

VRH3-0

VREG2OUT

VCOM4-0

VGH(+9 ~ +165V)

AVDD(+35~ +55V)


VCL

VgoffH (to -50V)


VGL (-165 to -9V)

-1 times-1 times

VREG1OUT

VDV4-0

VCI1

VC2-0

VSS(0V)

VC3=1VRL3-0

GVDD(+30~ +50V)

VC3=0VRL3-0


Voltage Waveforms


sn(source output)

VCOM

Gn (Gate output)

VGH(+9 ~ +165V)


VgoffH (~to -50V)


GVDD(+30~ +50V)VDD(20V ~ 33V)

AVDD(+35~ +55V)

VSS(0V)






OVcomOUT


OVREG2OUT


OVREG1OUT


IOREGP





IOVCI



IOAVDD



-VDD

DescriptionIOSymbol




OVgoffL


OVgoffH



voltage

OVgoffOUT


IVgoff


higher than -150 V

OVGL



OVGH



OVcomL


OVcomH



IVcomR

DescriptionIOSymbol



mA2015-IVCI



by mode


Outputs


Outputs


Outputs





V5-3GVDD

V-5--16VGOFF

V-9--165VGL

V165-9VGH


V55-35AVDD

LCD Supply Voltage







Vcom


Vcom



Vgoff






V595583571VREG1OUT









VCI2

VCI VCI

VDDVSSVCIVSS

C7

int

VGL

VGH

C1VGH

C22P

C16


C11+

C1 5REGP

VCL

C31MVCI3

C22M

C12-C12+

C11-Vci1

VCIOUT

VCOMR

VGOFFOUT

VGOFFL

C20

C19

VCOMOUT

VCOMH

VREG1OUT

VREG2OUT

C 21

C 11


(Vgoffadjustment)


adjustment)

VcomHadjustment

circuit


circuit

GVDDoutput

amplifier

VcomHoutput

amplifier

VcomLoutput

amplifier

VgoffHoutput


amplifier


circuit

C12

C9GVDD

VGOFFH

C10

Voltageadjustment

circuitRegulator

Charge-pump

circuit 1

C23PC23M

C21M

Charge-pump

circuit 2

C21P

C31P Charge-pump

circuit 3

C41-Vci4

C41+ Charge-pump

circuit 4

REGN

C14C17

AVDD

C18

C4

C3

C2

C6

VC1

C5

C3


AVDD

VGL

GVDD

VCOML





GRAMMSB LSB

PKP00PKP01PKP02

PKP10PKP11PKP12

PKP20PKP21PKP22

PKP30PKP31PKP32

PKP40PKP41PKP42

PKP50PKP51PKP52

PRP00PRP01PRP02

PRP10PRP11PRP12

VRP00VRP01VRP02

VRP10VRP11VRP12

VRP03

VRP13VRP14

PKN00PKN01PKN02

PKN10PKN11PKN12

PKN20PKN21PKN22

PKN30PKN31PKN32

PKN40PKN41PKN42

PKN50PKN51PKN52

PRN00PRN01PRN02

PRN10PRN11PRN12

VRN00VRN01VRN02

VRN10VRN11VRN12

VRN03

VRN13VRN14



GrayscaleAm plifier


ltRgt

LCD driver

64 grayscalecontrol

ltG gt

LCD driver

64 grayscalecontrol

ltBgt

LCD driver

64

V1

V0

V63

6 6 6

R G BLCD


Scan Mode

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176


11


01

G176 G175 G174 G173 hellip G4 G3 G2 G110

G1 G2 G3 G4 hellip G173 G174 G175 G17600

Scan ModeGSSM

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176


A

B

C

D

A

B

C

D






33 3 3 3 54333








G V D D

V G S


V I N P N 0

V I N P N 1

V I N P N 2

V I N P N 3

V I N P N 4

V I N P N 5

V I N P N 6

V I N P N 7

V 0

V 6 3

V 6 2

V 5 5

V 4 3

V 2 0

V 8

V 1V 2V 3

V 9

V 2 1

V 4 4

V 5 6V 5 7





Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge





8080Dummy Pad1195239742


Pad sizeum


UnitSize

Pad nameItems









Technology






25532V Process










Gat

e D

river

IC


Gat

e D

river

IC

T-Con

LTPS TFT-LCD


Source Driver IC

Gat

e D

river

IC

De-MUX






Outline









Digital vs Analog




TTL vs LVDS





XGA 325M (2 ports)

67M ( 1 port)

67M (2 ports)

SXGA 54M (2 ports)

54M (2 ports)

108M (2 ports)

Frequency

UXGA - 81M 162M LCD




6-bit ~80 ~60 ~50



RSDS Definition




8 Bit RGB RSDS Data

Start pulseR0 R1

R2 R3

R4 R5

G0 G1

G2 G3G4 G5

B0 B1

B2 B3

B4 B5

Invalid data

Invalid data

Invalid data

R6 R7

G6 G7

B6 B7



Single-end

FrontBack








Mini-LVDS

Data Bus Structure


Mini-LVDS

6 bit data 5 pairs


8 bit data 6 pairs

Mini-LVDS






TQFP100


RSDS vs Mini-LVDS













PPDSRSDSParameter



PPDSTM








PPDS Protocol





10-bit(1024灰階)


Memo








Horizontal period

Pixel frequency

Horizontal period

Pixel frequency




DA Converter









Idea DA Converter


1 2 011 2 12 2 2 2

n nin n n








1 2 011 2 1

2 2 2 2

2


refLSB N

b b bbV V L V B

VV

minus minusminus

⎛ ⎞= + + + + = times⎜ ⎟⎝ ⎠




















Offset Error



2-bit example

00( ) outoff

LSB

VE DAC V=






LSB LSB

V VEV V





Accuracy



error


removed










DA Converter









bull Glitches






Decoder-based

Binary-weighted

Thermometer-code

Hybrid



Decoder-Based DAC








Decoder-Based DAC






R

R

R

R

R

R

R

R

R

b0 b0

b1 b1

b2

b2

Vout

VRef

2N resistors

Bin = b22-1+b12-2+b02-3


















( 1) (2 3 )

tr tr tr tr tr tr

tr tr

R C R C N R C

N N R C


= + sdot

L











R

R

R

R

R

R

R

R

R

VRef

Vout

b2

b1

b0




Decoder-Based DAC



























3 2 1

1 2 33 2 1

2 4 8 2 2 2

Fout F ref ref In

In




= + + +LL

bull 4-bit example





















R-2R-based DAC


bull 4-bit example


11 1

_2 2 2

N Nref i R iF

R out F refi ii i


= =


sum sum













Current-mode DAC


ground potential

















across RF)









bull Glitches


















current sources












Examples of DAC 2





R-String DAC

R2

R2

R

R

R

R

R

R

R

b1b1

out

5

-19

b3b2b2 b3







ROM Decoder


Gamma Correction




Gamma Correction






Low noise






Output Buffer

DAC P

DAC N


OddOutput

EvenOutput

Gamma Voltage

(+)

Gamma Voltage

(-)

To data line

Rail to rail OP-AMP

-+

+-


Output Buffer

DAC P

negativebuffer


OddOutput

EvenOutput

Gamma Voltage

(+)

Gamma Voltage

(-)

To data line


PN type OP-AMP

DAC N

positivebuffer

+-

+-




Low deviation



Optimum OP AMP area



V1V2

+

-

Vss

Vdd

+

-+

-

Vout=Av(V1-V2)+

-





stage

High-gainstage

OutputBuffer


Bias Circuitry

Vout VoutrsquoV1V2





2




Hierarchy

Current to voltage

Current to voltage

voltage to current

voltage to current

conversion



(current mirror)





MOS diodeload


Class B (push-pull)

Currentstage

1stvoltagestage

2ndvoltagestage



Examples of Op-Amp





Design of Op Amp





1 Hand calculation









V-1005(L=1um)001(L=2um)

004(L=1um)001(L=2um)




Krsquo



symbol
















A(s)

F(s)

+

-ΣVin(s) Vout(s)

















need compensation




Z1 = gmIICC

CII gtgt CI CC



loop gain F(s)=1






and the RHP zero


C

m

C

mI

Cg

CgGB 2=cong

C

m

C

mI

m

II

mII

Cm

dsdsdsds

CmII

III

Cg

Cgz

Cg

Cgp

Cggggg

CgGGp

21

2

62

6

76421

))((

=cong

minus=

minuscong

++minus=

minuscong

Unit gain bandwidth






Cm

dsdsdsds

CmII

III

Cggggg

CgGGp

6

7642

1

))(( ++minus

=minus

cong








2

62 C

gCgp m

II

mII minus=

minuscong






VsCRsCgRV

sCRRV

sCRsCRgsV

CII

CmII

CII

II

CII

CIImout 1

)1(1

1

)1()( 66

+minusminus

=⎟⎟⎠

⎞⎜⎜⎝

⎛+

+⎟⎟⎠

⎞⎜⎜⎝

⎛+

minus=

Vrsquorsquo

Vout

VDD

CC

Vrsquo

++

--

M6

RII



IC1 IC2


VocOutput offset

between chip tochip




of gray m


Offset Cancellation

Voffset

VinVo=Vin+Voffset


Phase 1

Phase 2

Caz



Caz

Vo=Vin


+-

+ -

- +

- +

- +-+



Channel 384

Channel 383

Channel 382

Channel 381

Channel 4

Channel 3

Channel 2

Channel 1

Length

Height


Channel 420

Channel 419

Channel 418

Channel 417

Channel 4

Channel 3

Channel 2

Channel 1


Channel 480

Channel 479

Channel 478

Channel 477

Channel 4

Channel 3

Channel 2

Channel 1


resistor

Gammaresistor

Gammaresistor



TSMC HV Process




LCD Panel

Start pulse










dtdVCI times=

P = fdCloadVDD2

Turn on one clock




ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

clock

clock

Clock 2Clock 1

Clock 2Clock 1



Dual edge clocking

1 2 3 4

CK1XCK1CK2XCK2


Charge Sharing

To data line

DAC P


OddOutput

EvenOutput

OP

OPDAC NData

Data

Vgmama+

Vgmama-

-+

-+









CNS for Car

4~8mA

DSC Game PDA

2~3mA

05 ~ 2 mA

Mobile-phone


Large size panel









TV application


Outline









LCD TV Electronics

LCD Control Board


SDTV 720x480

cable


DCDC power




LCD Module

TTLLVDSTMDS

γ


OSD

Scaler

MCU

ADCAnalog

RGB

VideoDecoder

DigitalDVI

TMDSRx

De-interlace

Tuner

YC

SyncSep

Compositevideo

AntennaRF in

YCbCr

YPbPr



Digital TV System


MPEG2Decoder PODCI

32MB DDRSDRAM

Scaler IC







RESETRESET


SWITCHSWITCH



DiodesDiodes

LCDLCDDRIVERDRIVER


MICONMICON



INVERTERINVERTER


LCDLCDPANELPANEL

POWERAMPPOWERAMP




LA7585LA7585LA758788LA758788

LA7565LA7565


LA426061LA426061LA426570LA426570LA428082LA428082


LA7221LA7221









LA76818LA76818LA863228LA863228

FSS140132134FSS140132134CPH33043414CPH33043414


CPH5506CPH5506

LA426642674268LA426642674268LA427642774278LA427642774278








Black Insertion





DAC

γminus18R1 string

γminus22R2 string

γminus26R3 string

switch


Vref [118] Vout

8-bit Data


V0~V255




example



Over-8 bit data







Gn-1

Gn

Gray Level



Actual Response

Gn-1

Gn

Gray Level


Gn

Overdrive Response

Voltage by Driver







Overdrive Circuits

Memory

Lookup Table

Control ckts

Data

Dn

Dn+1

Ctrl

addressReadWrite

Datarsquo




ight

ness

Normal image

brig

htne

ss

bright imagebr

ight

ness


Other Technologies






LCD TV Trends


Size

BrightnessCR

Response Time

LCD Monitor

15-20rdquo

250400

25~16ms


Resolution XGA~UXGA

2002~2003

LCD TV


400~550500~700 gt550gt2k

25~16ms 16~12ms lt 8 ms

160160 176176


2004~2008

challenge

COST


Outline








TFTTFT



Controller025 μm

Sourcedriver05 μm


Gatedriver

06 μm HV



HV

Single chipHV

4 Chip TCPCOF Type

2 Chip COGCOF Type

1 Chip COG Type


HitachiSamsung

奇景聯詠

智寶科技







PWR SRAMGAMA64

APRSRAM

Gate Driver

PWR



18

64

18


Gate control

PowerSupplyCircuit

TimingGenerator

OSCSystem Interface


Indexregister

Controlregister

graylevelgenerator




Gammaadjusting

Addresscounter

VGHVGL

VgoffGVDDVGS

AVDD

18

G17

7G

176

G17

5 G

2G

1G

0

S396

S395

S394

S3 S2 S1

SPIC

ontrol

RW

Data

VDD3VDD

Latch circuitand

Vcom


Voltage Setting


VDD(20V ~ 33V)


VCI(25V ~ 33V)

BT2-0

BT2-0

VRH3-0

VREG2OUT

VCOM4-0

VGH(+9 ~ +165V)

AVDD(+35~ +55V)


VCL

VgoffH (to -50V)


VGL (-165 to -9V)

-1 times-1 times

VREG1OUT

VDV4-0

VCI1

VC2-0

VSS(0V)

VC3=1VRL3-0

GVDD(+30~ +50V)

VC3=0VRL3-0


Voltage Waveforms


sn(source output)

VCOM

Gn (Gate output)

VGH(+9 ~ +165V)


VgoffH (~to -50V)


GVDD(+30~ +50V)VDD(20V ~ 33V)

AVDD(+35~ +55V)

VSS(0V)






OVcomOUT


OVREG2OUT


OVREG1OUT


IOREGP





IOVCI



IOAVDD



-VDD

DescriptionIOSymbol




OVgoffL


OVgoffH



voltage

OVgoffOUT


IVgoff


higher than -150 V

OVGL



OVGH



OVcomL


OVcomH



IVcomR

DescriptionIOSymbol



mA2015-IVCI



by mode


Outputs


Outputs


Outputs





V5-3GVDD

V-5--16VGOFF

V-9--165VGL

V165-9VGH


V55-35AVDD

LCD Supply Voltage







Vcom


Vcom



Vgoff






V595583571VREG1OUT









VCI2

VCI VCI

VDDVSSVCIVSS

C7

int

VGL

VGH

C1VGH

C22P

C16


C11+

C1 5REGP

VCL

C31MVCI3

C22M

C12-C12+

C11-Vci1

VCIOUT

VCOMR

VGOFFOUT

VGOFFL

C20

C19

VCOMOUT

VCOMH

VREG1OUT

VREG2OUT

C 21

C 11


(Vgoffadjustment)


adjustment)

VcomHadjustment

circuit


circuit

GVDDoutput

amplifier

VcomHoutput

amplifier

VcomLoutput

amplifier

VgoffHoutput


amplifier


circuit

C12

C9GVDD

VGOFFH

C10

Voltageadjustment

circuitRegulator

Charge-pump

circuit 1

C23PC23M

C21M

Charge-pump

circuit 2

C21P

C31P Charge-pump

circuit 3

C41-Vci4

C41+ Charge-pump

circuit 4

REGN

C14C17

AVDD

C18

C4

C3

C2

C6

VC1

C5

C3


AVDD

VGL

GVDD

VCOML





GRAMMSB LSB

PKP00PKP01PKP02

PKP10PKP11PKP12

PKP20PKP21PKP22

PKP30PKP31PKP32

PKP40PKP41PKP42

PKP50PKP51PKP52

PRP00PRP01PRP02

PRP10PRP11PRP12

VRP00VRP01VRP02

VRP10VRP11VRP12

VRP03

VRP13VRP14

PKN00PKN01PKN02

PKN10PKN11PKN12

PKN20PKN21PKN22

PKN30PKN31PKN32

PKN40PKN41PKN42

PKN50PKN51PKN52

PRN00PRN01PRN02

PRN10PRN11PRN12

VRN00VRN01VRN02

VRN10VRN11VRN12

VRN03

VRN13VRN14



GrayscaleAm plifier


ltRgt

LCD driver

64 grayscalecontrol

ltG gt

LCD driver

64 grayscalecontrol

ltBgt

LCD driver

64

V1

V0

V63

6 6 6

R G BLCD


Scan Mode

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176


11


01

G176 G175 G174 G173 hellip G4 G3 G2 G110

G1 G2 G3 G4 hellip G173 G174 G175 G17600

Scan ModeGSSM

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176


A

B

C

D

A

B

C

D






33 3 3 3 54333








G V D D

V G S


V I N P N 0

V I N P N 1

V I N P N 2

V I N P N 3

V I N P N 4

V I N P N 5

V I N P N 6

V I N P N 7

V 0

V 6 3

V 6 2

V 5 5

V 4 3

V 2 0

V 8

V 1V 2V 3

V 9

V 2 1

V 4 4

V 5 6V 5 7





Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge





8080Dummy Pad1195239742


Pad sizeum


UnitSize

Pad nameItems









Technology






25532V Process










Gat

e D

river

IC


Gat

e D

river

IC

T-Con

LTPS TFT-LCD


Source Driver IC

Gat

e D

river

IC

De-MUX






Outline









Digital vs Analog




TTL vs LVDS





XGA 325M (2 ports)

67M ( 1 port)

67M (2 ports)

SXGA 54M (2 ports)

54M (2 ports)

108M (2 ports)

Frequency

UXGA - 81M 162M LCD




6-bit ~80 ~60 ~50



RSDS Definition




8 Bit RGB RSDS Data

Start pulseR0 R1

R2 R3

R4 R5

G0 G1

G2 G3G4 G5

B0 B1

B2 B3

B4 B5

Invalid data

Invalid data

Invalid data

R6 R7

G6 G7

B6 B7



Single-end

FrontBack








Mini-LVDS

Data Bus Structure


Mini-LVDS

6 bit data 5 pairs


8 bit data 6 pairs

Mini-LVDS






TQFP100


RSDS vs Mini-LVDS













PPDSRSDSParameter



PPDSTM








PPDS Protocol





10-bit(1024灰階)


Memo





1 2 011 2 1

2 2 2 2

2


refLSB N

b b bbV V L V B

VV

minus minusminus

⎛ ⎞= + + + + = times⎜ ⎟⎝ ⎠




















Offset Error



2-bit example

00( ) outoff

LSB

VE DAC V=






LSB LSB

V VEV V





Accuracy



error


removed










DA Converter









bull Glitches






Decoder-based

Binary-weighted

Thermometer-code

Hybrid



Decoder-Based DAC








Decoder-Based DAC






R

R

R

R

R

R

R

R

R

b0 b0

b1 b1

b2

b2

Vout

VRef

2N resistors

Bin = b22-1+b12-2+b02-3


















( 1) (2 3 )

tr tr tr tr tr tr

tr tr

R C R C N R C

N N R C


= + sdot

L











R

R

R

R

R

R

R

R

R

VRef

Vout

b2

b1

b0




Decoder-Based DAC



























3 2 1

1 2 33 2 1

2 4 8 2 2 2

Fout F ref ref In

In




= + + +LL

bull 4-bit example





















R-2R-based DAC


bull 4-bit example


11 1

_2 2 2

N Nref i R iF

R out F refi ii i


= =


sum sum













Current-mode DAC


ground potential

















across RF)









bull Glitches


















current sources












Examples of DAC 2





R-String DAC

R2

R2

R

R

R

R

R

R

R

b1b1

out

5

-19

b3b2b2 b3







ROM Decoder


Gamma Correction




Gamma Correction






Low noise






Output Buffer

DAC P

DAC N


OddOutput

EvenOutput

Gamma Voltage

(+)

Gamma Voltage

(-)

To data line

Rail to rail OP-AMP

-+

+-


Output Buffer

DAC P

negativebuffer


OddOutput

EvenOutput

Gamma Voltage

(+)

Gamma Voltage

(-)

To data line


PN type OP-AMP

DAC N

positivebuffer

+-

+-




Low deviation



Optimum OP AMP area



V1V2

+

-

Vss

Vdd

+

-+

-

Vout=Av(V1-V2)+

-





stage

High-gainstage

OutputBuffer


Bias Circuitry

Vout VoutrsquoV1V2





2




Hierarchy

Current to voltage

Current to voltage

voltage to current

voltage to current

conversion



(current mirror)





MOS diodeload


Class B (push-pull)

Currentstage

1stvoltagestage

2ndvoltagestage



Examples of Op-Amp





Design of Op Amp





1 Hand calculation









V-1005(L=1um)001(L=2um)

004(L=1um)001(L=2um)




Krsquo



symbol
















A(s)

F(s)

+

-ΣVin(s) Vout(s)

















need compensation




Z1 = gmIICC

CII gtgt CI CC



loop gain F(s)=1






and the RHP zero


C

m

C

mI

Cg

CgGB 2=cong

C

m

C

mI

m

II

mII

Cm

dsdsdsds

CmII

III

Cg

Cgz

Cg

Cgp

Cggggg

CgGGp

21

2

62

6

76421

))((

=cong

minus=

minuscong

++minus=

minuscong

Unit gain bandwidth






Cm

dsdsdsds

CmII

III

Cggggg

CgGGp

6

7642

1

))(( ++minus

=minus

cong








2

62 C

gCgp m

II

mII minus=

minuscong






VsCRsCgRV

sCRRV

sCRsCRgsV

CII

CmII

CII

II

CII

CIImout 1

)1(1

1

)1()( 66

+minusminus

=⎟⎟⎠

⎞⎜⎜⎝

⎛+

+⎟⎟⎠

⎞⎜⎜⎝

⎛+

minus=

Vrsquorsquo

Vout

VDD

CC

Vrsquo

++

--

M6

RII



IC1 IC2


VocOutput offset

between chip tochip




of gray m


Offset Cancellation

Voffset

VinVo=Vin+Voffset


Phase 1

Phase 2

Caz



Caz

Vo=Vin


+-

+ -

- +

- +

- +-+



Channel 384

Channel 383

Channel 382

Channel 381

Channel 4

Channel 3

Channel 2

Channel 1

Length

Height


Channel 420

Channel 419

Channel 418

Channel 417

Channel 4

Channel 3

Channel 2

Channel 1


Channel 480

Channel 479

Channel 478

Channel 477

Channel 4

Channel 3

Channel 2

Channel 1


resistor

Gammaresistor

Gammaresistor



TSMC HV Process




LCD Panel

Start pulse










dtdVCI times=

P = fdCloadVDD2

Turn on one clock




ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

clock

clock

Clock 2Clock 1

Clock 2Clock 1



Dual edge clocking

1 2 3 4

CK1XCK1CK2XCK2


Charge Sharing

To data line

DAC P


OddOutput

EvenOutput

OP

OPDAC NData

Data

Vgmama+

Vgmama-

-+

-+









CNS for Car

4~8mA

DSC Game PDA

2~3mA

05 ~ 2 mA

Mobile-phone


Large size panel









TV application


Outline









LCD TV Electronics

LCD Control Board


SDTV 720x480

cable


DCDC power




LCD Module

TTLLVDSTMDS

γ


OSD

Scaler

MCU

ADCAnalog

RGB

VideoDecoder

DigitalDVI

TMDSRx

De-interlace

Tuner

YC

SyncSep

Compositevideo

AntennaRF in

YCbCr

YPbPr



Digital TV System


MPEG2Decoder PODCI

32MB DDRSDRAM

Scaler IC







RESETRESET


SWITCHSWITCH



DiodesDiodes

LCDLCDDRIVERDRIVER


MICONMICON



INVERTERINVERTER


LCDLCDPANELPANEL

POWERAMPPOWERAMP




LA7585LA7585LA758788LA758788

LA7565LA7565


LA426061LA426061LA426570LA426570LA428082LA428082


LA7221LA7221









LA76818LA76818LA863228LA863228

FSS140132134FSS140132134CPH33043414CPH33043414


CPH5506CPH5506

LA426642674268LA426642674268LA427642774278LA427642774278








Black Insertion





DAC

γminus18R1 string

γminus22R2 string

γminus26R3 string

switch


Vref [118] Vout

8-bit Data


V0~V255




example



Over-8 bit data







Gn-1

Gn

Gray Level



Actual Response

Gn-1

Gn

Gray Level


Gn

Overdrive Response

Voltage by Driver







Overdrive Circuits

Memory

Lookup Table

Control ckts

Data

Dn

Dn+1

Ctrl

addressReadWrite

Datarsquo




ight

ness

Normal image

brig

htne

ss

bright imagebr

ight

ness


Other Technologies






LCD TV Trends


Size

BrightnessCR

Response Time

LCD Monitor

15-20rdquo

250400

25~16ms


Resolution XGA~UXGA

2002~2003

LCD TV


400~550500~700 gt550gt2k

25~16ms 16~12ms lt 8 ms

160160 176176


2004~2008

challenge

COST


Outline








TFTTFT



Controller025 μm

Sourcedriver05 μm


Gatedriver

06 μm HV



HV

Single chipHV

4 Chip TCPCOF Type

2 Chip COGCOF Type

1 Chip COG Type


HitachiSamsung

奇景聯詠

智寶科技







PWR SRAMGAMA64

APRSRAM

Gate Driver

PWR



18

64

18


Gate control

PowerSupplyCircuit

TimingGenerator

OSCSystem Interface


Indexregister

Controlregister

graylevelgenerator




Gammaadjusting

Addresscounter

VGHVGL

VgoffGVDDVGS

AVDD

18

G17

7G

176

G17

5 G

2G

1G

0

S396

S395

S394

S3 S2 S1

SPIC

ontrol

RW

Data

VDD3VDD

Latch circuitand

Vcom


Voltage Setting


VDD(20V ~ 33V)


VCI(25V ~ 33V)

BT2-0

BT2-0

VRH3-0

VREG2OUT

VCOM4-0

VGH(+9 ~ +165V)

AVDD(+35~ +55V)


VCL

VgoffH (to -50V)


VGL (-165 to -9V)

-1 times-1 times

VREG1OUT

VDV4-0

VCI1

VC2-0

VSS(0V)

VC3=1VRL3-0

GVDD(+30~ +50V)

VC3=0VRL3-0


Voltage Waveforms


sn(source output)

VCOM

Gn (Gate output)

VGH(+9 ~ +165V)


VgoffH (~to -50V)


GVDD(+30~ +50V)VDD(20V ~ 33V)

AVDD(+35~ +55V)

VSS(0V)






OVcomOUT


OVREG2OUT


OVREG1OUT


IOREGP





IOVCI



IOAVDD



-VDD

DescriptionIOSymbol




OVgoffL


OVgoffH



voltage

OVgoffOUT


IVgoff


higher than -150 V

OVGL



OVGH



OVcomL


OVcomH



IVcomR

DescriptionIOSymbol



mA2015-IVCI



by mode


Outputs


Outputs


Outputs





V5-3GVDD

V-5--16VGOFF

V-9--165VGL

V165-9VGH


V55-35AVDD

LCD Supply Voltage







Vcom


Vcom



Vgoff






V595583571VREG1OUT









VCI2

VCI VCI

VDDVSSVCIVSS

C7

int

VGL

VGH

C1VGH

C22P

C16


C11+

C1 5REGP

VCL

C31MVCI3

C22M

C12-C12+

C11-Vci1

VCIOUT

VCOMR

VGOFFOUT

VGOFFL

C20

C19

VCOMOUT

VCOMH

VREG1OUT

VREG2OUT

C 21

C 11


(Vgoffadjustment)


adjustment)

VcomHadjustment

circuit


circuit

GVDDoutput

amplifier

VcomHoutput

amplifier

VcomLoutput

amplifier

VgoffHoutput


amplifier


circuit

C12

C9GVDD

VGOFFH

C10

Voltageadjustment

circuitRegulator

Charge-pump

circuit 1

C23PC23M

C21M

Charge-pump

circuit 2

C21P

C31P Charge-pump

circuit 3

C41-Vci4

C41+ Charge-pump

circuit 4

REGN

C14C17

AVDD

C18

C4

C3

C2

C6

VC1

C5

C3


AVDD

VGL

GVDD

VCOML





GRAMMSB LSB

PKP00PKP01PKP02

PKP10PKP11PKP12

PKP20PKP21PKP22

PKP30PKP31PKP32

PKP40PKP41PKP42

PKP50PKP51PKP52

PRP00PRP01PRP02

PRP10PRP11PRP12

VRP00VRP01VRP02

VRP10VRP11VRP12

VRP03

VRP13VRP14

PKN00PKN01PKN02

PKN10PKN11PKN12

PKN20PKN21PKN22

PKN30PKN31PKN32

PKN40PKN41PKN42

PKN50PKN51PKN52

PRN00PRN01PRN02

PRN10PRN11PRN12

VRN00VRN01VRN02

VRN10VRN11VRN12

VRN03

VRN13VRN14



GrayscaleAm plifier


ltRgt

LCD driver

64 grayscalecontrol

ltG gt

LCD driver

64 grayscalecontrol

ltBgt

LCD driver

64

V1

V0

V63

6 6 6

R G BLCD


Scan Mode

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176


11


01

G176 G175 G174 G173 hellip G4 G3 G2 G110

G1 G2 G3 G4 hellip G173 G174 G175 G17600

Scan ModeGSSM

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176


A

B

C

D

A

B

C

D






33 3 3 3 54333








G V D D

V G S


V I N P N 0

V I N P N 1

V I N P N 2

V I N P N 3

V I N P N 4

V I N P N 5

V I N P N 6

V I N P N 7

V 0

V 6 3

V 6 2

V 5 5

V 4 3

V 2 0

V 8

V 1V 2V 3

V 9

V 2 1

V 4 4

V 5 6V 5 7





Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge





8080Dummy Pad1195239742


Pad sizeum


UnitSize

Pad nameItems









Technology






25532V Process










Gat

e D

river

IC


Gat

e D

river

IC

T-Con

LTPS TFT-LCD


Source Driver IC

Gat

e D

river

IC

De-MUX






Outline









Digital vs Analog




TTL vs LVDS





XGA 325M (2 ports)

67M ( 1 port)

67M (2 ports)

SXGA 54M (2 ports)

54M (2 ports)

108M (2 ports)

Frequency

UXGA - 81M 162M LCD




6-bit ~80 ~60 ~50



RSDS Definition




8 Bit RGB RSDS Data

Start pulseR0 R1

R2 R3

R4 R5

G0 G1

G2 G3G4 G5

B0 B1

B2 B3

B4 B5

Invalid data

Invalid data

Invalid data

R6 R7

G6 G7

B6 B7



Single-end

FrontBack








Mini-LVDS

Data Bus Structure


Mini-LVDS

6 bit data 5 pairs


8 bit data 6 pairs

Mini-LVDS






TQFP100


RSDS vs Mini-LVDS













PPDSRSDSParameter



PPDSTM








PPDS Protocol





10-bit(1024灰階)


Memo


Offset Error



2-bit example

00( ) outoff

LSB

VE DAC V=






LSB LSB

V VEV V





Accuracy



error


removed










DA Converter









bull Glitches






Decoder-based

Binary-weighted

Thermometer-code

Hybrid



Decoder-Based DAC








Decoder-Based DAC






R

R

R

R

R

R

R

R

R

b0 b0

b1 b1

b2

b2

Vout

VRef

2N resistors

Bin = b22-1+b12-2+b02-3


















( 1) (2 3 )

tr tr tr tr tr tr

tr tr

R C R C N R C

N N R C


= + sdot

L











R

R

R

R

R

R

R

R

R

VRef

Vout

b2

b1

b0




Decoder-Based DAC



























3 2 1

1 2 33 2 1

2 4 8 2 2 2

Fout F ref ref In

In




= + + +LL

bull 4-bit example





















R-2R-based DAC


bull 4-bit example


11 1

_2 2 2

N Nref i R iF

R out F refi ii i


= =


sum sum













Current-mode DAC


ground potential

















across RF)









bull Glitches


















current sources












Examples of DAC 2





R-String DAC

R2

R2

R

R

R

R

R

R

R

b1b1

out

5

-19

b3b2b2 b3







ROM Decoder


Gamma Correction




Gamma Correction






Low noise






Output Buffer

DAC P

DAC N


OddOutput

EvenOutput

Gamma Voltage

(+)

Gamma Voltage

(-)

To data line

Rail to rail OP-AMP

-+

+-


Output Buffer

DAC P

negativebuffer


OddOutput

EvenOutput

Gamma Voltage

(+)

Gamma Voltage

(-)

To data line


PN type OP-AMP

DAC N

positivebuffer

+-

+-




Low deviation



Optimum OP AMP area



V1V2

+

-

Vss

Vdd

+

-+

-

Vout=Av(V1-V2)+

-





stage

High-gainstage

OutputBuffer


Bias Circuitry

Vout VoutrsquoV1V2





2




Hierarchy

Current to voltage

Current to voltage

voltage to current

voltage to current

conversion



(current mirror)





MOS diodeload


Class B (push-pull)

Currentstage

1stvoltagestage

2ndvoltagestage



Examples of Op-Amp





Design of Op Amp





1 Hand calculation









V-1005(L=1um)001(L=2um)

004(L=1um)001(L=2um)




Krsquo



symbol
















A(s)

F(s)

+

-ΣVin(s) Vout(s)

















need compensation




Z1 = gmIICC

CII gtgt CI CC



loop gain F(s)=1






and the RHP zero


C

m

C

mI

Cg

CgGB 2=cong

C

m

C

mI

m

II

mII

Cm

dsdsdsds

CmII

III

Cg

Cgz

Cg

Cgp

Cggggg

CgGGp

21

2

62

6

76421

))((

=cong

minus=

minuscong

++minus=

minuscong

Unit gain bandwidth






Cm

dsdsdsds

CmII

III

Cggggg

CgGGp

6

7642

1

))(( ++minus

=minus

cong








2

62 C

gCgp m

II

mII minus=

minuscong






VsCRsCgRV

sCRRV

sCRsCRgsV

CII

CmII

CII

II

CII

CIImout 1

)1(1

1

)1()( 66

+minusminus

=⎟⎟⎠

⎞⎜⎜⎝

⎛+

+⎟⎟⎠

⎞⎜⎜⎝

⎛+

minus=

Vrsquorsquo

Vout

VDD

CC

Vrsquo

++

--

M6

RII



IC1 IC2


VocOutput offset

between chip tochip




of gray m


Offset Cancellation

Voffset

VinVo=Vin+Voffset


Phase 1

Phase 2

Caz



Caz

Vo=Vin


+-

+ -

- +

- +

- +-+



Channel 384

Channel 383

Channel 382

Channel 381

Channel 4

Channel 3

Channel 2

Channel 1

Length

Height


Channel 420

Channel 419

Channel 418

Channel 417

Channel 4

Channel 3

Channel 2

Channel 1


Channel 480

Channel 479

Channel 478

Channel 477

Channel 4

Channel 3

Channel 2

Channel 1


resistor

Gammaresistor

Gammaresistor



TSMC HV Process




LCD Panel

Start pulse










dtdVCI times=

P = fdCloadVDD2

Turn on one clock




ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

clock

clock

Clock 2Clock 1

Clock 2Clock 1



Dual edge clocking

1 2 3 4

CK1XCK1CK2XCK2


Charge Sharing

To data line

DAC P


OddOutput

EvenOutput

OP

OPDAC NData

Data

Vgmama+

Vgmama-

-+

-+









CNS for Car

4~8mA

DSC Game PDA

2~3mA

05 ~ 2 mA

Mobile-phone


Large size panel









TV application


Outline









LCD TV Electronics

LCD Control Board


SDTV 720x480

cable


DCDC power




LCD Module

TTLLVDSTMDS

γ


OSD

Scaler

MCU

ADCAnalog

RGB

VideoDecoder

DigitalDVI

TMDSRx

De-interlace

Tuner

YC

SyncSep

Compositevideo

AntennaRF in

YCbCr

YPbPr



Digital TV System


MPEG2Decoder PODCI

32MB DDRSDRAM

Scaler IC







RESETRESET


SWITCHSWITCH



DiodesDiodes

LCDLCDDRIVERDRIVER


MICONMICON



INVERTERINVERTER


LCDLCDPANELPANEL

POWERAMPPOWERAMP




LA7585LA7585LA758788LA758788

LA7565LA7565


LA426061LA426061LA426570LA426570LA428082LA428082


LA7221LA7221









LA76818LA76818LA863228LA863228

FSS140132134FSS140132134CPH33043414CPH33043414


CPH5506CPH5506

LA426642674268LA426642674268LA427642774278LA427642774278








Black Insertion





DAC

γminus18R1 string

γminus22R2 string

γminus26R3 string

switch


Vref [118] Vout

8-bit Data


V0~V255




example



Over-8 bit data







Gn-1

Gn

Gray Level



Actual Response

Gn-1

Gn

Gray Level


Gn

Overdrive Response

Voltage by Driver







Overdrive Circuits

Memory

Lookup Table

Control ckts

Data

Dn

Dn+1

Ctrl

addressReadWrite

Datarsquo




ight

ness

Normal image

brig

htne

ss

bright imagebr

ight

ness


Other Technologies






LCD TV Trends


Size

BrightnessCR

Response Time

LCD Monitor

15-20rdquo

250400

25~16ms


Resolution XGA~UXGA

2002~2003

LCD TV


400~550500~700 gt550gt2k

25~16ms 16~12ms lt 8 ms

160160 176176


2004~2008

challenge

COST


Outline








TFTTFT



Controller025 μm

Sourcedriver05 μm


Gatedriver

06 μm HV



HV

Single chipHV

4 Chip TCPCOF Type

2 Chip COGCOF Type

1 Chip COG Type


HitachiSamsung

奇景聯詠

智寶科技







PWR SRAMGAMA64

APRSRAM

Gate Driver

PWR



18

64

18


Gate control

PowerSupplyCircuit

TimingGenerator

OSCSystem Interface


Indexregister

Controlregister

graylevelgenerator




Gammaadjusting

Addresscounter

VGHVGL

VgoffGVDDVGS

AVDD

18

G17

7G

176

G17

5 G

2G

1G

0

S396

S395

S394

S3 S2 S1

SPIC

ontrol

RW

Data

VDD3VDD

Latch circuitand

Vcom


Voltage Setting


VDD(20V ~ 33V)


VCI(25V ~ 33V)

BT2-0

BT2-0

VRH3-0

VREG2OUT

VCOM4-0

VGH(+9 ~ +165V)

AVDD(+35~ +55V)


VCL

VgoffH (to -50V)


VGL (-165 to -9V)

-1 times-1 times

VREG1OUT

VDV4-0

VCI1

VC2-0

VSS(0V)

VC3=1VRL3-0

GVDD(+30~ +50V)

VC3=0VRL3-0


Voltage Waveforms


sn(source output)

VCOM

Gn (Gate output)

VGH(+9 ~ +165V)


VgoffH (~to -50V)


GVDD(+30~ +50V)VDD(20V ~ 33V)

AVDD(+35~ +55V)

VSS(0V)






OVcomOUT


OVREG2OUT


OVREG1OUT


IOREGP





IOVCI



IOAVDD



-VDD

DescriptionIOSymbol




OVgoffL


OVgoffH



voltage

OVgoffOUT


IVgoff


higher than -150 V

OVGL



OVGH



OVcomL


OVcomH



IVcomR

DescriptionIOSymbol



mA2015-IVCI



by mode


Outputs


Outputs


Outputs





V5-3GVDD

V-5--16VGOFF

V-9--165VGL

V165-9VGH


V55-35AVDD

LCD Supply Voltage







Vcom


Vcom



Vgoff






V595583571VREG1OUT









VCI2

VCI VCI

VDDVSSVCIVSS

C7

int

VGL

VGH

C1VGH

C22P

C16


C11+

C1 5REGP

VCL

C31MVCI3

C22M

C12-C12+

C11-Vci1

VCIOUT

VCOMR

VGOFFOUT

VGOFFL

C20

C19

VCOMOUT

VCOMH

VREG1OUT

VREG2OUT

C 21

C 11


(Vgoffadjustment)


adjustment)

VcomHadjustment

circuit


circuit

GVDDoutput

amplifier

VcomHoutput

amplifier

VcomLoutput

amplifier

VgoffHoutput


amplifier


circuit

C12

C9GVDD

VGOFFH

C10

Voltageadjustment

circuitRegulator

Charge-pump

circuit 1

C23PC23M

C21M

Charge-pump

circuit 2

C21P

C31P Charge-pump

circuit 3

C41-Vci4

C41+ Charge-pump

circuit 4

REGN

C14C17

AVDD

C18

C4

C3

C2

C6

VC1

C5

C3


AVDD

VGL

GVDD

VCOML





GRAMMSB LSB

PKP00PKP01PKP02

PKP10PKP11PKP12

PKP20PKP21PKP22

PKP30PKP31PKP32

PKP40PKP41PKP42

PKP50PKP51PKP52

PRP00PRP01PRP02

PRP10PRP11PRP12

VRP00VRP01VRP02

VRP10VRP11VRP12

VRP03

VRP13VRP14

PKN00PKN01PKN02

PKN10PKN11PKN12

PKN20PKN21PKN22

PKN30PKN31PKN32

PKN40PKN41PKN42

PKN50PKN51PKN52

PRN00PRN01PRN02

PRN10PRN11PRN12

VRN00VRN01VRN02

VRN10VRN11VRN12

VRN03

VRN13VRN14



GrayscaleAm plifier


ltRgt

LCD driver

64 grayscalecontrol

ltG gt

LCD driver

64 grayscalecontrol

ltBgt

LCD driver

64

V1

V0

V63

6 6 6

R G BLCD


Scan Mode

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176


11


01

G176 G175 G174 G173 hellip G4 G3 G2 G110

G1 G2 G3 G4 hellip G173 G174 G175 G17600

Scan ModeGSSM

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176


A

B

C

D

A

B

C

D






33 3 3 3 54333








G V D D

V G S


V I N P N 0

V I N P N 1

V I N P N 2

V I N P N 3

V I N P N 4

V I N P N 5

V I N P N 6

V I N P N 7

V 0

V 6 3

V 6 2

V 5 5

V 4 3

V 2 0

V 8

V 1V 2V 3

V 9

V 2 1

V 4 4

V 5 6V 5 7





Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge





8080Dummy Pad1195239742


Pad sizeum


UnitSize

Pad nameItems









Technology






25532V Process










Gat

e D

river

IC


Gat

e D

river

IC

T-Con

LTPS TFT-LCD


Source Driver IC

Gat

e D

river

IC

De-MUX






Outline









Digital vs Analog




TTL vs LVDS





XGA 325M (2 ports)

67M ( 1 port)

67M (2 ports)

SXGA 54M (2 ports)

54M (2 ports)

108M (2 ports)

Frequency

UXGA - 81M 162M LCD




6-bit ~80 ~60 ~50



RSDS Definition




8 Bit RGB RSDS Data

Start pulseR0 R1

R2 R3

R4 R5

G0 G1

G2 G3G4 G5

B0 B1

B2 B3

B4 B5

Invalid data

Invalid data

Invalid data

R6 R7

G6 G7

B6 B7



Single-end

FrontBack








Mini-LVDS

Data Bus Structure


Mini-LVDS

6 bit data 5 pairs


8 bit data 6 pairs

Mini-LVDS






TQFP100


RSDS vs Mini-LVDS













PPDSRSDSParameter



PPDSTM








PPDS Protocol





10-bit(1024灰階)


Memo


DA Converter









bull Glitches






Decoder-based

Binary-weighted

Thermometer-code

Hybrid



Decoder-Based DAC








Decoder-Based DAC






R

R

R

R

R

R

R

R

R

b0 b0

b1 b1

b2

b2

Vout

VRef

2N resistors

Bin = b22-1+b12-2+b02-3


















( 1) (2 3 )

tr tr tr tr tr tr

tr tr

R C R C N R C

N N R C


= + sdot

L











R

R

R

R

R

R

R

R

R

VRef

Vout

b2

b1

b0




Decoder-Based DAC



























3 2 1

1 2 33 2 1

2 4 8 2 2 2

Fout F ref ref In

In




= + + +LL

bull 4-bit example





















R-2R-based DAC


bull 4-bit example


11 1

_2 2 2

N Nref i R iF

R out F refi ii i


= =


sum sum













Current-mode DAC


ground potential

















across RF)









bull Glitches


















current sources












Examples of DAC 2





R-String DAC

R2

R2

R

R

R

R

R

R

R

b1b1

out

5

-19

b3b2b2 b3







ROM Decoder


Gamma Correction




Gamma Correction






Low noise






Output Buffer

DAC P

DAC N


OddOutput

EvenOutput

Gamma Voltage

(+)

Gamma Voltage

(-)

To data line

Rail to rail OP-AMP

-+

+-


Output Buffer

DAC P

negativebuffer


OddOutput

EvenOutput

Gamma Voltage

(+)

Gamma Voltage

(-)

To data line


PN type OP-AMP

DAC N

positivebuffer

+-

+-




Low deviation



Optimum OP AMP area



V1V2

+

-

Vss

Vdd

+

-+

-

Vout=Av(V1-V2)+

-





stage

High-gainstage

OutputBuffer


Bias Circuitry

Vout VoutrsquoV1V2





2




Hierarchy

Current to voltage

Current to voltage

voltage to current

voltage to current

conversion



(current mirror)





MOS diodeload


Class B (push-pull)

Currentstage

1stvoltagestage

2ndvoltagestage



Examples of Op-Amp





Design of Op Amp





1 Hand calculation









V-1005(L=1um)001(L=2um)

004(L=1um)001(L=2um)




Krsquo



symbol
















A(s)

F(s)

+

-ΣVin(s) Vout(s)

















need compensation




Z1 = gmIICC

CII gtgt CI CC



loop gain F(s)=1






and the RHP zero


C

m

C

mI

Cg

CgGB 2=cong

C

m

C

mI

m

II

mII

Cm

dsdsdsds

CmII

III

Cg

Cgz

Cg

Cgp

Cggggg

CgGGp

21

2

62

6

76421

))((

=cong

minus=

minuscong

++minus=

minuscong

Unit gain bandwidth






Cm

dsdsdsds

CmII

III

Cggggg

CgGGp

6

7642

1

))(( ++minus

=minus

cong








2

62 C

gCgp m

II

mII minus=

minuscong






VsCRsCgRV

sCRRV

sCRsCRgsV

CII

CmII

CII

II

CII

CIImout 1

)1(1

1

)1()( 66

+minusminus

=⎟⎟⎠

⎞⎜⎜⎝

⎛+

+⎟⎟⎠

⎞⎜⎜⎝

⎛+

minus=

Vrsquorsquo

Vout

VDD

CC

Vrsquo

++

--

M6

RII



IC1 IC2


VocOutput offset

between chip tochip




of gray m


Offset Cancellation

Voffset

VinVo=Vin+Voffset


Phase 1

Phase 2

Caz



Caz

Vo=Vin


+-

+ -

- +

- +

- +-+



Channel 384

Channel 383

Channel 382

Channel 381

Channel 4

Channel 3

Channel 2

Channel 1

Length

Height


Channel 420

Channel 419

Channel 418

Channel 417

Channel 4

Channel 3

Channel 2

Channel 1


Channel 480

Channel 479

Channel 478

Channel 477

Channel 4

Channel 3

Channel 2

Channel 1


resistor

Gammaresistor

Gammaresistor



TSMC HV Process




LCD Panel

Start pulse










dtdVCI times=

P = fdCloadVDD2

Turn on one clock




ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

clock

clock

Clock 2Clock 1

Clock 2Clock 1



Dual edge clocking

1 2 3 4

CK1XCK1CK2XCK2


Charge Sharing

To data line

DAC P


OddOutput

EvenOutput

OP

OPDAC NData

Data

Vgmama+

Vgmama-

-+

-+









CNS for Car

4~8mA

DSC Game PDA

2~3mA

05 ~ 2 mA

Mobile-phone


Large size panel









TV application


Outline









LCD TV Electronics

LCD Control Board


SDTV 720x480

cable


DCDC power




LCD Module

TTLLVDSTMDS

γ


OSD

Scaler

MCU

ADCAnalog

RGB

VideoDecoder

DigitalDVI

TMDSRx

De-interlace

Tuner

YC

SyncSep

Compositevideo

AntennaRF in

YCbCr

YPbPr



Digital TV System


MPEG2Decoder PODCI

32MB DDRSDRAM

Scaler IC







RESETRESET


SWITCHSWITCH



DiodesDiodes

LCDLCDDRIVERDRIVER


MICONMICON



INVERTERINVERTER


LCDLCDPANELPANEL

POWERAMPPOWERAMP




LA7585LA7585LA758788LA758788

LA7565LA7565


LA426061LA426061LA426570LA426570LA428082LA428082


LA7221LA7221









LA76818LA76818LA863228LA863228

FSS140132134FSS140132134CPH33043414CPH33043414


CPH5506CPH5506

LA426642674268LA426642674268LA427642774278LA427642774278








Black Insertion





DAC

γminus18R1 string

γminus22R2 string

γminus26R3 string

switch


Vref [118] Vout

8-bit Data


V0~V255




example



Over-8 bit data







Gn-1

Gn

Gray Level



Actual Response

Gn-1

Gn

Gray Level


Gn

Overdrive Response

Voltage by Driver







Overdrive Circuits

Memory

Lookup Table

Control ckts

Data

Dn

Dn+1

Ctrl

addressReadWrite

Datarsquo




ight

ness

Normal image

brig

htne

ss

bright imagebr

ight

ness


Other Technologies






LCD TV Trends


Size

BrightnessCR

Response Time

LCD Monitor

15-20rdquo

250400

25~16ms


Resolution XGA~UXGA

2002~2003

LCD TV


400~550500~700 gt550gt2k

25~16ms 16~12ms lt 8 ms

160160 176176


2004~2008

challenge

COST


Outline








TFTTFT



Controller025 μm

Sourcedriver05 μm


Gatedriver

06 μm HV



HV

Single chipHV

4 Chip TCPCOF Type

2 Chip COGCOF Type

1 Chip COG Type


HitachiSamsung

奇景聯詠

智寶科技







PWR SRAMGAMA64

APRSRAM

Gate Driver

PWR



18

64

18


Gate control

PowerSupplyCircuit

TimingGenerator

OSCSystem Interface


Indexregister

Controlregister

graylevelgenerator




Gammaadjusting

Addresscounter

VGHVGL

VgoffGVDDVGS

AVDD

18

G17

7G

176

G17

5 G

2G

1G

0

S396

S395

S394

S3 S2 S1

SPIC

ontrol

RW

Data

VDD3VDD

Latch circuitand

Vcom


Voltage Setting


VDD(20V ~ 33V)


VCI(25V ~ 33V)

BT2-0

BT2-0

VRH3-0

VREG2OUT

VCOM4-0

VGH(+9 ~ +165V)

AVDD(+35~ +55V)


VCL

VgoffH (to -50V)


VGL (-165 to -9V)

-1 times-1 times

VREG1OUT

VDV4-0

VCI1

VC2-0

VSS(0V)

VC3=1VRL3-0

GVDD(+30~ +50V)

VC3=0VRL3-0


Voltage Waveforms


sn(source output)

VCOM

Gn (Gate output)

VGH(+9 ~ +165V)


VgoffH (~to -50V)


GVDD(+30~ +50V)VDD(20V ~ 33V)

AVDD(+35~ +55V)

VSS(0V)






OVcomOUT


OVREG2OUT


OVREG1OUT


IOREGP





IOVCI



IOAVDD



-VDD

DescriptionIOSymbol




OVgoffL


OVgoffH



voltage

OVgoffOUT


IVgoff


higher than -150 V

OVGL



OVGH



OVcomL


OVcomH



IVcomR

DescriptionIOSymbol



mA2015-IVCI



by mode


Outputs


Outputs


Outputs





V5-3GVDD

V-5--16VGOFF

V-9--165VGL

V165-9VGH


V55-35AVDD

LCD Supply Voltage







Vcom


Vcom



Vgoff






V595583571VREG1OUT









VCI2

VCI VCI

VDDVSSVCIVSS

C7

int

VGL

VGH

C1VGH

C22P

C16


C11+

C1 5REGP

VCL

C31MVCI3

C22M

C12-C12+

C11-Vci1

VCIOUT

VCOMR

VGOFFOUT

VGOFFL

C20

C19

VCOMOUT

VCOMH

VREG1OUT

VREG2OUT

C 21

C 11


(Vgoffadjustment)


adjustment)

VcomHadjustment

circuit


circuit

GVDDoutput

amplifier

VcomHoutput

amplifier

VcomLoutput

amplifier

VgoffHoutput


amplifier


circuit

C12

C9GVDD

VGOFFH

C10

Voltageadjustment

circuitRegulator

Charge-pump

circuit 1

C23PC23M

C21M

Charge-pump

circuit 2

C21P

C31P Charge-pump

circuit 3

C41-Vci4

C41+ Charge-pump

circuit 4

REGN

C14C17

AVDD

C18

C4

C3

C2

C6

VC1

C5

C3


AVDD

VGL

GVDD

VCOML





GRAMMSB LSB

PKP00PKP01PKP02

PKP10PKP11PKP12

PKP20PKP21PKP22

PKP30PKP31PKP32

PKP40PKP41PKP42

PKP50PKP51PKP52

PRP00PRP01PRP02

PRP10PRP11PRP12

VRP00VRP01VRP02

VRP10VRP11VRP12

VRP03

VRP13VRP14

PKN00PKN01PKN02

PKN10PKN11PKN12

PKN20PKN21PKN22

PKN30PKN31PKN32

PKN40PKN41PKN42

PKN50PKN51PKN52

PRN00PRN01PRN02

PRN10PRN11PRN12

VRN00VRN01VRN02

VRN10VRN11VRN12

VRN03

VRN13VRN14



GrayscaleAm plifier


ltRgt

LCD driver

64 grayscalecontrol

ltG gt

LCD driver

64 grayscalecontrol

ltBgt

LCD driver

64

V1

V0

V63

6 6 6

R G BLCD


Scan Mode

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176


11


01

G176 G175 G174 G173 hellip G4 G3 G2 G110

G1 G2 G3 G4 hellip G173 G174 G175 G17600

Scan ModeGSSM

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176


A

B

C

D

A

B

C

D






33 3 3 3 54333








G V D D

V G S


V I N P N 0

V I N P N 1

V I N P N 2

V I N P N 3

V I N P N 4

V I N P N 5

V I N P N 6

V I N P N 7

V 0

V 6 3

V 6 2

V 5 5

V 4 3

V 2 0

V 8

V 1V 2V 3

V 9

V 2 1

V 4 4

V 5 6V 5 7





Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge





8080Dummy Pad1195239742


Pad sizeum


UnitSize

Pad nameItems









Technology






25532V Process










Gat

e D

river

IC


Gat

e D

river

IC

T-Con

LTPS TFT-LCD


Source Driver IC

Gat

e D

river

IC

De-MUX






Outline









Digital vs Analog




TTL vs LVDS





XGA 325M (2 ports)

67M ( 1 port)

67M (2 ports)

SXGA 54M (2 ports)

54M (2 ports)

108M (2 ports)

Frequency

UXGA - 81M 162M LCD




6-bit ~80 ~60 ~50



RSDS Definition




8 Bit RGB RSDS Data

Start pulseR0 R1

R2 R3

R4 R5

G0 G1

G2 G3G4 G5

B0 B1

B2 B3

B4 B5

Invalid data

Invalid data

Invalid data

R6 R7

G6 G7

B6 B7



Single-end

FrontBack








Mini-LVDS

Data Bus Structure


Mini-LVDS

6 bit data 5 pairs


8 bit data 6 pairs

Mini-LVDS






TQFP100


RSDS vs Mini-LVDS













PPDSRSDSParameter



PPDSTM








PPDS Protocol





10-bit(1024灰階)


Memo


Decoder-Based DAC






R

R

R

R

R

R

R

R

R

b0 b0

b1 b1

b2

b2

Vout

VRef

2N resistors

Bin = b22-1+b12-2+b02-3


















( 1) (2 3 )

tr tr tr tr tr tr

tr tr

R C R C N R C

N N R C


= + sdot

L











R

R

R

R

R

R

R

R

R

VRef

Vout

b2

b1

b0




Decoder-Based DAC



























3 2 1

1 2 33 2 1

2 4 8 2 2 2

Fout F ref ref In

In




= + + +LL

bull 4-bit example





















R-2R-based DAC


bull 4-bit example


11 1

_2 2 2

N Nref i R iF

R out F refi ii i


= =


sum sum













Current-mode DAC


ground potential

















across RF)









bull Glitches


















current sources












Examples of DAC 2





R-String DAC

R2

R2

R

R

R

R

R

R

R

b1b1

out

5

-19

b3b2b2 b3







ROM Decoder


Gamma Correction




Gamma Correction






Low noise






Output Buffer

DAC P

DAC N


OddOutput

EvenOutput

Gamma Voltage

(+)

Gamma Voltage

(-)

To data line

Rail to rail OP-AMP

-+

+-


Output Buffer

DAC P

negativebuffer


OddOutput

EvenOutput

Gamma Voltage

(+)

Gamma Voltage

(-)

To data line


PN type OP-AMP

DAC N

positivebuffer

+-

+-




Low deviation



Optimum OP AMP area



V1V2

+

-

Vss

Vdd

+

-+

-

Vout=Av(V1-V2)+

-





stage

High-gainstage

OutputBuffer


Bias Circuitry

Vout VoutrsquoV1V2





2




Hierarchy

Current to voltage

Current to voltage

voltage to current

voltage to current

conversion



(current mirror)





MOS diodeload


Class B (push-pull)

Currentstage

1stvoltagestage

2ndvoltagestage



Examples of Op-Amp





Design of Op Amp





1 Hand calculation









V-1005(L=1um)001(L=2um)

004(L=1um)001(L=2um)




Krsquo



symbol
















A(s)

F(s)

+

-ΣVin(s) Vout(s)

















need compensation




Z1 = gmIICC

CII gtgt CI CC



loop gain F(s)=1






and the RHP zero


C

m

C

mI

Cg

CgGB 2=cong

C

m

C

mI

m

II

mII

Cm

dsdsdsds

CmII

III

Cg

Cgz

Cg

Cgp

Cggggg

CgGGp

21

2

62

6

76421

))((

=cong

minus=

minuscong

++minus=

minuscong

Unit gain bandwidth






Cm

dsdsdsds

CmII

III

Cggggg

CgGGp

6

7642

1

))(( ++minus

=minus

cong








2

62 C

gCgp m

II

mII minus=

minuscong






VsCRsCgRV

sCRRV

sCRsCRgsV

CII

CmII

CII

II

CII

CIImout 1

)1(1

1

)1()( 66

+minusminus

=⎟⎟⎠

⎞⎜⎜⎝

⎛+

+⎟⎟⎠

⎞⎜⎜⎝

⎛+

minus=

Vrsquorsquo

Vout

VDD

CC

Vrsquo

++

--

M6

RII



IC1 IC2


VocOutput offset

between chip tochip




of gray m


Offset Cancellation

Voffset

VinVo=Vin+Voffset


Phase 1

Phase 2

Caz



Caz

Vo=Vin


+-

+ -

- +

- +

- +-+



Channel 384

Channel 383

Channel 382

Channel 381

Channel 4

Channel 3

Channel 2

Channel 1

Length

Height


Channel 420

Channel 419

Channel 418

Channel 417

Channel 4

Channel 3

Channel 2

Channel 1


Channel 480

Channel 479

Channel 478

Channel 477

Channel 4

Channel 3

Channel 2

Channel 1


resistor

Gammaresistor

Gammaresistor



TSMC HV Process




LCD Panel

Start pulse










dtdVCI times=

P = fdCloadVDD2

Turn on one clock




ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

clock

clock

Clock 2Clock 1

Clock 2Clock 1



Dual edge clocking

1 2 3 4

CK1XCK1CK2XCK2


Charge Sharing

To data line

DAC P


OddOutput

EvenOutput

OP

OPDAC NData

Data

Vgmama+

Vgmama-

-+

-+









CNS for Car

4~8mA

DSC Game PDA

2~3mA

05 ~ 2 mA

Mobile-phone


Large size panel









TV application


Outline









LCD TV Electronics

LCD Control Board


SDTV 720x480

cable


DCDC power




LCD Module

TTLLVDSTMDS

γ


OSD

Scaler

MCU

ADCAnalog

RGB

VideoDecoder

DigitalDVI

TMDSRx

De-interlace

Tuner

YC

SyncSep

Compositevideo

AntennaRF in

YCbCr

YPbPr



Digital TV System


MPEG2Decoder PODCI

32MB DDRSDRAM

Scaler IC







RESETRESET


SWITCHSWITCH



DiodesDiodes

LCDLCDDRIVERDRIVER


MICONMICON



INVERTERINVERTER


LCDLCDPANELPANEL

POWERAMPPOWERAMP




LA7585LA7585LA758788LA758788

LA7565LA7565


LA426061LA426061LA426570LA426570LA428082LA428082


LA7221LA7221









LA76818LA76818LA863228LA863228

FSS140132134FSS140132134CPH33043414CPH33043414


CPH5506CPH5506

LA426642674268LA426642674268LA427642774278LA427642774278








Black Insertion





DAC

γminus18R1 string

γminus22R2 string

γminus26R3 string

switch


Vref [118] Vout

8-bit Data


V0~V255




example



Over-8 bit data







Gn-1

Gn

Gray Level



Actual Response

Gn-1

Gn

Gray Level


Gn

Overdrive Response

Voltage by Driver







Overdrive Circuits

Memory

Lookup Table

Control ckts

Data

Dn

Dn+1

Ctrl

addressReadWrite

Datarsquo




ight

ness

Normal image

brig

htne

ss

bright imagebr

ight

ness


Other Technologies






LCD TV Trends


Size

BrightnessCR

Response Time

LCD Monitor

15-20rdquo

250400

25~16ms


Resolution XGA~UXGA

2002~2003

LCD TV


400~550500~700 gt550gt2k

25~16ms 16~12ms lt 8 ms

160160 176176


2004~2008

challenge

COST


Outline








TFTTFT



Controller025 μm

Sourcedriver05 μm


Gatedriver

06 μm HV



HV

Single chipHV

4 Chip TCPCOF Type

2 Chip COGCOF Type

1 Chip COG Type


HitachiSamsung

奇景聯詠

智寶科技







PWR SRAMGAMA64

APRSRAM

Gate Driver

PWR



18

64

18


Gate control

PowerSupplyCircuit

TimingGenerator

OSCSystem Interface


Indexregister

Controlregister

graylevelgenerator




Gammaadjusting

Addresscounter

VGHVGL

VgoffGVDDVGS

AVDD

18

G17

7G

176

G17

5 G

2G

1G

0

S396

S395

S394

S3 S2 S1

SPIC

ontrol

RW

Data

VDD3VDD

Latch circuitand

Vcom


Voltage Setting


VDD(20V ~ 33V)


VCI(25V ~ 33V)

BT2-0

BT2-0

VRH3-0

VREG2OUT

VCOM4-0

VGH(+9 ~ +165V)

AVDD(+35~ +55V)


VCL

VgoffH (to -50V)


VGL (-165 to -9V)

-1 times-1 times

VREG1OUT

VDV4-0

VCI1

VC2-0

VSS(0V)

VC3=1VRL3-0

GVDD(+30~ +50V)

VC3=0VRL3-0


Voltage Waveforms


sn(source output)

VCOM

Gn (Gate output)

VGH(+9 ~ +165V)


VgoffH (~to -50V)


GVDD(+30~ +50V)VDD(20V ~ 33V)

AVDD(+35~ +55V)

VSS(0V)






OVcomOUT


OVREG2OUT


OVREG1OUT


IOREGP





IOVCI



IOAVDD



-VDD

DescriptionIOSymbol




OVgoffL


OVgoffH



voltage

OVgoffOUT


IVgoff


higher than -150 V

OVGL



OVGH



OVcomL


OVcomH



IVcomR

DescriptionIOSymbol



mA2015-IVCI



by mode


Outputs


Outputs


Outputs





V5-3GVDD

V-5--16VGOFF

V-9--165VGL

V165-9VGH


V55-35AVDD

LCD Supply Voltage







Vcom


Vcom



Vgoff






V595583571VREG1OUT









VCI2

VCI VCI

VDDVSSVCIVSS

C7

int

VGL

VGH

C1VGH

C22P

C16


C11+

C1 5REGP

VCL

C31MVCI3

C22M

C12-C12+

C11-Vci1

VCIOUT

VCOMR

VGOFFOUT

VGOFFL

C20

C19

VCOMOUT

VCOMH

VREG1OUT

VREG2OUT

C 21

C 11


(Vgoffadjustment)


adjustment)

VcomHadjustment

circuit


circuit

GVDDoutput

amplifier

VcomHoutput

amplifier

VcomLoutput

amplifier

VgoffHoutput


amplifier


circuit

C12

C9GVDD

VGOFFH

C10

Voltageadjustment

circuitRegulator

Charge-pump

circuit 1

C23PC23M

C21M

Charge-pump

circuit 2

C21P

C31P Charge-pump

circuit 3

C41-Vci4

C41+ Charge-pump

circuit 4

REGN

C14C17

AVDD

C18

C4

C3

C2

C6

VC1

C5

C3


AVDD

VGL

GVDD

VCOML





GRAMMSB LSB

PKP00PKP01PKP02

PKP10PKP11PKP12

PKP20PKP21PKP22

PKP30PKP31PKP32

PKP40PKP41PKP42

PKP50PKP51PKP52

PRP00PRP01PRP02

PRP10PRP11PRP12

VRP00VRP01VRP02

VRP10VRP11VRP12

VRP03

VRP13VRP14

PKN00PKN01PKN02

PKN10PKN11PKN12

PKN20PKN21PKN22

PKN30PKN31PKN32

PKN40PKN41PKN42

PKN50PKN51PKN52

PRN00PRN01PRN02

PRN10PRN11PRN12

VRN00VRN01VRN02

VRN10VRN11VRN12

VRN03

VRN13VRN14



GrayscaleAm plifier


ltRgt

LCD driver

64 grayscalecontrol

ltG gt

LCD driver

64 grayscalecontrol

ltBgt

LCD driver

64

V1

V0

V63

6 6 6

R G BLCD


Scan Mode

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176


11


01

G176 G175 G174 G173 hellip G4 G3 G2 G110

G1 G2 G3 G4 hellip G173 G174 G175 G17600

Scan ModeGSSM

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176


A

B

C

D

A

B

C

D






33 3 3 3 54333








G V D D

V G S


V I N P N 0

V I N P N 1

V I N P N 2

V I N P N 3

V I N P N 4

V I N P N 5

V I N P N 6

V I N P N 7

V 0

V 6 3

V 6 2

V 5 5

V 4 3

V 2 0

V 8

V 1V 2V 3

V 9

V 2 1

V 4 4

V 5 6V 5 7





Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge





8080Dummy Pad1195239742


Pad sizeum


UnitSize

Pad nameItems









Technology






25532V Process










Gat

e D

river

IC


Gat

e D

river

IC

T-Con

LTPS TFT-LCD


Source Driver IC

Gat

e D

river

IC

De-MUX






Outline









Digital vs Analog




TTL vs LVDS





XGA 325M (2 ports)

67M ( 1 port)

67M (2 ports)

SXGA 54M (2 ports)

54M (2 ports)

108M (2 ports)

Frequency

UXGA - 81M 162M LCD




6-bit ~80 ~60 ~50



RSDS Definition




8 Bit RGB RSDS Data

Start pulseR0 R1

R2 R3

R4 R5

G0 G1

G2 G3G4 G5

B0 B1

B2 B3

B4 B5

Invalid data

Invalid data

Invalid data

R6 R7

G6 G7

B6 B7



Single-end

FrontBack








Mini-LVDS

Data Bus Structure


Mini-LVDS

6 bit data 5 pairs


8 bit data 6 pairs

Mini-LVDS






TQFP100


RSDS vs Mini-LVDS













PPDSRSDSParameter



PPDSTM








PPDS Protocol





10-bit(1024灰階)


Memo









R

R

R

R

R

R

R

R

R

VRef

Vout

b2

b1

b0




Decoder-Based DAC



























3 2 1

1 2 33 2 1

2 4 8 2 2 2

Fout F ref ref In

In




= + + +LL

bull 4-bit example





















R-2R-based DAC


bull 4-bit example


11 1

_2 2 2

N Nref i R iF

R out F refi ii i


= =


sum sum













Current-mode DAC


ground potential

















across RF)









bull Glitches


















current sources












Examples of DAC 2





R-String DAC

R2

R2

R

R

R

R

R

R

R

b1b1

out

5

-19

b3b2b2 b3







ROM Decoder


Gamma Correction




Gamma Correction






Low noise






Output Buffer

DAC P

DAC N


OddOutput

EvenOutput

Gamma Voltage

(+)

Gamma Voltage

(-)

To data line

Rail to rail OP-AMP

-+

+-


Output Buffer

DAC P

negativebuffer


OddOutput

EvenOutput

Gamma Voltage

(+)

Gamma Voltage

(-)

To data line


PN type OP-AMP

DAC N

positivebuffer

+-

+-




Low deviation



Optimum OP AMP area



V1V2

+

-

Vss

Vdd

+

-+

-

Vout=Av(V1-V2)+

-





stage

High-gainstage

OutputBuffer


Bias Circuitry

Vout VoutrsquoV1V2





2




Hierarchy

Current to voltage

Current to voltage

voltage to current

voltage to current

conversion



(current mirror)





MOS diodeload


Class B (push-pull)

Currentstage

1stvoltagestage

2ndvoltagestage



Examples of Op-Amp





Design of Op Amp





1 Hand calculation









V-1005(L=1um)001(L=2um)

004(L=1um)001(L=2um)




Krsquo



symbol
















A(s)

F(s)

+

-ΣVin(s) Vout(s)

















need compensation




Z1 = gmIICC

CII gtgt CI CC



loop gain F(s)=1






and the RHP zero


C

m

C

mI

Cg

CgGB 2=cong

C

m

C

mI

m

II

mII

Cm

dsdsdsds

CmII

III

Cg

Cgz

Cg

Cgp

Cggggg

CgGGp

21

2

62

6

76421

))((

=cong

minus=

minuscong

++minus=

minuscong

Unit gain bandwidth






Cm

dsdsdsds

CmII

III

Cggggg

CgGGp

6

7642

1

))(( ++minus

=minus

cong








2

62 C

gCgp m

II

mII minus=

minuscong






VsCRsCgRV

sCRRV

sCRsCRgsV

CII

CmII

CII

II

CII

CIImout 1

)1(1

1

)1()( 66

+minusminus

=⎟⎟⎠

⎞⎜⎜⎝

⎛+

+⎟⎟⎠

⎞⎜⎜⎝

⎛+

minus=

Vrsquorsquo

Vout

VDD

CC

Vrsquo

++

--

M6

RII



IC1 IC2


VocOutput offset

between chip tochip




of gray m


Offset Cancellation

Voffset

VinVo=Vin+Voffset


Phase 1

Phase 2

Caz



Caz

Vo=Vin


+-

+ -

- +

- +

- +-+



Channel 384

Channel 383

Channel 382

Channel 381

Channel 4

Channel 3

Channel 2

Channel 1

Length

Height


Channel 420

Channel 419

Channel 418

Channel 417

Channel 4

Channel 3

Channel 2

Channel 1


Channel 480

Channel 479

Channel 478

Channel 477

Channel 4

Channel 3

Channel 2

Channel 1


resistor

Gammaresistor

Gammaresistor



TSMC HV Process




LCD Panel

Start pulse










dtdVCI times=

P = fdCloadVDD2

Turn on one clock




ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

clock

clock

Clock 2Clock 1

Clock 2Clock 1



Dual edge clocking

1 2 3 4

CK1XCK1CK2XCK2


Charge Sharing

To data line

DAC P


OddOutput

EvenOutput

OP

OPDAC NData

Data

Vgmama+

Vgmama-

-+

-+









CNS for Car

4~8mA

DSC Game PDA

2~3mA

05 ~ 2 mA

Mobile-phone


Large size panel









TV application


Outline









LCD TV Electronics

LCD Control Board


SDTV 720x480

cable


DCDC power




LCD Module

TTLLVDSTMDS

γ


OSD

Scaler

MCU

ADCAnalog

RGB

VideoDecoder

DigitalDVI

TMDSRx

De-interlace

Tuner

YC

SyncSep

Compositevideo

AntennaRF in

YCbCr

YPbPr



Digital TV System


MPEG2Decoder PODCI

32MB DDRSDRAM

Scaler IC







RESETRESET


SWITCHSWITCH



DiodesDiodes

LCDLCDDRIVERDRIVER


MICONMICON



INVERTERINVERTER


LCDLCDPANELPANEL

POWERAMPPOWERAMP




LA7585LA7585LA758788LA758788

LA7565LA7565


LA426061LA426061LA426570LA426570LA428082LA428082


LA7221LA7221









LA76818LA76818LA863228LA863228

FSS140132134FSS140132134CPH33043414CPH33043414


CPH5506CPH5506

LA426642674268LA426642674268LA427642774278LA427642774278








Black Insertion





DAC

γminus18R1 string

γminus22R2 string

γminus26R3 string

switch


Vref [118] Vout

8-bit Data


V0~V255




example



Over-8 bit data







Gn-1

Gn

Gray Level



Actual Response

Gn-1

Gn

Gray Level


Gn

Overdrive Response

Voltage by Driver







Overdrive Circuits

Memory

Lookup Table

Control ckts

Data

Dn

Dn+1

Ctrl

addressReadWrite

Datarsquo




ight

ness

Normal image

brig

htne

ss

bright imagebr

ight

ness


Other Technologies






LCD TV Trends


Size

BrightnessCR

Response Time

LCD Monitor

15-20rdquo

250400

25~16ms


Resolution XGA~UXGA

2002~2003

LCD TV


400~550500~700 gt550gt2k

25~16ms 16~12ms lt 8 ms

160160 176176


2004~2008

challenge

COST


Outline








TFTTFT



Controller025 μm

Sourcedriver05 μm


Gatedriver

06 μm HV



HV

Single chipHV

4 Chip TCPCOF Type

2 Chip COGCOF Type

1 Chip COG Type


HitachiSamsung

奇景聯詠

智寶科技







PWR SRAMGAMA64

APRSRAM

Gate Driver

PWR



18

64

18


Gate control

PowerSupplyCircuit

TimingGenerator

OSCSystem Interface


Indexregister

Controlregister

graylevelgenerator




Gammaadjusting

Addresscounter

VGHVGL

VgoffGVDDVGS

AVDD

18

G17

7G

176

G17

5 G

2G

1G

0

S396

S395

S394

S3 S2 S1

SPIC

ontrol

RW

Data

VDD3VDD

Latch circuitand

Vcom


Voltage Setting


VDD(20V ~ 33V)


VCI(25V ~ 33V)

BT2-0

BT2-0

VRH3-0

VREG2OUT

VCOM4-0

VGH(+9 ~ +165V)

AVDD(+35~ +55V)


VCL

VgoffH (to -50V)


VGL (-165 to -9V)

-1 times-1 times

VREG1OUT

VDV4-0

VCI1

VC2-0

VSS(0V)

VC3=1VRL3-0

GVDD(+30~ +50V)

VC3=0VRL3-0


Voltage Waveforms


sn(source output)

VCOM

Gn (Gate output)

VGH(+9 ~ +165V)


VgoffH (~to -50V)


GVDD(+30~ +50V)VDD(20V ~ 33V)

AVDD(+35~ +55V)

VSS(0V)






OVcomOUT


OVREG2OUT


OVREG1OUT


IOREGP





IOVCI



IOAVDD



-VDD

DescriptionIOSymbol




OVgoffL


OVgoffH



voltage

OVgoffOUT


IVgoff


higher than -150 V

OVGL



OVGH



OVcomL


OVcomH



IVcomR

DescriptionIOSymbol



mA2015-IVCI



by mode


Outputs


Outputs


Outputs





V5-3GVDD

V-5--16VGOFF

V-9--165VGL

V165-9VGH


V55-35AVDD

LCD Supply Voltage







Vcom


Vcom



Vgoff






V595583571VREG1OUT









VCI2

VCI VCI

VDDVSSVCIVSS

C7

int

VGL

VGH

C1VGH

C22P

C16


C11+

C1 5REGP

VCL

C31MVCI3

C22M

C12-C12+

C11-Vci1

VCIOUT

VCOMR

VGOFFOUT

VGOFFL

C20

C19

VCOMOUT

VCOMH

VREG1OUT

VREG2OUT

C 21

C 11


(Vgoffadjustment)


adjustment)

VcomHadjustment

circuit


circuit

GVDDoutput

amplifier

VcomHoutput

amplifier

VcomLoutput

amplifier

VgoffHoutput


amplifier


circuit

C12

C9GVDD

VGOFFH

C10

Voltageadjustment

circuitRegulator

Charge-pump

circuit 1

C23PC23M

C21M

Charge-pump

circuit 2

C21P

C31P Charge-pump

circuit 3

C41-Vci4

C41+ Charge-pump

circuit 4

REGN

C14C17

AVDD

C18

C4

C3

C2

C6

VC1

C5

C3


AVDD

VGL

GVDD

VCOML





GRAMMSB LSB

PKP00PKP01PKP02

PKP10PKP11PKP12

PKP20PKP21PKP22

PKP30PKP31PKP32

PKP40PKP41PKP42

PKP50PKP51PKP52

PRP00PRP01PRP02

PRP10PRP11PRP12

VRP00VRP01VRP02

VRP10VRP11VRP12

VRP03

VRP13VRP14

PKN00PKN01PKN02

PKN10PKN11PKN12

PKN20PKN21PKN22

PKN30PKN31PKN32

PKN40PKN41PKN42

PKN50PKN51PKN52

PRN00PRN01PRN02

PRN10PRN11PRN12

VRN00VRN01VRN02

VRN10VRN11VRN12

VRN03

VRN13VRN14



GrayscaleAm plifier


ltRgt

LCD driver

64 grayscalecontrol

ltG gt

LCD driver

64 grayscalecontrol

ltBgt

LCD driver

64

V1

V0

V63

6 6 6

R G BLCD


Scan Mode

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176


11


01

G176 G175 G174 G173 hellip G4 G3 G2 G110

G1 G2 G3 G4 hellip G173 G174 G175 G17600

Scan ModeGSSM

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176


A

B

C

D

A

B

C

D






33 3 3 3 54333








G V D D

V G S


V I N P N 0

V I N P N 1

V I N P N 2

V I N P N 3

V I N P N 4

V I N P N 5

V I N P N 6

V I N P N 7

V 0

V 6 3

V 6 2

V 5 5

V 4 3

V 2 0

V 8

V 1V 2V 3

V 9

V 2 1

V 4 4

V 5 6V 5 7





Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge





8080Dummy Pad1195239742


Pad sizeum


UnitSize

Pad nameItems









Technology






25532V Process










Gat

e D

river

IC


Gat

e D

river

IC

T-Con

LTPS TFT-LCD


Source Driver IC

Gat

e D

river

IC

De-MUX






Outline









Digital vs Analog




TTL vs LVDS





XGA 325M (2 ports)

67M ( 1 port)

67M (2 ports)

SXGA 54M (2 ports)

54M (2 ports)

108M (2 ports)

Frequency

UXGA - 81M 162M LCD




6-bit ~80 ~60 ~50



RSDS Definition




8 Bit RGB RSDS Data

Start pulseR0 R1

R2 R3

R4 R5

G0 G1

G2 G3G4 G5

B0 B1

B2 B3

B4 B5

Invalid data

Invalid data

Invalid data

R6 R7

G6 G7

B6 B7



Single-end

FrontBack








Mini-LVDS

Data Bus Structure


Mini-LVDS

6 bit data 5 pairs


8 bit data 6 pairs

Mini-LVDS






TQFP100


RSDS vs Mini-LVDS













PPDSRSDSParameter



PPDSTM








PPDS Protocol





10-bit(1024灰階)


Memo















3 2 1

1 2 33 2 1

2 4 8 2 2 2

Fout F ref ref In

In




= + + +LL

bull 4-bit example





















R-2R-based DAC


bull 4-bit example


11 1

_2 2 2

N Nref i R iF

R out F refi ii i


= =


sum sum













Current-mode DAC


ground potential

















across RF)









bull Glitches


















current sources












Examples of DAC 2





R-String DAC

R2

R2

R

R

R

R

R

R

R

b1b1

out

5

-19

b3b2b2 b3







ROM Decoder


Gamma Correction




Gamma Correction






Low noise






Output Buffer

DAC P

DAC N


OddOutput

EvenOutput

Gamma Voltage

(+)

Gamma Voltage

(-)

To data line

Rail to rail OP-AMP

-+

+-


Output Buffer

DAC P

negativebuffer


OddOutput

EvenOutput

Gamma Voltage

(+)

Gamma Voltage

(-)

To data line


PN type OP-AMP

DAC N

positivebuffer

+-

+-




Low deviation



Optimum OP AMP area



V1V2

+

-

Vss

Vdd

+

-+

-

Vout=Av(V1-V2)+

-





stage

High-gainstage

OutputBuffer


Bias Circuitry

Vout VoutrsquoV1V2





2




Hierarchy

Current to voltage

Current to voltage

voltage to current

voltage to current

conversion



(current mirror)





MOS diodeload


Class B (push-pull)

Currentstage

1stvoltagestage

2ndvoltagestage



Examples of Op-Amp





Design of Op Amp





1 Hand calculation









V-1005(L=1um)001(L=2um)

004(L=1um)001(L=2um)




Krsquo



symbol
















A(s)

F(s)

+

-ΣVin(s) Vout(s)

















need compensation




Z1 = gmIICC

CII gtgt CI CC



loop gain F(s)=1






and the RHP zero


C

m

C

mI

Cg

CgGB 2=cong

C

m

C

mI

m

II

mII

Cm

dsdsdsds

CmII

III

Cg

Cgz

Cg

Cgp

Cggggg

CgGGp

21

2

62

6

76421

))((

=cong

minus=

minuscong

++minus=

minuscong

Unit gain bandwidth






Cm

dsdsdsds

CmII

III

Cggggg

CgGGp

6

7642

1

))(( ++minus

=minus

cong








2

62 C

gCgp m

II

mII minus=

minuscong






VsCRsCgRV

sCRRV

sCRsCRgsV

CII

CmII

CII

II

CII

CIImout 1

)1(1

1

)1()( 66

+minusminus

=⎟⎟⎠

⎞⎜⎜⎝

⎛+

+⎟⎟⎠

⎞⎜⎜⎝

⎛+

minus=

Vrsquorsquo

Vout

VDD

CC

Vrsquo

++

--

M6

RII



IC1 IC2


VocOutput offset

between chip tochip




of gray m


Offset Cancellation

Voffset

VinVo=Vin+Voffset


Phase 1

Phase 2

Caz



Caz

Vo=Vin


+-

+ -

- +

- +

- +-+



Channel 384

Channel 383

Channel 382

Channel 381

Channel 4

Channel 3

Channel 2

Channel 1

Length

Height


Channel 420

Channel 419

Channel 418

Channel 417

Channel 4

Channel 3

Channel 2

Channel 1


Channel 480

Channel 479

Channel 478

Channel 477

Channel 4

Channel 3

Channel 2

Channel 1


resistor

Gammaresistor

Gammaresistor



TSMC HV Process




LCD Panel

Start pulse










dtdVCI times=

P = fdCloadVDD2

Turn on one clock




ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

clock

clock

Clock 2Clock 1

Clock 2Clock 1



Dual edge clocking

1 2 3 4

CK1XCK1CK2XCK2


Charge Sharing

To data line

DAC P


OddOutput

EvenOutput

OP

OPDAC NData

Data

Vgmama+

Vgmama-

-+

-+









CNS for Car

4~8mA

DSC Game PDA

2~3mA

05 ~ 2 mA

Mobile-phone


Large size panel









TV application


Outline









LCD TV Electronics

LCD Control Board


SDTV 720x480

cable


DCDC power




LCD Module

TTLLVDSTMDS

γ


OSD

Scaler

MCU

ADCAnalog

RGB

VideoDecoder

DigitalDVI

TMDSRx

De-interlace

Tuner

YC

SyncSep

Compositevideo

AntennaRF in

YCbCr

YPbPr



Digital TV System


MPEG2Decoder PODCI

32MB DDRSDRAM

Scaler IC







RESETRESET


SWITCHSWITCH



DiodesDiodes

LCDLCDDRIVERDRIVER


MICONMICON



INVERTERINVERTER


LCDLCDPANELPANEL

POWERAMPPOWERAMP




LA7585LA7585LA758788LA758788

LA7565LA7565


LA426061LA426061LA426570LA426570LA428082LA428082


LA7221LA7221









LA76818LA76818LA863228LA863228

FSS140132134FSS140132134CPH33043414CPH33043414


CPH5506CPH5506

LA426642674268LA426642674268LA427642774278LA427642774278








Black Insertion





DAC

γminus18R1 string

γminus22R2 string

γminus26R3 string

switch


Vref [118] Vout

8-bit Data


V0~V255




example



Over-8 bit data







Gn-1

Gn

Gray Level



Actual Response

Gn-1

Gn

Gray Level


Gn

Overdrive Response

Voltage by Driver







Overdrive Circuits

Memory

Lookup Table

Control ckts

Data

Dn

Dn+1

Ctrl

addressReadWrite

Datarsquo




ight

ness

Normal image

brig

htne

ss

bright imagebr

ight

ness


Other Technologies






LCD TV Trends


Size

BrightnessCR

Response Time

LCD Monitor

15-20rdquo

250400

25~16ms


Resolution XGA~UXGA

2002~2003

LCD TV


400~550500~700 gt550gt2k

25~16ms 16~12ms lt 8 ms

160160 176176


2004~2008

challenge

COST


Outline








TFTTFT



Controller025 μm

Sourcedriver05 μm


Gatedriver

06 μm HV



HV

Single chipHV

4 Chip TCPCOF Type

2 Chip COGCOF Type

1 Chip COG Type


HitachiSamsung

奇景聯詠

智寶科技







PWR SRAMGAMA64

APRSRAM

Gate Driver

PWR



18

64

18


Gate control

PowerSupplyCircuit

TimingGenerator

OSCSystem Interface


Indexregister

Controlregister

graylevelgenerator




Gammaadjusting

Addresscounter

VGHVGL

VgoffGVDDVGS

AVDD

18

G17

7G

176

G17

5 G

2G

1G

0

S396

S395

S394

S3 S2 S1

SPIC

ontrol

RW

Data

VDD3VDD

Latch circuitand

Vcom


Voltage Setting


VDD(20V ~ 33V)


VCI(25V ~ 33V)

BT2-0

BT2-0

VRH3-0

VREG2OUT

VCOM4-0

VGH(+9 ~ +165V)

AVDD(+35~ +55V)


VCL

VgoffH (to -50V)


VGL (-165 to -9V)

-1 times-1 times

VREG1OUT

VDV4-0

VCI1

VC2-0

VSS(0V)

VC3=1VRL3-0

GVDD(+30~ +50V)

VC3=0VRL3-0


Voltage Waveforms


sn(source output)

VCOM

Gn (Gate output)

VGH(+9 ~ +165V)


VgoffH (~to -50V)


GVDD(+30~ +50V)VDD(20V ~ 33V)

AVDD(+35~ +55V)

VSS(0V)






OVcomOUT


OVREG2OUT


OVREG1OUT


IOREGP





IOVCI



IOAVDD



-VDD

DescriptionIOSymbol




OVgoffL


OVgoffH



voltage

OVgoffOUT


IVgoff


higher than -150 V

OVGL



OVGH



OVcomL


OVcomH



IVcomR

DescriptionIOSymbol



mA2015-IVCI



by mode


Outputs


Outputs


Outputs





V5-3GVDD

V-5--16VGOFF

V-9--165VGL

V165-9VGH


V55-35AVDD

LCD Supply Voltage







Vcom


Vcom



Vgoff






V595583571VREG1OUT









VCI2

VCI VCI

VDDVSSVCIVSS

C7

int

VGL

VGH

C1VGH

C22P

C16


C11+

C1 5REGP

VCL

C31MVCI3

C22M

C12-C12+

C11-Vci1

VCIOUT

VCOMR

VGOFFOUT

VGOFFL

C20

C19

VCOMOUT

VCOMH

VREG1OUT

VREG2OUT

C 21

C 11


(Vgoffadjustment)


adjustment)

VcomHadjustment

circuit


circuit

GVDDoutput

amplifier

VcomHoutput

amplifier

VcomLoutput

amplifier

VgoffHoutput


amplifier


circuit

C12

C9GVDD

VGOFFH

C10

Voltageadjustment

circuitRegulator

Charge-pump

circuit 1

C23PC23M

C21M

Charge-pump

circuit 2

C21P

C31P Charge-pump

circuit 3

C41-Vci4

C41+ Charge-pump

circuit 4

REGN

C14C17

AVDD

C18

C4

C3

C2

C6

VC1

C5

C3


AVDD

VGL

GVDD

VCOML





GRAMMSB LSB

PKP00PKP01PKP02

PKP10PKP11PKP12

PKP20PKP21PKP22

PKP30PKP31PKP32

PKP40PKP41PKP42

PKP50PKP51PKP52

PRP00PRP01PRP02

PRP10PRP11PRP12

VRP00VRP01VRP02

VRP10VRP11VRP12

VRP03

VRP13VRP14

PKN00PKN01PKN02

PKN10PKN11PKN12

PKN20PKN21PKN22

PKN30PKN31PKN32

PKN40PKN41PKN42

PKN50PKN51PKN52

PRN00PRN01PRN02

PRN10PRN11PRN12

VRN00VRN01VRN02

VRN10VRN11VRN12

VRN03

VRN13VRN14



GrayscaleAm plifier


ltRgt

LCD driver

64 grayscalecontrol

ltG gt

LCD driver

64 grayscalecontrol

ltBgt

LCD driver

64

V1

V0

V63

6 6 6

R G BLCD


Scan Mode

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176


11


01

G176 G175 G174 G173 hellip G4 G3 G2 G110

G1 G2 G3 G4 hellip G173 G174 G175 G17600

Scan ModeGSSM

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176


A

B

C

D

A

B

C

D






33 3 3 3 54333








G V D D

V G S


V I N P N 0

V I N P N 1

V I N P N 2

V I N P N 3

V I N P N 4

V I N P N 5

V I N P N 6

V I N P N 7

V 0

V 6 3

V 6 2

V 5 5

V 4 3

V 2 0

V 8

V 1V 2V 3

V 9

V 2 1

V 4 4

V 5 6V 5 7





Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge





8080Dummy Pad1195239742


Pad sizeum


UnitSize

Pad nameItems









Technology






25532V Process










Gat

e D

river

IC


Gat

e D

river

IC

T-Con

LTPS TFT-LCD


Source Driver IC

Gat

e D

river

IC

De-MUX






Outline









Digital vs Analog




TTL vs LVDS





XGA 325M (2 ports)

67M ( 1 port)

67M (2 ports)

SXGA 54M (2 ports)

54M (2 ports)

108M (2 ports)

Frequency

UXGA - 81M 162M LCD




6-bit ~80 ~60 ~50



RSDS Definition




8 Bit RGB RSDS Data

Start pulseR0 R1

R2 R3

R4 R5

G0 G1

G2 G3G4 G5

B0 B1

B2 B3

B4 B5

Invalid data

Invalid data

Invalid data

R6 R7

G6 G7

B6 B7



Single-end

FrontBack








Mini-LVDS

Data Bus Structure


Mini-LVDS

6 bit data 5 pairs


8 bit data 6 pairs

Mini-LVDS






TQFP100


RSDS vs Mini-LVDS













PPDSRSDSParameter



PPDSTM








PPDS Protocol





10-bit(1024灰階)


Memo














R-2R-based DAC


bull 4-bit example


11 1

_2 2 2

N Nref i R iF

R out F refi ii i


= =


sum sum













Current-mode DAC


ground potential

















across RF)









bull Glitches


















current sources












Examples of DAC 2





R-String DAC

R2

R2

R

R

R

R

R

R

R

b1b1

out

5

-19

b3b2b2 b3







ROM Decoder


Gamma Correction




Gamma Correction






Low noise






Output Buffer

DAC P

DAC N


OddOutput

EvenOutput

Gamma Voltage

(+)

Gamma Voltage

(-)

To data line

Rail to rail OP-AMP

-+

+-


Output Buffer

DAC P

negativebuffer


OddOutput

EvenOutput

Gamma Voltage

(+)

Gamma Voltage

(-)

To data line


PN type OP-AMP

DAC N

positivebuffer

+-

+-




Low deviation



Optimum OP AMP area



V1V2

+

-

Vss

Vdd

+

-+

-

Vout=Av(V1-V2)+

-





stage

High-gainstage

OutputBuffer


Bias Circuitry

Vout VoutrsquoV1V2





2




Hierarchy

Current to voltage

Current to voltage

voltage to current

voltage to current

conversion



(current mirror)





MOS diodeload


Class B (push-pull)

Currentstage

1stvoltagestage

2ndvoltagestage



Examples of Op-Amp





Design of Op Amp





1 Hand calculation









V-1005(L=1um)001(L=2um)

004(L=1um)001(L=2um)




Krsquo



symbol
















A(s)

F(s)

+

-ΣVin(s) Vout(s)

















need compensation




Z1 = gmIICC

CII gtgt CI CC



loop gain F(s)=1






and the RHP zero


C

m

C

mI

Cg

CgGB 2=cong

C

m

C

mI

m

II

mII

Cm

dsdsdsds

CmII

III

Cg

Cgz

Cg

Cgp

Cggggg

CgGGp

21

2

62

6

76421

))((

=cong

minus=

minuscong

++minus=

minuscong

Unit gain bandwidth






Cm

dsdsdsds

CmII

III

Cggggg

CgGGp

6

7642

1

))(( ++minus

=minus

cong








2

62 C

gCgp m

II

mII minus=

minuscong






VsCRsCgRV

sCRRV

sCRsCRgsV

CII

CmII

CII

II

CII

CIImout 1

)1(1

1

)1()( 66

+minusminus

=⎟⎟⎠

⎞⎜⎜⎝

⎛+

+⎟⎟⎠

⎞⎜⎜⎝

⎛+

minus=

Vrsquorsquo

Vout

VDD

CC

Vrsquo

++

--

M6

RII



IC1 IC2


VocOutput offset

between chip tochip




of gray m


Offset Cancellation

Voffset

VinVo=Vin+Voffset


Phase 1

Phase 2

Caz



Caz

Vo=Vin


+-

+ -

- +

- +

- +-+



Channel 384

Channel 383

Channel 382

Channel 381

Channel 4

Channel 3

Channel 2

Channel 1

Length

Height


Channel 420

Channel 419

Channel 418

Channel 417

Channel 4

Channel 3

Channel 2

Channel 1


Channel 480

Channel 479

Channel 478

Channel 477

Channel 4

Channel 3

Channel 2

Channel 1


resistor

Gammaresistor

Gammaresistor



TSMC HV Process




LCD Panel

Start pulse










dtdVCI times=

P = fdCloadVDD2

Turn on one clock




ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

clock

clock

Clock 2Clock 1

Clock 2Clock 1



Dual edge clocking

1 2 3 4

CK1XCK1CK2XCK2


Charge Sharing

To data line

DAC P


OddOutput

EvenOutput

OP

OPDAC NData

Data

Vgmama+

Vgmama-

-+

-+









CNS for Car

4~8mA

DSC Game PDA

2~3mA

05 ~ 2 mA

Mobile-phone


Large size panel









TV application


Outline









LCD TV Electronics

LCD Control Board


SDTV 720x480

cable


DCDC power




LCD Module

TTLLVDSTMDS

γ


OSD

Scaler

MCU

ADCAnalog

RGB

VideoDecoder

DigitalDVI

TMDSRx

De-interlace

Tuner

YC

SyncSep

Compositevideo

AntennaRF in

YCbCr

YPbPr



Digital TV System


MPEG2Decoder PODCI

32MB DDRSDRAM

Scaler IC







RESETRESET


SWITCHSWITCH



DiodesDiodes

LCDLCDDRIVERDRIVER


MICONMICON



INVERTERINVERTER


LCDLCDPANELPANEL

POWERAMPPOWERAMP




LA7585LA7585LA758788LA758788

LA7565LA7565


LA426061LA426061LA426570LA426570LA428082LA428082


LA7221LA7221









LA76818LA76818LA863228LA863228

FSS140132134FSS140132134CPH33043414CPH33043414


CPH5506CPH5506

LA426642674268LA426642674268LA427642774278LA427642774278








Black Insertion





DAC

γminus18R1 string

γminus22R2 string

γminus26R3 string

switch


Vref [118] Vout

8-bit Data


V0~V255




example



Over-8 bit data







Gn-1

Gn

Gray Level



Actual Response

Gn-1

Gn

Gray Level


Gn

Overdrive Response

Voltage by Driver







Overdrive Circuits

Memory

Lookup Table

Control ckts

Data

Dn

Dn+1

Ctrl

addressReadWrite

Datarsquo




ight

ness

Normal image

brig

htne

ss

bright imagebr

ight

ness


Other Technologies






LCD TV Trends


Size

BrightnessCR

Response Time

LCD Monitor

15-20rdquo

250400

25~16ms


Resolution XGA~UXGA

2002~2003

LCD TV


400~550500~700 gt550gt2k

25~16ms 16~12ms lt 8 ms

160160 176176


2004~2008

challenge

COST


Outline








TFTTFT



Controller025 μm

Sourcedriver05 μm


Gatedriver

06 μm HV



HV

Single chipHV

4 Chip TCPCOF Type

2 Chip COGCOF Type

1 Chip COG Type


HitachiSamsung

奇景聯詠

智寶科技







PWR SRAMGAMA64

APRSRAM

Gate Driver

PWR



18

64

18


Gate control

PowerSupplyCircuit

TimingGenerator

OSCSystem Interface


Indexregister

Controlregister

graylevelgenerator




Gammaadjusting

Addresscounter

VGHVGL

VgoffGVDDVGS

AVDD

18

G17

7G

176

G17

5 G

2G

1G

0

S396

S395

S394

S3 S2 S1

SPIC

ontrol

RW

Data

VDD3VDD

Latch circuitand

Vcom


Voltage Setting


VDD(20V ~ 33V)


VCI(25V ~ 33V)

BT2-0

BT2-0

VRH3-0

VREG2OUT

VCOM4-0

VGH(+9 ~ +165V)

AVDD(+35~ +55V)


VCL

VgoffH (to -50V)


VGL (-165 to -9V)

-1 times-1 times

VREG1OUT

VDV4-0

VCI1

VC2-0

VSS(0V)

VC3=1VRL3-0

GVDD(+30~ +50V)

VC3=0VRL3-0


Voltage Waveforms


sn(source output)

VCOM

Gn (Gate output)

VGH(+9 ~ +165V)


VgoffH (~to -50V)


GVDD(+30~ +50V)VDD(20V ~ 33V)

AVDD(+35~ +55V)

VSS(0V)






OVcomOUT


OVREG2OUT


OVREG1OUT


IOREGP





IOVCI



IOAVDD



-VDD

DescriptionIOSymbol




OVgoffL


OVgoffH



voltage

OVgoffOUT


IVgoff


higher than -150 V

OVGL



OVGH



OVcomL


OVcomH



IVcomR

DescriptionIOSymbol



mA2015-IVCI



by mode


Outputs


Outputs


Outputs





V5-3GVDD

V-5--16VGOFF

V-9--165VGL

V165-9VGH


V55-35AVDD

LCD Supply Voltage







Vcom


Vcom



Vgoff






V595583571VREG1OUT









VCI2

VCI VCI

VDDVSSVCIVSS

C7

int

VGL

VGH

C1VGH

C22P

C16


C11+

C1 5REGP

VCL

C31MVCI3

C22M

C12-C12+

C11-Vci1

VCIOUT

VCOMR

VGOFFOUT

VGOFFL

C20

C19

VCOMOUT

VCOMH

VREG1OUT

VREG2OUT

C 21

C 11


(Vgoffadjustment)


adjustment)

VcomHadjustment

circuit


circuit

GVDDoutput

amplifier

VcomHoutput

amplifier

VcomLoutput

amplifier

VgoffHoutput


amplifier


circuit

C12

C9GVDD

VGOFFH

C10

Voltageadjustment

circuitRegulator

Charge-pump

circuit 1

C23PC23M

C21M

Charge-pump

circuit 2

C21P

C31P Charge-pump

circuit 3

C41-Vci4

C41+ Charge-pump

circuit 4

REGN

C14C17

AVDD

C18

C4

C3

C2

C6

VC1

C5

C3


AVDD

VGL

GVDD

VCOML





GRAMMSB LSB

PKP00PKP01PKP02

PKP10PKP11PKP12

PKP20PKP21PKP22

PKP30PKP31PKP32

PKP40PKP41PKP42

PKP50PKP51PKP52

PRP00PRP01PRP02

PRP10PRP11PRP12

VRP00VRP01VRP02

VRP10VRP11VRP12

VRP03

VRP13VRP14

PKN00PKN01PKN02

PKN10PKN11PKN12

PKN20PKN21PKN22

PKN30PKN31PKN32

PKN40PKN41PKN42

PKN50PKN51PKN52

PRN00PRN01PRN02

PRN10PRN11PRN12

VRN00VRN01VRN02

VRN10VRN11VRN12

VRN03

VRN13VRN14



GrayscaleAm plifier


ltRgt

LCD driver

64 grayscalecontrol

ltG gt

LCD driver

64 grayscalecontrol

ltBgt

LCD driver

64

V1

V0

V63

6 6 6

R G BLCD


Scan Mode

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176


11


01

G176 G175 G174 G173 hellip G4 G3 G2 G110

G1 G2 G3 G4 hellip G173 G174 G175 G17600

Scan ModeGSSM

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176


A

B

C

D

A

B

C

D






33 3 3 3 54333








G V D D

V G S


V I N P N 0

V I N P N 1

V I N P N 2

V I N P N 3

V I N P N 4

V I N P N 5

V I N P N 6

V I N P N 7

V 0

V 6 3

V 6 2

V 5 5

V 4 3

V 2 0

V 8

V 1V 2V 3

V 9

V 2 1

V 4 4

V 5 6V 5 7





Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge





8080Dummy Pad1195239742


Pad sizeum


UnitSize

Pad nameItems









Technology






25532V Process










Gat

e D

river

IC


Gat

e D

river

IC

T-Con

LTPS TFT-LCD


Source Driver IC

Gat

e D

river

IC

De-MUX






Outline









Digital vs Analog




TTL vs LVDS





XGA 325M (2 ports)

67M ( 1 port)

67M (2 ports)

SXGA 54M (2 ports)

54M (2 ports)

108M (2 ports)

Frequency

UXGA - 81M 162M LCD




6-bit ~80 ~60 ~50



RSDS Definition




8 Bit RGB RSDS Data

Start pulseR0 R1

R2 R3

R4 R5

G0 G1

G2 G3G4 G5

B0 B1

B2 B3

B4 B5

Invalid data

Invalid data

Invalid data

R6 R7

G6 G7

B6 B7



Single-end

FrontBack








Mini-LVDS

Data Bus Structure


Mini-LVDS

6 bit data 5 pairs


8 bit data 6 pairs

Mini-LVDS






TQFP100


RSDS vs Mini-LVDS













PPDSRSDSParameter



PPDSTM








PPDS Protocol





10-bit(1024灰階)


Memo







Current-mode DAC


ground potential

















across RF)









bull Glitches


















current sources












Examples of DAC 2





R-String DAC

R2

R2

R

R

R

R

R

R

R

b1b1

out

5

-19

b3b2b2 b3







ROM Decoder


Gamma Correction




Gamma Correction






Low noise






Output Buffer

DAC P

DAC N


OddOutput

EvenOutput

Gamma Voltage

(+)

Gamma Voltage

(-)

To data line

Rail to rail OP-AMP

-+

+-


Output Buffer

DAC P

negativebuffer


OddOutput

EvenOutput

Gamma Voltage

(+)

Gamma Voltage

(-)

To data line


PN type OP-AMP

DAC N

positivebuffer

+-

+-




Low deviation



Optimum OP AMP area



V1V2

+

-

Vss

Vdd

+

-+

-

Vout=Av(V1-V2)+

-





stage

High-gainstage

OutputBuffer


Bias Circuitry

Vout VoutrsquoV1V2





2




Hierarchy

Current to voltage

Current to voltage

voltage to current

voltage to current

conversion



(current mirror)





MOS diodeload


Class B (push-pull)

Currentstage

1stvoltagestage

2ndvoltagestage



Examples of Op-Amp





Design of Op Amp





1 Hand calculation









V-1005(L=1um)001(L=2um)

004(L=1um)001(L=2um)




Krsquo



symbol
















A(s)

F(s)

+

-ΣVin(s) Vout(s)

















need compensation




Z1 = gmIICC

CII gtgt CI CC



loop gain F(s)=1






and the RHP zero


C

m

C

mI

Cg

CgGB 2=cong

C

m

C

mI

m

II

mII

Cm

dsdsdsds

CmII

III

Cg

Cgz

Cg

Cgp

Cggggg

CgGGp

21

2

62

6

76421

))((

=cong

minus=

minuscong

++minus=

minuscong

Unit gain bandwidth






Cm

dsdsdsds

CmII

III

Cggggg

CgGGp

6

7642

1

))(( ++minus

=minus

cong








2

62 C

gCgp m

II

mII minus=

minuscong






VsCRsCgRV

sCRRV

sCRsCRgsV

CII

CmII

CII

II

CII

CIImout 1

)1(1

1

)1()( 66

+minusminus

=⎟⎟⎠

⎞⎜⎜⎝

⎛+

+⎟⎟⎠

⎞⎜⎜⎝

⎛+

minus=

Vrsquorsquo

Vout

VDD

CC

Vrsquo

++

--

M6

RII



IC1 IC2


VocOutput offset

between chip tochip




of gray m


Offset Cancellation

Voffset

VinVo=Vin+Voffset


Phase 1

Phase 2

Caz



Caz

Vo=Vin


+-

+ -

- +

- +

- +-+



Channel 384

Channel 383

Channel 382

Channel 381

Channel 4

Channel 3

Channel 2

Channel 1

Length

Height


Channel 420

Channel 419

Channel 418

Channel 417

Channel 4

Channel 3

Channel 2

Channel 1


Channel 480

Channel 479

Channel 478

Channel 477

Channel 4

Channel 3

Channel 2

Channel 1


resistor

Gammaresistor

Gammaresistor



TSMC HV Process




LCD Panel

Start pulse










dtdVCI times=

P = fdCloadVDD2

Turn on one clock




ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

clock

clock

Clock 2Clock 1

Clock 2Clock 1



Dual edge clocking

1 2 3 4

CK1XCK1CK2XCK2


Charge Sharing

To data line

DAC P


OddOutput

EvenOutput

OP

OPDAC NData

Data

Vgmama+

Vgmama-

-+

-+









CNS for Car

4~8mA

DSC Game PDA

2~3mA

05 ~ 2 mA

Mobile-phone


Large size panel









TV application


Outline









LCD TV Electronics

LCD Control Board


SDTV 720x480

cable


DCDC power




LCD Module

TTLLVDSTMDS

γ


OSD

Scaler

MCU

ADCAnalog

RGB

VideoDecoder

DigitalDVI

TMDSRx

De-interlace

Tuner

YC

SyncSep

Compositevideo

AntennaRF in

YCbCr

YPbPr



Digital TV System


MPEG2Decoder PODCI

32MB DDRSDRAM

Scaler IC







RESETRESET


SWITCHSWITCH



DiodesDiodes

LCDLCDDRIVERDRIVER


MICONMICON



INVERTERINVERTER


LCDLCDPANELPANEL

POWERAMPPOWERAMP




LA7585LA7585LA758788LA758788

LA7565LA7565


LA426061LA426061LA426570LA426570LA428082LA428082


LA7221LA7221









LA76818LA76818LA863228LA863228

FSS140132134FSS140132134CPH33043414CPH33043414


CPH5506CPH5506

LA426642674268LA426642674268LA427642774278LA427642774278








Black Insertion





DAC

γminus18R1 string

γminus22R2 string

γminus26R3 string

switch


Vref [118] Vout

8-bit Data


V0~V255




example



Over-8 bit data







Gn-1

Gn

Gray Level



Actual Response

Gn-1

Gn

Gray Level


Gn

Overdrive Response

Voltage by Driver







Overdrive Circuits

Memory

Lookup Table

Control ckts

Data

Dn

Dn+1

Ctrl

addressReadWrite

Datarsquo




ight

ness

Normal image

brig

htne

ss

bright imagebr

ight

ness


Other Technologies






LCD TV Trends


Size

BrightnessCR

Response Time

LCD Monitor

15-20rdquo

250400

25~16ms


Resolution XGA~UXGA

2002~2003

LCD TV


400~550500~700 gt550gt2k

25~16ms 16~12ms lt 8 ms

160160 176176


2004~2008

challenge

COST


Outline








TFTTFT



Controller025 μm

Sourcedriver05 μm


Gatedriver

06 μm HV



HV

Single chipHV

4 Chip TCPCOF Type

2 Chip COGCOF Type

1 Chip COG Type


HitachiSamsung

奇景聯詠

智寶科技







PWR SRAMGAMA64

APRSRAM

Gate Driver

PWR



18

64

18


Gate control

PowerSupplyCircuit

TimingGenerator

OSCSystem Interface


Indexregister

Controlregister

graylevelgenerator




Gammaadjusting

Addresscounter

VGHVGL

VgoffGVDDVGS

AVDD

18

G17

7G

176

G17

5 G

2G

1G

0

S396

S395

S394

S3 S2 S1

SPIC

ontrol

RW

Data

VDD3VDD

Latch circuitand

Vcom


Voltage Setting


VDD(20V ~ 33V)


VCI(25V ~ 33V)

BT2-0

BT2-0

VRH3-0

VREG2OUT

VCOM4-0

VGH(+9 ~ +165V)

AVDD(+35~ +55V)


VCL

VgoffH (to -50V)


VGL (-165 to -9V)

-1 times-1 times

VREG1OUT

VDV4-0

VCI1

VC2-0

VSS(0V)

VC3=1VRL3-0

GVDD(+30~ +50V)

VC3=0VRL3-0


Voltage Waveforms


sn(source output)

VCOM

Gn (Gate output)

VGH(+9 ~ +165V)


VgoffH (~to -50V)


GVDD(+30~ +50V)VDD(20V ~ 33V)

AVDD(+35~ +55V)

VSS(0V)






OVcomOUT


OVREG2OUT


OVREG1OUT


IOREGP





IOVCI



IOAVDD



-VDD

DescriptionIOSymbol




OVgoffL


OVgoffH



voltage

OVgoffOUT


IVgoff


higher than -150 V

OVGL



OVGH



OVcomL


OVcomH



IVcomR

DescriptionIOSymbol



mA2015-IVCI



by mode


Outputs


Outputs


Outputs





V5-3GVDD

V-5--16VGOFF

V-9--165VGL

V165-9VGH


V55-35AVDD

LCD Supply Voltage







Vcom


Vcom



Vgoff






V595583571VREG1OUT









VCI2

VCI VCI

VDDVSSVCIVSS

C7

int

VGL

VGH

C1VGH

C22P

C16


C11+

C1 5REGP

VCL

C31MVCI3

C22M

C12-C12+

C11-Vci1

VCIOUT

VCOMR

VGOFFOUT

VGOFFL

C20

C19

VCOMOUT

VCOMH

VREG1OUT

VREG2OUT

C 21

C 11


(Vgoffadjustment)


adjustment)

VcomHadjustment

circuit


circuit

GVDDoutput

amplifier

VcomHoutput

amplifier

VcomLoutput

amplifier

VgoffHoutput


amplifier


circuit

C12

C9GVDD

VGOFFH

C10

Voltageadjustment

circuitRegulator

Charge-pump

circuit 1

C23PC23M

C21M

Charge-pump

circuit 2

C21P

C31P Charge-pump

circuit 3

C41-Vci4

C41+ Charge-pump

circuit 4

REGN

C14C17

AVDD

C18

C4

C3

C2

C6

VC1

C5

C3


AVDD

VGL

GVDD

VCOML





GRAMMSB LSB

PKP00PKP01PKP02

PKP10PKP11PKP12

PKP20PKP21PKP22

PKP30PKP31PKP32

PKP40PKP41PKP42

PKP50PKP51PKP52

PRP00PRP01PRP02

PRP10PRP11PRP12

VRP00VRP01VRP02

VRP10VRP11VRP12

VRP03

VRP13VRP14

PKN00PKN01PKN02

PKN10PKN11PKN12

PKN20PKN21PKN22

PKN30PKN31PKN32

PKN40PKN41PKN42

PKN50PKN51PKN52

PRN00PRN01PRN02

PRN10PRN11PRN12

VRN00VRN01VRN02

VRN10VRN11VRN12

VRN03

VRN13VRN14



GrayscaleAm plifier


ltRgt

LCD driver

64 grayscalecontrol

ltG gt

LCD driver

64 grayscalecontrol

ltBgt

LCD driver

64

V1

V0

V63

6 6 6

R G BLCD


Scan Mode

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176


11


01

G176 G175 G174 G173 hellip G4 G3 G2 G110

G1 G2 G3 G4 hellip G173 G174 G175 G17600

Scan ModeGSSM

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176


A

B

C

D

A

B

C

D






33 3 3 3 54333








G V D D

V G S


V I N P N 0

V I N P N 1

V I N P N 2

V I N P N 3

V I N P N 4

V I N P N 5

V I N P N 6

V I N P N 7

V 0

V 6 3

V 6 2

V 5 5

V 4 3

V 2 0

V 8

V 1V 2V 3

V 9

V 2 1

V 4 4

V 5 6V 5 7





Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge





8080Dummy Pad1195239742


Pad sizeum


UnitSize

Pad nameItems









Technology






25532V Process










Gat

e D

river

IC


Gat

e D

river

IC

T-Con

LTPS TFT-LCD


Source Driver IC

Gat

e D

river

IC

De-MUX






Outline









Digital vs Analog




TTL vs LVDS





XGA 325M (2 ports)

67M ( 1 port)

67M (2 ports)

SXGA 54M (2 ports)

54M (2 ports)

108M (2 ports)

Frequency

UXGA - 81M 162M LCD




6-bit ~80 ~60 ~50



RSDS Definition




8 Bit RGB RSDS Data

Start pulseR0 R1

R2 R3

R4 R5

G0 G1

G2 G3G4 G5

B0 B1

B2 B3

B4 B5

Invalid data

Invalid data

Invalid data

R6 R7

G6 G7

B6 B7



Single-end

FrontBack








Mini-LVDS

Data Bus Structure


Mini-LVDS

6 bit data 5 pairs


8 bit data 6 pairs

Mini-LVDS






TQFP100


RSDS vs Mini-LVDS













PPDSRSDSParameter



PPDSTM








PPDS Protocol





10-bit(1024灰階)


Memo




across RF)









bull Glitches


















current sources












Examples of DAC 2





R-String DAC

R2

R2

R

R

R

R

R

R

R

b1b1

out

5

-19

b3b2b2 b3







ROM Decoder


Gamma Correction




Gamma Correction






Low noise






Output Buffer

DAC P

DAC N


OddOutput

EvenOutput

Gamma Voltage

(+)

Gamma Voltage

(-)

To data line

Rail to rail OP-AMP

-+

+-


Output Buffer

DAC P

negativebuffer


OddOutput

EvenOutput

Gamma Voltage

(+)

Gamma Voltage

(-)

To data line


PN type OP-AMP

DAC N

positivebuffer

+-

+-




Low deviation



Optimum OP AMP area



V1V2

+

-

Vss

Vdd

+

-+

-

Vout=Av(V1-V2)+

-





stage

High-gainstage

OutputBuffer


Bias Circuitry

Vout VoutrsquoV1V2





2




Hierarchy

Current to voltage

Current to voltage

voltage to current

voltage to current

conversion



(current mirror)





MOS diodeload


Class B (push-pull)

Currentstage

1stvoltagestage

2ndvoltagestage



Examples of Op-Amp





Design of Op Amp





1 Hand calculation









V-1005(L=1um)001(L=2um)

004(L=1um)001(L=2um)




Krsquo



symbol
















A(s)

F(s)

+

-ΣVin(s) Vout(s)

















need compensation




Z1 = gmIICC

CII gtgt CI CC



loop gain F(s)=1






and the RHP zero


C

m

C

mI

Cg

CgGB 2=cong

C

m

C

mI

m

II

mII

Cm

dsdsdsds

CmII

III

Cg

Cgz

Cg

Cgp

Cggggg

CgGGp

21

2

62

6

76421

))((

=cong

minus=

minuscong

++minus=

minuscong

Unit gain bandwidth






Cm

dsdsdsds

CmII

III

Cggggg

CgGGp

6

7642

1

))(( ++minus

=minus

cong








2

62 C

gCgp m

II

mII minus=

minuscong






VsCRsCgRV

sCRRV

sCRsCRgsV

CII

CmII

CII

II

CII

CIImout 1

)1(1

1

)1()( 66

+minusminus

=⎟⎟⎠

⎞⎜⎜⎝

⎛+

+⎟⎟⎠

⎞⎜⎜⎝

⎛+

minus=

Vrsquorsquo

Vout

VDD

CC

Vrsquo

++

--

M6

RII



IC1 IC2


VocOutput offset

between chip tochip




of gray m


Offset Cancellation

Voffset

VinVo=Vin+Voffset


Phase 1

Phase 2

Caz



Caz

Vo=Vin


+-

+ -

- +

- +

- +-+



Channel 384

Channel 383

Channel 382

Channel 381

Channel 4

Channel 3

Channel 2

Channel 1

Length

Height


Channel 420

Channel 419

Channel 418

Channel 417

Channel 4

Channel 3

Channel 2

Channel 1


Channel 480

Channel 479

Channel 478

Channel 477

Channel 4

Channel 3

Channel 2

Channel 1


resistor

Gammaresistor

Gammaresistor



TSMC HV Process




LCD Panel

Start pulse










dtdVCI times=

P = fdCloadVDD2

Turn on one clock




ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

clock

clock

Clock 2Clock 1

Clock 2Clock 1



Dual edge clocking

1 2 3 4

CK1XCK1CK2XCK2


Charge Sharing

To data line

DAC P


OddOutput

EvenOutput

OP

OPDAC NData

Data

Vgmama+

Vgmama-

-+

-+









CNS for Car

4~8mA

DSC Game PDA

2~3mA

05 ~ 2 mA

Mobile-phone


Large size panel









TV application


Outline









LCD TV Electronics

LCD Control Board


SDTV 720x480

cable


DCDC power




LCD Module

TTLLVDSTMDS

γ


OSD

Scaler

MCU

ADCAnalog

RGB

VideoDecoder

DigitalDVI

TMDSRx

De-interlace

Tuner

YC

SyncSep

Compositevideo

AntennaRF in

YCbCr

YPbPr



Digital TV System


MPEG2Decoder PODCI

32MB DDRSDRAM

Scaler IC







RESETRESET


SWITCHSWITCH



DiodesDiodes

LCDLCDDRIVERDRIVER


MICONMICON



INVERTERINVERTER


LCDLCDPANELPANEL

POWERAMPPOWERAMP




LA7585LA7585LA758788LA758788

LA7565LA7565


LA426061LA426061LA426570LA426570LA428082LA428082


LA7221LA7221









LA76818LA76818LA863228LA863228

FSS140132134FSS140132134CPH33043414CPH33043414


CPH5506CPH5506

LA426642674268LA426642674268LA427642774278LA427642774278








Black Insertion





DAC

γminus18R1 string

γminus22R2 string

γminus26R3 string

switch


Vref [118] Vout

8-bit Data


V0~V255




example



Over-8 bit data







Gn-1

Gn

Gray Level



Actual Response

Gn-1

Gn

Gray Level


Gn

Overdrive Response

Voltage by Driver







Overdrive Circuits

Memory

Lookup Table

Control ckts

Data

Dn

Dn+1

Ctrl

addressReadWrite

Datarsquo




ight

ness

Normal image

brig

htne

ss

bright imagebr

ight

ness


Other Technologies






LCD TV Trends


Size

BrightnessCR

Response Time

LCD Monitor

15-20rdquo

250400

25~16ms


Resolution XGA~UXGA

2002~2003

LCD TV


400~550500~700 gt550gt2k

25~16ms 16~12ms lt 8 ms

160160 176176


2004~2008

challenge

COST


Outline








TFTTFT



Controller025 μm

Sourcedriver05 μm


Gatedriver

06 μm HV



HV

Single chipHV

4 Chip TCPCOF Type

2 Chip COGCOF Type

1 Chip COG Type


HitachiSamsung

奇景聯詠

智寶科技







PWR SRAMGAMA64

APRSRAM

Gate Driver

PWR



18

64

18


Gate control

PowerSupplyCircuit

TimingGenerator

OSCSystem Interface


Indexregister

Controlregister

graylevelgenerator




Gammaadjusting

Addresscounter

VGHVGL

VgoffGVDDVGS

AVDD

18

G17

7G

176

G17

5 G

2G

1G

0

S396

S395

S394

S3 S2 S1

SPIC

ontrol

RW

Data

VDD3VDD

Latch circuitand

Vcom


Voltage Setting


VDD(20V ~ 33V)


VCI(25V ~ 33V)

BT2-0

BT2-0

VRH3-0

VREG2OUT

VCOM4-0

VGH(+9 ~ +165V)

AVDD(+35~ +55V)


VCL

VgoffH (to -50V)


VGL (-165 to -9V)

-1 times-1 times

VREG1OUT

VDV4-0

VCI1

VC2-0

VSS(0V)

VC3=1VRL3-0

GVDD(+30~ +50V)

VC3=0VRL3-0


Voltage Waveforms


sn(source output)

VCOM

Gn (Gate output)

VGH(+9 ~ +165V)


VgoffH (~to -50V)


GVDD(+30~ +50V)VDD(20V ~ 33V)

AVDD(+35~ +55V)

VSS(0V)






OVcomOUT


OVREG2OUT


OVREG1OUT


IOREGP





IOVCI



IOAVDD



-VDD

DescriptionIOSymbol




OVgoffL


OVgoffH



voltage

OVgoffOUT


IVgoff


higher than -150 V

OVGL



OVGH



OVcomL


OVcomH



IVcomR

DescriptionIOSymbol



mA2015-IVCI



by mode


Outputs


Outputs


Outputs





V5-3GVDD

V-5--16VGOFF

V-9--165VGL

V165-9VGH


V55-35AVDD

LCD Supply Voltage







Vcom


Vcom



Vgoff






V595583571VREG1OUT









VCI2

VCI VCI

VDDVSSVCIVSS

C7

int

VGL

VGH

C1VGH

C22P

C16


C11+

C1 5REGP

VCL

C31MVCI3

C22M

C12-C12+

C11-Vci1

VCIOUT

VCOMR

VGOFFOUT

VGOFFL

C20

C19

VCOMOUT

VCOMH

VREG1OUT

VREG2OUT

C 21

C 11


(Vgoffadjustment)


adjustment)

VcomHadjustment

circuit


circuit

GVDDoutput

amplifier

VcomHoutput

amplifier

VcomLoutput

amplifier

VgoffHoutput


amplifier


circuit

C12

C9GVDD

VGOFFH

C10

Voltageadjustment

circuitRegulator

Charge-pump

circuit 1

C23PC23M

C21M

Charge-pump

circuit 2

C21P

C31P Charge-pump

circuit 3

C41-Vci4

C41+ Charge-pump

circuit 4

REGN

C14C17

AVDD

C18

C4

C3

C2

C6

VC1

C5

C3


AVDD

VGL

GVDD

VCOML





GRAMMSB LSB

PKP00PKP01PKP02

PKP10PKP11PKP12

PKP20PKP21PKP22

PKP30PKP31PKP32

PKP40PKP41PKP42

PKP50PKP51PKP52

PRP00PRP01PRP02

PRP10PRP11PRP12

VRP00VRP01VRP02

VRP10VRP11VRP12

VRP03

VRP13VRP14

PKN00PKN01PKN02

PKN10PKN11PKN12

PKN20PKN21PKN22

PKN30PKN31PKN32

PKN40PKN41PKN42

PKN50PKN51PKN52

PRN00PRN01PRN02

PRN10PRN11PRN12

VRN00VRN01VRN02

VRN10VRN11VRN12

VRN03

VRN13VRN14



GrayscaleAm plifier


ltRgt

LCD driver

64 grayscalecontrol

ltG gt

LCD driver

64 grayscalecontrol

ltBgt

LCD driver

64

V1

V0

V63

6 6 6

R G BLCD


Scan Mode

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176


11


01

G176 G175 G174 G173 hellip G4 G3 G2 G110

G1 G2 G3 G4 hellip G173 G174 G175 G17600

Scan ModeGSSM

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176


A

B

C

D

A

B

C

D






33 3 3 3 54333








G V D D

V G S


V I N P N 0

V I N P N 1

V I N P N 2

V I N P N 3

V I N P N 4

V I N P N 5

V I N P N 6

V I N P N 7

V 0

V 6 3

V 6 2

V 5 5

V 4 3

V 2 0

V 8

V 1V 2V 3

V 9

V 2 1

V 4 4

V 5 6V 5 7





Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge





8080Dummy Pad1195239742


Pad sizeum


UnitSize

Pad nameItems









Technology






25532V Process










Gat

e D

river

IC


Gat

e D

river

IC

T-Con

LTPS TFT-LCD


Source Driver IC

Gat

e D

river

IC

De-MUX






Outline









Digital vs Analog




TTL vs LVDS





XGA 325M (2 ports)

67M ( 1 port)

67M (2 ports)

SXGA 54M (2 ports)

54M (2 ports)

108M (2 ports)

Frequency

UXGA - 81M 162M LCD




6-bit ~80 ~60 ~50



RSDS Definition




8 Bit RGB RSDS Data

Start pulseR0 R1

R2 R3

R4 R5

G0 G1

G2 G3G4 G5

B0 B1

B2 B3

B4 B5

Invalid data

Invalid data

Invalid data

R6 R7

G6 G7

B6 B7



Single-end

FrontBack








Mini-LVDS

Data Bus Structure


Mini-LVDS

6 bit data 5 pairs


8 bit data 6 pairs

Mini-LVDS






TQFP100


RSDS vs Mini-LVDS













PPDSRSDSParameter



PPDSTM








PPDS Protocol





10-bit(1024灰階)


Memo







current sources












Examples of DAC 2





R-String DAC

R2

R2

R

R

R

R

R

R

R

b1b1

out

5

-19

b3b2b2 b3







ROM Decoder


Gamma Correction




Gamma Correction






Low noise






Output Buffer

DAC P

DAC N


OddOutput

EvenOutput

Gamma Voltage

(+)

Gamma Voltage

(-)

To data line

Rail to rail OP-AMP

-+

+-


Output Buffer

DAC P

negativebuffer


OddOutput

EvenOutput

Gamma Voltage

(+)

Gamma Voltage

(-)

To data line


PN type OP-AMP

DAC N

positivebuffer

+-

+-




Low deviation



Optimum OP AMP area



V1V2

+

-

Vss

Vdd

+

-+

-

Vout=Av(V1-V2)+

-





stage

High-gainstage

OutputBuffer


Bias Circuitry

Vout VoutrsquoV1V2





2




Hierarchy

Current to voltage

Current to voltage

voltage to current

voltage to current

conversion



(current mirror)





MOS diodeload


Class B (push-pull)

Currentstage

1stvoltagestage

2ndvoltagestage



Examples of Op-Amp





Design of Op Amp





1 Hand calculation









V-1005(L=1um)001(L=2um)

004(L=1um)001(L=2um)




Krsquo



symbol
















A(s)

F(s)

+

-ΣVin(s) Vout(s)

















need compensation




Z1 = gmIICC

CII gtgt CI CC



loop gain F(s)=1






and the RHP zero


C

m

C

mI

Cg

CgGB 2=cong

C

m

C

mI

m

II

mII

Cm

dsdsdsds

CmII

III

Cg

Cgz

Cg

Cgp

Cggggg

CgGGp

21

2

62

6

76421

))((

=cong

minus=

minuscong

++minus=

minuscong

Unit gain bandwidth






Cm

dsdsdsds

CmII

III

Cggggg

CgGGp

6

7642

1

))(( ++minus

=minus

cong








2

62 C

gCgp m

II

mII minus=

minuscong






VsCRsCgRV

sCRRV

sCRsCRgsV

CII

CmII

CII

II

CII

CIImout 1

)1(1

1

)1()( 66

+minusminus

=⎟⎟⎠

⎞⎜⎜⎝

⎛+

+⎟⎟⎠

⎞⎜⎜⎝

⎛+

minus=

Vrsquorsquo

Vout

VDD

CC

Vrsquo

++

--

M6

RII



IC1 IC2


VocOutput offset

between chip tochip




of gray m


Offset Cancellation

Voffset

VinVo=Vin+Voffset


Phase 1

Phase 2

Caz



Caz

Vo=Vin


+-

+ -

- +

- +

- +-+



Channel 384

Channel 383

Channel 382

Channel 381

Channel 4

Channel 3

Channel 2

Channel 1

Length

Height


Channel 420

Channel 419

Channel 418

Channel 417

Channel 4

Channel 3

Channel 2

Channel 1


Channel 480

Channel 479

Channel 478

Channel 477

Channel 4

Channel 3

Channel 2

Channel 1


resistor

Gammaresistor

Gammaresistor



TSMC HV Process




LCD Panel

Start pulse










dtdVCI times=

P = fdCloadVDD2

Turn on one clock




ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

clock

clock

Clock 2Clock 1

Clock 2Clock 1



Dual edge clocking

1 2 3 4

CK1XCK1CK2XCK2


Charge Sharing

To data line

DAC P


OddOutput

EvenOutput

OP

OPDAC NData

Data

Vgmama+

Vgmama-

-+

-+









CNS for Car

4~8mA

DSC Game PDA

2~3mA

05 ~ 2 mA

Mobile-phone


Large size panel









TV application


Outline









LCD TV Electronics

LCD Control Board


SDTV 720x480

cable


DCDC power




LCD Module

TTLLVDSTMDS

γ


OSD

Scaler

MCU

ADCAnalog

RGB

VideoDecoder

DigitalDVI

TMDSRx

De-interlace

Tuner

YC

SyncSep

Compositevideo

AntennaRF in

YCbCr

YPbPr



Digital TV System


MPEG2Decoder PODCI

32MB DDRSDRAM

Scaler IC







RESETRESET


SWITCHSWITCH



DiodesDiodes

LCDLCDDRIVERDRIVER


MICONMICON



INVERTERINVERTER


LCDLCDPANELPANEL

POWERAMPPOWERAMP




LA7585LA7585LA758788LA758788

LA7565LA7565


LA426061LA426061LA426570LA426570LA428082LA428082


LA7221LA7221









LA76818LA76818LA863228LA863228

FSS140132134FSS140132134CPH33043414CPH33043414


CPH5506CPH5506

LA426642674268LA426642674268LA427642774278LA427642774278








Black Insertion





DAC

γminus18R1 string

γminus22R2 string

γminus26R3 string

switch


Vref [118] Vout

8-bit Data


V0~V255




example



Over-8 bit data







Gn-1

Gn

Gray Level



Actual Response

Gn-1

Gn

Gray Level


Gn

Overdrive Response

Voltage by Driver







Overdrive Circuits

Memory

Lookup Table

Control ckts

Data

Dn

Dn+1

Ctrl

addressReadWrite

Datarsquo




ight

ness

Normal image

brig

htne

ss

bright imagebr

ight

ness


Other Technologies






LCD TV Trends


Size

BrightnessCR

Response Time

LCD Monitor

15-20rdquo

250400

25~16ms


Resolution XGA~UXGA

2002~2003

LCD TV


400~550500~700 gt550gt2k

25~16ms 16~12ms lt 8 ms

160160 176176


2004~2008

challenge

COST


Outline








TFTTFT



Controller025 μm

Sourcedriver05 μm


Gatedriver

06 μm HV



HV

Single chipHV

4 Chip TCPCOF Type

2 Chip COGCOF Type

1 Chip COG Type


HitachiSamsung

奇景聯詠

智寶科技







PWR SRAMGAMA64

APRSRAM

Gate Driver

PWR



18

64

18


Gate control

PowerSupplyCircuit

TimingGenerator

OSCSystem Interface


Indexregister

Controlregister

graylevelgenerator




Gammaadjusting

Addresscounter

VGHVGL

VgoffGVDDVGS

AVDD

18

G17

7G

176

G17

5 G

2G

1G

0

S396

S395

S394

S3 S2 S1

SPIC

ontrol

RW

Data

VDD3VDD

Latch circuitand

Vcom


Voltage Setting


VDD(20V ~ 33V)


VCI(25V ~ 33V)

BT2-0

BT2-0

VRH3-0

VREG2OUT

VCOM4-0

VGH(+9 ~ +165V)

AVDD(+35~ +55V)


VCL

VgoffH (to -50V)


VGL (-165 to -9V)

-1 times-1 times

VREG1OUT

VDV4-0

VCI1

VC2-0

VSS(0V)

VC3=1VRL3-0

GVDD(+30~ +50V)

VC3=0VRL3-0


Voltage Waveforms


sn(source output)

VCOM

Gn (Gate output)

VGH(+9 ~ +165V)


VgoffH (~to -50V)


GVDD(+30~ +50V)VDD(20V ~ 33V)

AVDD(+35~ +55V)

VSS(0V)






OVcomOUT


OVREG2OUT


OVREG1OUT


IOREGP





IOVCI



IOAVDD



-VDD

DescriptionIOSymbol




OVgoffL


OVgoffH



voltage

OVgoffOUT


IVgoff


higher than -150 V

OVGL



OVGH



OVcomL


OVcomH



IVcomR

DescriptionIOSymbol



mA2015-IVCI



by mode


Outputs


Outputs


Outputs





V5-3GVDD

V-5--16VGOFF

V-9--165VGL

V165-9VGH


V55-35AVDD

LCD Supply Voltage







Vcom


Vcom



Vgoff






V595583571VREG1OUT









VCI2

VCI VCI

VDDVSSVCIVSS

C7

int

VGL

VGH

C1VGH

C22P

C16


C11+

C1 5REGP

VCL

C31MVCI3

C22M

C12-C12+

C11-Vci1

VCIOUT

VCOMR

VGOFFOUT

VGOFFL

C20

C19

VCOMOUT

VCOMH

VREG1OUT

VREG2OUT

C 21

C 11


(Vgoffadjustment)


adjustment)

VcomHadjustment

circuit


circuit

GVDDoutput

amplifier

VcomHoutput

amplifier

VcomLoutput

amplifier

VgoffHoutput


amplifier


circuit

C12

C9GVDD

VGOFFH

C10

Voltageadjustment

circuitRegulator

Charge-pump

circuit 1

C23PC23M

C21M

Charge-pump

circuit 2

C21P

C31P Charge-pump

circuit 3

C41-Vci4

C41+ Charge-pump

circuit 4

REGN

C14C17

AVDD

C18

C4

C3

C2

C6

VC1

C5

C3


AVDD

VGL

GVDD

VCOML





GRAMMSB LSB

PKP00PKP01PKP02

PKP10PKP11PKP12

PKP20PKP21PKP22

PKP30PKP31PKP32

PKP40PKP41PKP42

PKP50PKP51PKP52

PRP00PRP01PRP02

PRP10PRP11PRP12

VRP00VRP01VRP02

VRP10VRP11VRP12

VRP03

VRP13VRP14

PKN00PKN01PKN02

PKN10PKN11PKN12

PKN20PKN21PKN22

PKN30PKN31PKN32

PKN40PKN41PKN42

PKN50PKN51PKN52

PRN00PRN01PRN02

PRN10PRN11PRN12

VRN00VRN01VRN02

VRN10VRN11VRN12

VRN03

VRN13VRN14



GrayscaleAm plifier


ltRgt

LCD driver

64 grayscalecontrol

ltG gt

LCD driver

64 grayscalecontrol

ltBgt

LCD driver

64

V1

V0

V63

6 6 6

R G BLCD


Scan Mode

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176


11


01

G176 G175 G174 G173 hellip G4 G3 G2 G110

G1 G2 G3 G4 hellip G173 G174 G175 G17600

Scan ModeGSSM

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176


A

B

C

D

A

B

C

D






33 3 3 3 54333








G V D D

V G S


V I N P N 0

V I N P N 1

V I N P N 2

V I N P N 3

V I N P N 4

V I N P N 5

V I N P N 6

V I N P N 7

V 0

V 6 3

V 6 2

V 5 5

V 4 3

V 2 0

V 8

V 1V 2V 3

V 9

V 2 1

V 4 4

V 5 6V 5 7





Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge





8080Dummy Pad1195239742


Pad sizeum


UnitSize

Pad nameItems









Technology






25532V Process










Gat

e D

river

IC


Gat

e D

river

IC

T-Con

LTPS TFT-LCD


Source Driver IC

Gat

e D

river

IC

De-MUX






Outline









Digital vs Analog




TTL vs LVDS





XGA 325M (2 ports)

67M ( 1 port)

67M (2 ports)

SXGA 54M (2 ports)

54M (2 ports)

108M (2 ports)

Frequency

UXGA - 81M 162M LCD




6-bit ~80 ~60 ~50



RSDS Definition




8 Bit RGB RSDS Data

Start pulseR0 R1

R2 R3

R4 R5

G0 G1

G2 G3G4 G5

B0 B1

B2 B3

B4 B5

Invalid data

Invalid data

Invalid data

R6 R7

G6 G7

B6 B7



Single-end

FrontBack








Mini-LVDS

Data Bus Structure


Mini-LVDS

6 bit data 5 pairs


8 bit data 6 pairs

Mini-LVDS






TQFP100


RSDS vs Mini-LVDS













PPDSRSDSParameter



PPDSTM








PPDS Protocol





10-bit(1024灰階)


Memo




R-String DAC

R2

R2

R

R

R

R

R

R

R

b1b1

out

5

-19

b3b2b2 b3







ROM Decoder


Gamma Correction




Gamma Correction






Low noise






Output Buffer

DAC P

DAC N


OddOutput

EvenOutput

Gamma Voltage

(+)

Gamma Voltage

(-)

To data line

Rail to rail OP-AMP

-+

+-


Output Buffer

DAC P

negativebuffer


OddOutput

EvenOutput

Gamma Voltage

(+)

Gamma Voltage

(-)

To data line


PN type OP-AMP

DAC N

positivebuffer

+-

+-




Low deviation



Optimum OP AMP area



V1V2

+

-

Vss

Vdd

+

-+

-

Vout=Av(V1-V2)+

-





stage

High-gainstage

OutputBuffer


Bias Circuitry

Vout VoutrsquoV1V2





2




Hierarchy

Current to voltage

Current to voltage

voltage to current

voltage to current

conversion



(current mirror)





MOS diodeload


Class B (push-pull)

Currentstage

1stvoltagestage

2ndvoltagestage



Examples of Op-Amp





Design of Op Amp





1 Hand calculation









V-1005(L=1um)001(L=2um)

004(L=1um)001(L=2um)




Krsquo



symbol
















A(s)

F(s)

+

-ΣVin(s) Vout(s)

















need compensation




Z1 = gmIICC

CII gtgt CI CC



loop gain F(s)=1






and the RHP zero


C

m

C

mI

Cg

CgGB 2=cong

C

m

C

mI

m

II

mII

Cm

dsdsdsds

CmII

III

Cg

Cgz

Cg

Cgp

Cggggg

CgGGp

21

2

62

6

76421

))((

=cong

minus=

minuscong

++minus=

minuscong

Unit gain bandwidth






Cm

dsdsdsds

CmII

III

Cggggg

CgGGp

6

7642

1

))(( ++minus

=minus

cong








2

62 C

gCgp m

II

mII minus=

minuscong






VsCRsCgRV

sCRRV

sCRsCRgsV

CII

CmII

CII

II

CII

CIImout 1

)1(1

1

)1()( 66

+minusminus

=⎟⎟⎠

⎞⎜⎜⎝

⎛+

+⎟⎟⎠

⎞⎜⎜⎝

⎛+

minus=

Vrsquorsquo

Vout

VDD

CC

Vrsquo

++

--

M6

RII



IC1 IC2


VocOutput offset

between chip tochip




of gray m


Offset Cancellation

Voffset

VinVo=Vin+Voffset


Phase 1

Phase 2

Caz



Caz

Vo=Vin


+-

+ -

- +

- +

- +-+



Channel 384

Channel 383

Channel 382

Channel 381

Channel 4

Channel 3

Channel 2

Channel 1

Length

Height


Channel 420

Channel 419

Channel 418

Channel 417

Channel 4

Channel 3

Channel 2

Channel 1


Channel 480

Channel 479

Channel 478

Channel 477

Channel 4

Channel 3

Channel 2

Channel 1


resistor

Gammaresistor

Gammaresistor



TSMC HV Process




LCD Panel

Start pulse










dtdVCI times=

P = fdCloadVDD2

Turn on one clock




ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

clock

clock

Clock 2Clock 1

Clock 2Clock 1



Dual edge clocking

1 2 3 4

CK1XCK1CK2XCK2


Charge Sharing

To data line

DAC P


OddOutput

EvenOutput

OP

OPDAC NData

Data

Vgmama+

Vgmama-

-+

-+









CNS for Car

4~8mA

DSC Game PDA

2~3mA

05 ~ 2 mA

Mobile-phone


Large size panel









TV application


Outline









LCD TV Electronics

LCD Control Board


SDTV 720x480

cable


DCDC power




LCD Module

TTLLVDSTMDS

γ


OSD

Scaler

MCU

ADCAnalog

RGB

VideoDecoder

DigitalDVI

TMDSRx

De-interlace

Tuner

YC

SyncSep

Compositevideo

AntennaRF in

YCbCr

YPbPr



Digital TV System


MPEG2Decoder PODCI

32MB DDRSDRAM

Scaler IC







RESETRESET


SWITCHSWITCH



DiodesDiodes

LCDLCDDRIVERDRIVER


MICONMICON



INVERTERINVERTER


LCDLCDPANELPANEL

POWERAMPPOWERAMP




LA7585LA7585LA758788LA758788

LA7565LA7565


LA426061LA426061LA426570LA426570LA428082LA428082


LA7221LA7221









LA76818LA76818LA863228LA863228

FSS140132134FSS140132134CPH33043414CPH33043414


CPH5506CPH5506

LA426642674268LA426642674268LA427642774278LA427642774278








Black Insertion





DAC

γminus18R1 string

γminus22R2 string

γminus26R3 string

switch


Vref [118] Vout

8-bit Data


V0~V255




example



Over-8 bit data







Gn-1

Gn

Gray Level



Actual Response

Gn-1

Gn

Gray Level


Gn

Overdrive Response

Voltage by Driver







Overdrive Circuits

Memory

Lookup Table

Control ckts

Data

Dn

Dn+1

Ctrl

addressReadWrite

Datarsquo




ight

ness

Normal image

brig

htne

ss

bright imagebr

ight

ness


Other Technologies






LCD TV Trends


Size

BrightnessCR

Response Time

LCD Monitor

15-20rdquo

250400

25~16ms


Resolution XGA~UXGA

2002~2003

LCD TV


400~550500~700 gt550gt2k

25~16ms 16~12ms lt 8 ms

160160 176176


2004~2008

challenge

COST


Outline








TFTTFT



Controller025 μm

Sourcedriver05 μm


Gatedriver

06 μm HV



HV

Single chipHV

4 Chip TCPCOF Type

2 Chip COGCOF Type

1 Chip COG Type


HitachiSamsung

奇景聯詠

智寶科技







PWR SRAMGAMA64

APRSRAM

Gate Driver

PWR



18

64

18


Gate control

PowerSupplyCircuit

TimingGenerator

OSCSystem Interface


Indexregister

Controlregister

graylevelgenerator




Gammaadjusting

Addresscounter

VGHVGL

VgoffGVDDVGS

AVDD

18

G17

7G

176

G17

5 G

2G

1G

0

S396

S395

S394

S3 S2 S1

SPIC

ontrol

RW

Data

VDD3VDD

Latch circuitand

Vcom


Voltage Setting


VDD(20V ~ 33V)


VCI(25V ~ 33V)

BT2-0

BT2-0

VRH3-0

VREG2OUT

VCOM4-0

VGH(+9 ~ +165V)

AVDD(+35~ +55V)


VCL

VgoffH (to -50V)


VGL (-165 to -9V)

-1 times-1 times

VREG1OUT

VDV4-0

VCI1

VC2-0

VSS(0V)

VC3=1VRL3-0

GVDD(+30~ +50V)

VC3=0VRL3-0


Voltage Waveforms


sn(source output)

VCOM

Gn (Gate output)

VGH(+9 ~ +165V)


VgoffH (~to -50V)


GVDD(+30~ +50V)VDD(20V ~ 33V)

AVDD(+35~ +55V)

VSS(0V)






OVcomOUT


OVREG2OUT


OVREG1OUT


IOREGP





IOVCI



IOAVDD



-VDD

DescriptionIOSymbol




OVgoffL


OVgoffH



voltage

OVgoffOUT


IVgoff


higher than -150 V

OVGL



OVGH



OVcomL


OVcomH



IVcomR

DescriptionIOSymbol



mA2015-IVCI



by mode


Outputs


Outputs


Outputs





V5-3GVDD

V-5--16VGOFF

V-9--165VGL

V165-9VGH


V55-35AVDD

LCD Supply Voltage







Vcom


Vcom



Vgoff






V595583571VREG1OUT









VCI2

VCI VCI

VDDVSSVCIVSS

C7

int

VGL

VGH

C1VGH

C22P

C16


C11+

C1 5REGP

VCL

C31MVCI3

C22M

C12-C12+

C11-Vci1

VCIOUT

VCOMR

VGOFFOUT

VGOFFL

C20

C19

VCOMOUT

VCOMH

VREG1OUT

VREG2OUT

C 21

C 11


(Vgoffadjustment)


adjustment)

VcomHadjustment

circuit


circuit

GVDDoutput

amplifier

VcomHoutput

amplifier

VcomLoutput

amplifier

VgoffHoutput


amplifier


circuit

C12

C9GVDD

VGOFFH

C10

Voltageadjustment

circuitRegulator

Charge-pump

circuit 1

C23PC23M

C21M

Charge-pump

circuit 2

C21P

C31P Charge-pump

circuit 3

C41-Vci4

C41+ Charge-pump

circuit 4

REGN

C14C17

AVDD

C18

C4

C3

C2

C6

VC1

C5

C3


AVDD

VGL

GVDD

VCOML





GRAMMSB LSB

PKP00PKP01PKP02

PKP10PKP11PKP12

PKP20PKP21PKP22

PKP30PKP31PKP32

PKP40PKP41PKP42

PKP50PKP51PKP52

PRP00PRP01PRP02

PRP10PRP11PRP12

VRP00VRP01VRP02

VRP10VRP11VRP12

VRP03

VRP13VRP14

PKN00PKN01PKN02

PKN10PKN11PKN12

PKN20PKN21PKN22

PKN30PKN31PKN32

PKN40PKN41PKN42

PKN50PKN51PKN52

PRN00PRN01PRN02

PRN10PRN11PRN12

VRN00VRN01VRN02

VRN10VRN11VRN12

VRN03

VRN13VRN14



GrayscaleAm plifier


ltRgt

LCD driver

64 grayscalecontrol

ltG gt

LCD driver

64 grayscalecontrol

ltBgt

LCD driver

64

V1

V0

V63

6 6 6

R G BLCD


Scan Mode

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176


11


01

G176 G175 G174 G173 hellip G4 G3 G2 G110

G1 G2 G3 G4 hellip G173 G174 G175 G17600

Scan ModeGSSM

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176


A

B

C

D

A

B

C

D






33 3 3 3 54333








G V D D

V G S


V I N P N 0

V I N P N 1

V I N P N 2

V I N P N 3

V I N P N 4

V I N P N 5

V I N P N 6

V I N P N 7

V 0

V 6 3

V 6 2

V 5 5

V 4 3

V 2 0

V 8

V 1V 2V 3

V 9

V 2 1

V 4 4

V 5 6V 5 7





Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge





8080Dummy Pad1195239742


Pad sizeum


UnitSize

Pad nameItems









Technology






25532V Process










Gat

e D

river

IC


Gat

e D

river

IC

T-Con

LTPS TFT-LCD


Source Driver IC

Gat

e D

river

IC

De-MUX






Outline









Digital vs Analog




TTL vs LVDS





XGA 325M (2 ports)

67M ( 1 port)

67M (2 ports)

SXGA 54M (2 ports)

54M (2 ports)

108M (2 ports)

Frequency

UXGA - 81M 162M LCD




6-bit ~80 ~60 ~50



RSDS Definition




8 Bit RGB RSDS Data

Start pulseR0 R1

R2 R3

R4 R5

G0 G1

G2 G3G4 G5

B0 B1

B2 B3

B4 B5

Invalid data

Invalid data

Invalid data

R6 R7

G6 G7

B6 B7



Single-end

FrontBack








Mini-LVDS

Data Bus Structure


Mini-LVDS

6 bit data 5 pairs


8 bit data 6 pairs

Mini-LVDS






TQFP100


RSDS vs Mini-LVDS













PPDSRSDSParameter



PPDSTM








PPDS Protocol





10-bit(1024灰階)


Memo


Gamma Correction




Gamma Correction






Low noise






Output Buffer

DAC P

DAC N


OddOutput

EvenOutput

Gamma Voltage

(+)

Gamma Voltage

(-)

To data line

Rail to rail OP-AMP

-+

+-


Output Buffer

DAC P

negativebuffer


OddOutput

EvenOutput

Gamma Voltage

(+)

Gamma Voltage

(-)

To data line


PN type OP-AMP

DAC N

positivebuffer

+-

+-




Low deviation



Optimum OP AMP area



V1V2

+

-

Vss

Vdd

+

-+

-

Vout=Av(V1-V2)+

-





stage

High-gainstage

OutputBuffer


Bias Circuitry

Vout VoutrsquoV1V2





2




Hierarchy

Current to voltage

Current to voltage

voltage to current

voltage to current

conversion



(current mirror)





MOS diodeload


Class B (push-pull)

Currentstage

1stvoltagestage

2ndvoltagestage



Examples of Op-Amp





Design of Op Amp





1 Hand calculation









V-1005(L=1um)001(L=2um)

004(L=1um)001(L=2um)




Krsquo



symbol
















A(s)

F(s)

+

-ΣVin(s) Vout(s)

















need compensation




Z1 = gmIICC

CII gtgt CI CC



loop gain F(s)=1






and the RHP zero


C

m

C

mI

Cg

CgGB 2=cong

C

m

C

mI

m

II

mII

Cm

dsdsdsds

CmII

III

Cg

Cgz

Cg

Cgp

Cggggg

CgGGp

21

2

62

6

76421

))((

=cong

minus=

minuscong

++minus=

minuscong

Unit gain bandwidth






Cm

dsdsdsds

CmII

III

Cggggg

CgGGp

6

7642

1

))(( ++minus

=minus

cong








2

62 C

gCgp m

II

mII minus=

minuscong






VsCRsCgRV

sCRRV

sCRsCRgsV

CII

CmII

CII

II

CII

CIImout 1

)1(1

1

)1()( 66

+minusminus

=⎟⎟⎠

⎞⎜⎜⎝

⎛+

+⎟⎟⎠

⎞⎜⎜⎝

⎛+

minus=

Vrsquorsquo

Vout

VDD

CC

Vrsquo

++

--

M6

RII



IC1 IC2


VocOutput offset

between chip tochip




of gray m


Offset Cancellation

Voffset

VinVo=Vin+Voffset


Phase 1

Phase 2

Caz



Caz

Vo=Vin


+-

+ -

- +

- +

- +-+



Channel 384

Channel 383

Channel 382

Channel 381

Channel 4

Channel 3

Channel 2

Channel 1

Length

Height


Channel 420

Channel 419

Channel 418

Channel 417

Channel 4

Channel 3

Channel 2

Channel 1


Channel 480

Channel 479

Channel 478

Channel 477

Channel 4

Channel 3

Channel 2

Channel 1


resistor

Gammaresistor

Gammaresistor



TSMC HV Process




LCD Panel

Start pulse










dtdVCI times=

P = fdCloadVDD2

Turn on one clock




ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

clock

clock

Clock 2Clock 1

Clock 2Clock 1



Dual edge clocking

1 2 3 4

CK1XCK1CK2XCK2


Charge Sharing

To data line

DAC P


OddOutput

EvenOutput

OP

OPDAC NData

Data

Vgmama+

Vgmama-

-+

-+









CNS for Car

4~8mA

DSC Game PDA

2~3mA

05 ~ 2 mA

Mobile-phone


Large size panel









TV application


Outline









LCD TV Electronics

LCD Control Board


SDTV 720x480

cable


DCDC power




LCD Module

TTLLVDSTMDS

γ


OSD

Scaler

MCU

ADCAnalog

RGB

VideoDecoder

DigitalDVI

TMDSRx

De-interlace

Tuner

YC

SyncSep

Compositevideo

AntennaRF in

YCbCr

YPbPr



Digital TV System


MPEG2Decoder PODCI

32MB DDRSDRAM

Scaler IC







RESETRESET


SWITCHSWITCH



DiodesDiodes

LCDLCDDRIVERDRIVER


MICONMICON



INVERTERINVERTER


LCDLCDPANELPANEL

POWERAMPPOWERAMP




LA7585LA7585LA758788LA758788

LA7565LA7565


LA426061LA426061LA426570LA426570LA428082LA428082


LA7221LA7221









LA76818LA76818LA863228LA863228

FSS140132134FSS140132134CPH33043414CPH33043414


CPH5506CPH5506

LA426642674268LA426642674268LA427642774278LA427642774278








Black Insertion





DAC

γminus18R1 string

γminus22R2 string

γminus26R3 string

switch


Vref [118] Vout

8-bit Data


V0~V255




example



Over-8 bit data







Gn-1

Gn

Gray Level



Actual Response

Gn-1

Gn

Gray Level


Gn

Overdrive Response

Voltage by Driver







Overdrive Circuits

Memory

Lookup Table

Control ckts

Data

Dn

Dn+1

Ctrl

addressReadWrite

Datarsquo




ight

ness

Normal image

brig

htne

ss

bright imagebr

ight

ness


Other Technologies






LCD TV Trends


Size

BrightnessCR

Response Time

LCD Monitor

15-20rdquo

250400

25~16ms


Resolution XGA~UXGA

2002~2003

LCD TV


400~550500~700 gt550gt2k

25~16ms 16~12ms lt 8 ms

160160 176176


2004~2008

challenge

COST


Outline








TFTTFT



Controller025 μm

Sourcedriver05 μm


Gatedriver

06 μm HV



HV

Single chipHV

4 Chip TCPCOF Type

2 Chip COGCOF Type

1 Chip COG Type


HitachiSamsung

奇景聯詠

智寶科技







PWR SRAMGAMA64

APRSRAM

Gate Driver

PWR



18

64

18


Gate control

PowerSupplyCircuit

TimingGenerator

OSCSystem Interface


Indexregister

Controlregister

graylevelgenerator




Gammaadjusting

Addresscounter

VGHVGL

VgoffGVDDVGS

AVDD

18

G17

7G

176

G17

5 G

2G

1G

0

S396

S395

S394

S3 S2 S1

SPIC

ontrol

RW

Data

VDD3VDD

Latch circuitand

Vcom


Voltage Setting


VDD(20V ~ 33V)


VCI(25V ~ 33V)

BT2-0

BT2-0

VRH3-0

VREG2OUT

VCOM4-0

VGH(+9 ~ +165V)

AVDD(+35~ +55V)


VCL

VgoffH (to -50V)


VGL (-165 to -9V)

-1 times-1 times

VREG1OUT

VDV4-0

VCI1

VC2-0

VSS(0V)

VC3=1VRL3-0

GVDD(+30~ +50V)

VC3=0VRL3-0


Voltage Waveforms


sn(source output)

VCOM

Gn (Gate output)

VGH(+9 ~ +165V)


VgoffH (~to -50V)


GVDD(+30~ +50V)VDD(20V ~ 33V)

AVDD(+35~ +55V)

VSS(0V)






OVcomOUT


OVREG2OUT


OVREG1OUT


IOREGP





IOVCI



IOAVDD



-VDD

DescriptionIOSymbol




OVgoffL


OVgoffH



voltage

OVgoffOUT


IVgoff


higher than -150 V

OVGL



OVGH



OVcomL


OVcomH



IVcomR

DescriptionIOSymbol



mA2015-IVCI



by mode


Outputs


Outputs


Outputs





V5-3GVDD

V-5--16VGOFF

V-9--165VGL

V165-9VGH


V55-35AVDD

LCD Supply Voltage







Vcom


Vcom



Vgoff






V595583571VREG1OUT









VCI2

VCI VCI

VDDVSSVCIVSS

C7

int

VGL

VGH

C1VGH

C22P

C16


C11+

C1 5REGP

VCL

C31MVCI3

C22M

C12-C12+

C11-Vci1

VCIOUT

VCOMR

VGOFFOUT

VGOFFL

C20

C19

VCOMOUT

VCOMH

VREG1OUT

VREG2OUT

C 21

C 11


(Vgoffadjustment)


adjustment)

VcomHadjustment

circuit


circuit

GVDDoutput

amplifier

VcomHoutput

amplifier

VcomLoutput

amplifier

VgoffHoutput


amplifier


circuit

C12

C9GVDD

VGOFFH

C10

Voltageadjustment

circuitRegulator

Charge-pump

circuit 1

C23PC23M

C21M

Charge-pump

circuit 2

C21P

C31P Charge-pump

circuit 3

C41-Vci4

C41+ Charge-pump

circuit 4

REGN

C14C17

AVDD

C18

C4

C3

C2

C6

VC1

C5

C3


AVDD

VGL

GVDD

VCOML





GRAMMSB LSB

PKP00PKP01PKP02

PKP10PKP11PKP12

PKP20PKP21PKP22

PKP30PKP31PKP32

PKP40PKP41PKP42

PKP50PKP51PKP52

PRP00PRP01PRP02

PRP10PRP11PRP12

VRP00VRP01VRP02

VRP10VRP11VRP12

VRP03

VRP13VRP14

PKN00PKN01PKN02

PKN10PKN11PKN12

PKN20PKN21PKN22

PKN30PKN31PKN32

PKN40PKN41PKN42

PKN50PKN51PKN52

PRN00PRN01PRN02

PRN10PRN11PRN12

VRN00VRN01VRN02

VRN10VRN11VRN12

VRN03

VRN13VRN14



GrayscaleAm plifier


ltRgt

LCD driver

64 grayscalecontrol

ltG gt

LCD driver

64 grayscalecontrol

ltBgt

LCD driver

64

V1

V0

V63

6 6 6

R G BLCD


Scan Mode

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176


11


01

G176 G175 G174 G173 hellip G4 G3 G2 G110

G1 G2 G3 G4 hellip G173 G174 G175 G17600

Scan ModeGSSM

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176


A

B

C

D

A

B

C

D






33 3 3 3 54333








G V D D

V G S


V I N P N 0

V I N P N 1

V I N P N 2

V I N P N 3

V I N P N 4

V I N P N 5

V I N P N 6

V I N P N 7

V 0

V 6 3

V 6 2

V 5 5

V 4 3

V 2 0

V 8

V 1V 2V 3

V 9

V 2 1

V 4 4

V 5 6V 5 7





Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge





8080Dummy Pad1195239742


Pad sizeum


UnitSize

Pad nameItems









Technology






25532V Process










Gat

e D

river

IC


Gat

e D

river

IC

T-Con

LTPS TFT-LCD


Source Driver IC

Gat

e D

river

IC

De-MUX






Outline









Digital vs Analog




TTL vs LVDS





XGA 325M (2 ports)

67M ( 1 port)

67M (2 ports)

SXGA 54M (2 ports)

54M (2 ports)

108M (2 ports)

Frequency

UXGA - 81M 162M LCD




6-bit ~80 ~60 ~50



RSDS Definition




8 Bit RGB RSDS Data

Start pulseR0 R1

R2 R3

R4 R5

G0 G1

G2 G3G4 G5

B0 B1

B2 B3

B4 B5

Invalid data

Invalid data

Invalid data

R6 R7

G6 G7

B6 B7



Single-end

FrontBack








Mini-LVDS

Data Bus Structure


Mini-LVDS

6 bit data 5 pairs


8 bit data 6 pairs

Mini-LVDS






TQFP100


RSDS vs Mini-LVDS













PPDSRSDSParameter



PPDSTM








PPDS Protocol





10-bit(1024灰階)


Memo


Output Buffer

DAC P

negativebuffer


OddOutput

EvenOutput

Gamma Voltage

(+)

Gamma Voltage

(-)

To data line


PN type OP-AMP

DAC N

positivebuffer

+-

+-




Low deviation



Optimum OP AMP area



V1V2

+

-

Vss

Vdd

+

-+

-

Vout=Av(V1-V2)+

-





stage

High-gainstage

OutputBuffer


Bias Circuitry

Vout VoutrsquoV1V2





2




Hierarchy

Current to voltage

Current to voltage

voltage to current

voltage to current

conversion



(current mirror)





MOS diodeload


Class B (push-pull)

Currentstage

1stvoltagestage

2ndvoltagestage



Examples of Op-Amp





Design of Op Amp





1 Hand calculation









V-1005(L=1um)001(L=2um)

004(L=1um)001(L=2um)




Krsquo



symbol
















A(s)

F(s)

+

-ΣVin(s) Vout(s)

















need compensation




Z1 = gmIICC

CII gtgt CI CC



loop gain F(s)=1






and the RHP zero


C

m

C

mI

Cg

CgGB 2=cong

C

m

C

mI

m

II

mII

Cm

dsdsdsds

CmII

III

Cg

Cgz

Cg

Cgp

Cggggg

CgGGp

21

2

62

6

76421

))((

=cong

minus=

minuscong

++minus=

minuscong

Unit gain bandwidth






Cm

dsdsdsds

CmII

III

Cggggg

CgGGp

6

7642

1

))(( ++minus

=minus

cong








2

62 C

gCgp m

II

mII minus=

minuscong






VsCRsCgRV

sCRRV

sCRsCRgsV

CII

CmII

CII

II

CII

CIImout 1

)1(1

1

)1()( 66

+minusminus

=⎟⎟⎠

⎞⎜⎜⎝

⎛+

+⎟⎟⎠

⎞⎜⎜⎝

⎛+

minus=

Vrsquorsquo

Vout

VDD

CC

Vrsquo

++

--

M6

RII



IC1 IC2


VocOutput offset

between chip tochip




of gray m


Offset Cancellation

Voffset

VinVo=Vin+Voffset


Phase 1

Phase 2

Caz



Caz

Vo=Vin


+-

+ -

- +

- +

- +-+



Channel 384

Channel 383

Channel 382

Channel 381

Channel 4

Channel 3

Channel 2

Channel 1

Length

Height


Channel 420

Channel 419

Channel 418

Channel 417

Channel 4

Channel 3

Channel 2

Channel 1


Channel 480

Channel 479

Channel 478

Channel 477

Channel 4

Channel 3

Channel 2

Channel 1


resistor

Gammaresistor

Gammaresistor



TSMC HV Process




LCD Panel

Start pulse










dtdVCI times=

P = fdCloadVDD2

Turn on one clock




ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

clock

clock

Clock 2Clock 1

Clock 2Clock 1



Dual edge clocking

1 2 3 4

CK1XCK1CK2XCK2


Charge Sharing

To data line

DAC P


OddOutput

EvenOutput

OP

OPDAC NData

Data

Vgmama+

Vgmama-

-+

-+









CNS for Car

4~8mA

DSC Game PDA

2~3mA

05 ~ 2 mA

Mobile-phone


Large size panel









TV application


Outline









LCD TV Electronics

LCD Control Board


SDTV 720x480

cable


DCDC power




LCD Module

TTLLVDSTMDS

γ


OSD

Scaler

MCU

ADCAnalog

RGB

VideoDecoder

DigitalDVI

TMDSRx

De-interlace

Tuner

YC

SyncSep

Compositevideo

AntennaRF in

YCbCr

YPbPr



Digital TV System


MPEG2Decoder PODCI

32MB DDRSDRAM

Scaler IC







RESETRESET


SWITCHSWITCH



DiodesDiodes

LCDLCDDRIVERDRIVER


MICONMICON



INVERTERINVERTER


LCDLCDPANELPANEL

POWERAMPPOWERAMP




LA7585LA7585LA758788LA758788

LA7565LA7565


LA426061LA426061LA426570LA426570LA428082LA428082


LA7221LA7221









LA76818LA76818LA863228LA863228

FSS140132134FSS140132134CPH33043414CPH33043414


CPH5506CPH5506

LA426642674268LA426642674268LA427642774278LA427642774278








Black Insertion





DAC

γminus18R1 string

γminus22R2 string

γminus26R3 string

switch


Vref [118] Vout

8-bit Data


V0~V255




example



Over-8 bit data







Gn-1

Gn

Gray Level



Actual Response

Gn-1

Gn

Gray Level


Gn

Overdrive Response

Voltage by Driver







Overdrive Circuits

Memory

Lookup Table

Control ckts

Data

Dn

Dn+1

Ctrl

addressReadWrite

Datarsquo




ight

ness

Normal image

brig

htne

ss

bright imagebr

ight

ness


Other Technologies






LCD TV Trends


Size

BrightnessCR

Response Time

LCD Monitor

15-20rdquo

250400

25~16ms


Resolution XGA~UXGA

2002~2003

LCD TV


400~550500~700 gt550gt2k

25~16ms 16~12ms lt 8 ms

160160 176176


2004~2008

challenge

COST


Outline








TFTTFT



Controller025 μm

Sourcedriver05 μm


Gatedriver

06 μm HV



HV

Single chipHV

4 Chip TCPCOF Type

2 Chip COGCOF Type

1 Chip COG Type


HitachiSamsung

奇景聯詠

智寶科技







PWR SRAMGAMA64

APRSRAM

Gate Driver

PWR



18

64

18


Gate control

PowerSupplyCircuit

TimingGenerator

OSCSystem Interface


Indexregister

Controlregister

graylevelgenerator




Gammaadjusting

Addresscounter

VGHVGL

VgoffGVDDVGS

AVDD

18

G17

7G

176

G17

5 G

2G

1G

0

S396

S395

S394

S3 S2 S1

SPIC

ontrol

RW

Data

VDD3VDD

Latch circuitand

Vcom


Voltage Setting


VDD(20V ~ 33V)


VCI(25V ~ 33V)

BT2-0

BT2-0

VRH3-0

VREG2OUT

VCOM4-0

VGH(+9 ~ +165V)

AVDD(+35~ +55V)


VCL

VgoffH (to -50V)


VGL (-165 to -9V)

-1 times-1 times

VREG1OUT

VDV4-0

VCI1

VC2-0

VSS(0V)

VC3=1VRL3-0

GVDD(+30~ +50V)

VC3=0VRL3-0


Voltage Waveforms


sn(source output)

VCOM

Gn (Gate output)

VGH(+9 ~ +165V)


VgoffH (~to -50V)


GVDD(+30~ +50V)VDD(20V ~ 33V)

AVDD(+35~ +55V)

VSS(0V)






OVcomOUT


OVREG2OUT


OVREG1OUT


IOREGP





IOVCI



IOAVDD



-VDD

DescriptionIOSymbol




OVgoffL


OVgoffH



voltage

OVgoffOUT


IVgoff


higher than -150 V

OVGL



OVGH



OVcomL


OVcomH



IVcomR

DescriptionIOSymbol



mA2015-IVCI



by mode


Outputs


Outputs


Outputs





V5-3GVDD

V-5--16VGOFF

V-9--165VGL

V165-9VGH


V55-35AVDD

LCD Supply Voltage







Vcom


Vcom



Vgoff






V595583571VREG1OUT









VCI2

VCI VCI

VDDVSSVCIVSS

C7

int

VGL

VGH

C1VGH

C22P

C16


C11+

C1 5REGP

VCL

C31MVCI3

C22M

C12-C12+

C11-Vci1

VCIOUT

VCOMR

VGOFFOUT

VGOFFL

C20

C19

VCOMOUT

VCOMH

VREG1OUT

VREG2OUT

C 21

C 11


(Vgoffadjustment)


adjustment)

VcomHadjustment

circuit


circuit

GVDDoutput

amplifier

VcomHoutput

amplifier

VcomLoutput

amplifier

VgoffHoutput


amplifier


circuit

C12

C9GVDD

VGOFFH

C10

Voltageadjustment

circuitRegulator

Charge-pump

circuit 1

C23PC23M

C21M

Charge-pump

circuit 2

C21P

C31P Charge-pump

circuit 3

C41-Vci4

C41+ Charge-pump

circuit 4

REGN

C14C17

AVDD

C18

C4

C3

C2

C6

VC1

C5

C3


AVDD

VGL

GVDD

VCOML





GRAMMSB LSB

PKP00PKP01PKP02

PKP10PKP11PKP12

PKP20PKP21PKP22

PKP30PKP31PKP32

PKP40PKP41PKP42

PKP50PKP51PKP52

PRP00PRP01PRP02

PRP10PRP11PRP12

VRP00VRP01VRP02

VRP10VRP11VRP12

VRP03

VRP13VRP14

PKN00PKN01PKN02

PKN10PKN11PKN12

PKN20PKN21PKN22

PKN30PKN31PKN32

PKN40PKN41PKN42

PKN50PKN51PKN52

PRN00PRN01PRN02

PRN10PRN11PRN12

VRN00VRN01VRN02

VRN10VRN11VRN12

VRN03

VRN13VRN14



GrayscaleAm plifier


ltRgt

LCD driver

64 grayscalecontrol

ltG gt

LCD driver

64 grayscalecontrol

ltBgt

LCD driver

64

V1

V0

V63

6 6 6

R G BLCD


Scan Mode

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176


11


01

G176 G175 G174 G173 hellip G4 G3 G2 G110

G1 G2 G3 G4 hellip G173 G174 G175 G17600

Scan ModeGSSM

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176


A

B

C

D

A

B

C

D






33 3 3 3 54333








G V D D

V G S


V I N P N 0

V I N P N 1

V I N P N 2

V I N P N 3

V I N P N 4

V I N P N 5

V I N P N 6

V I N P N 7

V 0

V 6 3

V 6 2

V 5 5

V 4 3

V 2 0

V 8

V 1V 2V 3

V 9

V 2 1

V 4 4

V 5 6V 5 7





Gra

ysca

le V

olta

ge

Gra

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le V

olta

ge

Gra

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le V

olta

ge

Gra

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le V

olta

ge





8080Dummy Pad1195239742


Pad sizeum


UnitSize

Pad nameItems









Technology






25532V Process










Gat

e D

river

IC


Gat

e D

river

IC

T-Con

LTPS TFT-LCD


Source Driver IC

Gat

e D

river

IC

De-MUX






Outline









Digital vs Analog




TTL vs LVDS





XGA 325M (2 ports)

67M ( 1 port)

67M (2 ports)

SXGA 54M (2 ports)

54M (2 ports)

108M (2 ports)

Frequency

UXGA - 81M 162M LCD




6-bit ~80 ~60 ~50



RSDS Definition




8 Bit RGB RSDS Data

Start pulseR0 R1

R2 R3

R4 R5

G0 G1

G2 G3G4 G5

B0 B1

B2 B3

B4 B5

Invalid data

Invalid data

Invalid data

R6 R7

G6 G7

B6 B7



Single-end

FrontBack








Mini-LVDS

Data Bus Structure


Mini-LVDS

6 bit data 5 pairs


8 bit data 6 pairs

Mini-LVDS






TQFP100


RSDS vs Mini-LVDS













PPDSRSDSParameter



PPDSTM








PPDS Protocol





10-bit(1024灰階)


Memo




2




Hierarchy

Current to voltage

Current to voltage

voltage to current

voltage to current

conversion



(current mirror)





MOS diodeload


Class B (push-pull)

Currentstage

1stvoltagestage

2ndvoltagestage



Examples of Op-Amp





Design of Op Amp





1 Hand calculation









V-1005(L=1um)001(L=2um)

004(L=1um)001(L=2um)




Krsquo



symbol
















A(s)

F(s)

+

-ΣVin(s) Vout(s)

















need compensation




Z1 = gmIICC

CII gtgt CI CC



loop gain F(s)=1






and the RHP zero


C

m

C

mI

Cg

CgGB 2=cong

C

m

C

mI

m

II

mII

Cm

dsdsdsds

CmII

III

Cg

Cgz

Cg

Cgp

Cggggg

CgGGp

21

2

62

6

76421

))((

=cong

minus=

minuscong

++minus=

minuscong

Unit gain bandwidth






Cm

dsdsdsds

CmII

III

Cggggg

CgGGp

6

7642

1

))(( ++minus

=minus

cong








2

62 C

gCgp m

II

mII minus=

minuscong






VsCRsCgRV

sCRRV

sCRsCRgsV

CII

CmII

CII

II

CII

CIImout 1

)1(1

1

)1()( 66

+minusminus

=⎟⎟⎠

⎞⎜⎜⎝

⎛+

+⎟⎟⎠

⎞⎜⎜⎝

⎛+

minus=

Vrsquorsquo

Vout

VDD

CC

Vrsquo

++

--

M6

RII



IC1 IC2


VocOutput offset

between chip tochip




of gray m


Offset Cancellation

Voffset

VinVo=Vin+Voffset


Phase 1

Phase 2

Caz



Caz

Vo=Vin


+-

+ -

- +

- +

- +-+



Channel 384

Channel 383

Channel 382

Channel 381

Channel 4

Channel 3

Channel 2

Channel 1

Length

Height


Channel 420

Channel 419

Channel 418

Channel 417

Channel 4

Channel 3

Channel 2

Channel 1


Channel 480

Channel 479

Channel 478

Channel 477

Channel 4

Channel 3

Channel 2

Channel 1


resistor

Gammaresistor

Gammaresistor



TSMC HV Process




LCD Panel

Start pulse










dtdVCI times=

P = fdCloadVDD2

Turn on one clock




ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

clock

clock

Clock 2Clock 1

Clock 2Clock 1



Dual edge clocking

1 2 3 4

CK1XCK1CK2XCK2


Charge Sharing

To data line

DAC P


OddOutput

EvenOutput

OP

OPDAC NData

Data

Vgmama+

Vgmama-

-+

-+









CNS for Car

4~8mA

DSC Game PDA

2~3mA

05 ~ 2 mA

Mobile-phone


Large size panel









TV application


Outline









LCD TV Electronics

LCD Control Board


SDTV 720x480

cable


DCDC power




LCD Module

TTLLVDSTMDS

γ


OSD

Scaler

MCU

ADCAnalog

RGB

VideoDecoder

DigitalDVI

TMDSRx

De-interlace

Tuner

YC

SyncSep

Compositevideo

AntennaRF in

YCbCr

YPbPr



Digital TV System


MPEG2Decoder PODCI

32MB DDRSDRAM

Scaler IC







RESETRESET


SWITCHSWITCH



DiodesDiodes

LCDLCDDRIVERDRIVER


MICONMICON



INVERTERINVERTER


LCDLCDPANELPANEL

POWERAMPPOWERAMP




LA7585LA7585LA758788LA758788

LA7565LA7565


LA426061LA426061LA426570LA426570LA428082LA428082


LA7221LA7221









LA76818LA76818LA863228LA863228

FSS140132134FSS140132134CPH33043414CPH33043414


CPH5506CPH5506

LA426642674268LA426642674268LA427642774278LA427642774278








Black Insertion





DAC

γminus18R1 string

γminus22R2 string

γminus26R3 string

switch


Vref [118] Vout

8-bit Data


V0~V255




example



Over-8 bit data







Gn-1

Gn

Gray Level



Actual Response

Gn-1

Gn

Gray Level


Gn

Overdrive Response

Voltage by Driver







Overdrive Circuits

Memory

Lookup Table

Control ckts

Data

Dn

Dn+1

Ctrl

addressReadWrite

Datarsquo




ight

ness

Normal image

brig

htne

ss

bright imagebr

ight

ness


Other Technologies






LCD TV Trends


Size

BrightnessCR

Response Time

LCD Monitor

15-20rdquo

250400

25~16ms


Resolution XGA~UXGA

2002~2003

LCD TV


400~550500~700 gt550gt2k

25~16ms 16~12ms lt 8 ms

160160 176176


2004~2008

challenge

COST


Outline








TFTTFT



Controller025 μm

Sourcedriver05 μm


Gatedriver

06 μm HV



HV

Single chipHV

4 Chip TCPCOF Type

2 Chip COGCOF Type

1 Chip COG Type


HitachiSamsung

奇景聯詠

智寶科技







PWR SRAMGAMA64

APRSRAM

Gate Driver

PWR



18

64

18


Gate control

PowerSupplyCircuit

TimingGenerator

OSCSystem Interface


Indexregister

Controlregister

graylevelgenerator




Gammaadjusting

Addresscounter

VGHVGL

VgoffGVDDVGS

AVDD

18

G17

7G

176

G17

5 G

2G

1G

0

S396

S395

S394

S3 S2 S1

SPIC

ontrol

RW

Data

VDD3VDD

Latch circuitand

Vcom


Voltage Setting


VDD(20V ~ 33V)


VCI(25V ~ 33V)

BT2-0

BT2-0

VRH3-0

VREG2OUT

VCOM4-0

VGH(+9 ~ +165V)

AVDD(+35~ +55V)


VCL

VgoffH (to -50V)


VGL (-165 to -9V)

-1 times-1 times

VREG1OUT

VDV4-0

VCI1

VC2-0

VSS(0V)

VC3=1VRL3-0

GVDD(+30~ +50V)

VC3=0VRL3-0


Voltage Waveforms


sn(source output)

VCOM

Gn (Gate output)

VGH(+9 ~ +165V)


VgoffH (~to -50V)


GVDD(+30~ +50V)VDD(20V ~ 33V)

AVDD(+35~ +55V)

VSS(0V)






OVcomOUT


OVREG2OUT


OVREG1OUT


IOREGP





IOVCI



IOAVDD



-VDD

DescriptionIOSymbol




OVgoffL


OVgoffH



voltage

OVgoffOUT


IVgoff


higher than -150 V

OVGL



OVGH



OVcomL


OVcomH



IVcomR

DescriptionIOSymbol



mA2015-IVCI



by mode


Outputs


Outputs


Outputs





V5-3GVDD

V-5--16VGOFF

V-9--165VGL

V165-9VGH


V55-35AVDD

LCD Supply Voltage







Vcom


Vcom



Vgoff






V595583571VREG1OUT









VCI2

VCI VCI

VDDVSSVCIVSS

C7

int

VGL

VGH

C1VGH

C22P

C16


C11+

C1 5REGP

VCL

C31MVCI3

C22M

C12-C12+

C11-Vci1

VCIOUT

VCOMR

VGOFFOUT

VGOFFL

C20

C19

VCOMOUT

VCOMH

VREG1OUT

VREG2OUT

C 21

C 11


(Vgoffadjustment)


adjustment)

VcomHadjustment

circuit


circuit

GVDDoutput

amplifier

VcomHoutput

amplifier

VcomLoutput

amplifier

VgoffHoutput


amplifier


circuit

C12

C9GVDD

VGOFFH

C10

Voltageadjustment

circuitRegulator

Charge-pump

circuit 1

C23PC23M

C21M

Charge-pump

circuit 2

C21P

C31P Charge-pump

circuit 3

C41-Vci4

C41+ Charge-pump

circuit 4

REGN

C14C17

AVDD

C18

C4

C3

C2

C6

VC1

C5

C3


AVDD

VGL

GVDD

VCOML





GRAMMSB LSB

PKP00PKP01PKP02

PKP10PKP11PKP12

PKP20PKP21PKP22

PKP30PKP31PKP32

PKP40PKP41PKP42

PKP50PKP51PKP52

PRP00PRP01PRP02

PRP10PRP11PRP12

VRP00VRP01VRP02

VRP10VRP11VRP12

VRP03

VRP13VRP14

PKN00PKN01PKN02

PKN10PKN11PKN12

PKN20PKN21PKN22

PKN30PKN31PKN32

PKN40PKN41PKN42

PKN50PKN51PKN52

PRN00PRN01PRN02

PRN10PRN11PRN12

VRN00VRN01VRN02

VRN10VRN11VRN12

VRN03

VRN13VRN14



GrayscaleAm plifier


ltRgt

LCD driver

64 grayscalecontrol

ltG gt

LCD driver

64 grayscalecontrol

ltBgt

LCD driver

64

V1

V0

V63

6 6 6

R G BLCD


Scan Mode

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176


11


01

G176 G175 G174 G173 hellip G4 G3 G2 G110

G1 G2 G3 G4 hellip G173 G174 G175 G17600

Scan ModeGSSM

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176


A

B

C

D

A

B

C

D






33 3 3 3 54333








G V D D

V G S


V I N P N 0

V I N P N 1

V I N P N 2

V I N P N 3

V I N P N 4

V I N P N 5

V I N P N 6

V I N P N 7

V 0

V 6 3

V 6 2

V 5 5

V 4 3

V 2 0

V 8

V 1V 2V 3

V 9

V 2 1

V 4 4

V 5 6V 5 7





Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge





8080Dummy Pad1195239742


Pad sizeum


UnitSize

Pad nameItems









Technology






25532V Process










Gat

e D

river

IC


Gat

e D

river

IC

T-Con

LTPS TFT-LCD


Source Driver IC

Gat

e D

river

IC

De-MUX






Outline









Digital vs Analog




TTL vs LVDS





XGA 325M (2 ports)

67M ( 1 port)

67M (2 ports)

SXGA 54M (2 ports)

54M (2 ports)

108M (2 ports)

Frequency

UXGA - 81M 162M LCD




6-bit ~80 ~60 ~50



RSDS Definition




8 Bit RGB RSDS Data

Start pulseR0 R1

R2 R3

R4 R5

G0 G1

G2 G3G4 G5

B0 B1

B2 B3

B4 B5

Invalid data

Invalid data

Invalid data

R6 R7

G6 G7

B6 B7



Single-end

FrontBack








Mini-LVDS

Data Bus Structure


Mini-LVDS

6 bit data 5 pairs


8 bit data 6 pairs

Mini-LVDS






TQFP100


RSDS vs Mini-LVDS













PPDSRSDSParameter



PPDSTM








PPDS Protocol





10-bit(1024灰階)


Memo







V-1005(L=1um)001(L=2um)

004(L=1um)001(L=2um)




Krsquo



symbol
















A(s)

F(s)

+

-ΣVin(s) Vout(s)

















need compensation




Z1 = gmIICC

CII gtgt CI CC



loop gain F(s)=1






and the RHP zero


C

m

C

mI

Cg

CgGB 2=cong

C

m

C

mI

m

II

mII

Cm

dsdsdsds

CmII

III

Cg

Cgz

Cg

Cgp

Cggggg

CgGGp

21

2

62

6

76421

))((

=cong

minus=

minuscong

++minus=

minuscong

Unit gain bandwidth






Cm

dsdsdsds

CmII

III

Cggggg

CgGGp

6

7642

1

))(( ++minus

=minus

cong








2

62 C

gCgp m

II

mII minus=

minuscong






VsCRsCgRV

sCRRV

sCRsCRgsV

CII

CmII

CII

II

CII

CIImout 1

)1(1

1

)1()( 66

+minusminus

=⎟⎟⎠

⎞⎜⎜⎝

⎛+

+⎟⎟⎠

⎞⎜⎜⎝

⎛+

minus=

Vrsquorsquo

Vout

VDD

CC

Vrsquo

++

--

M6

RII



IC1 IC2


VocOutput offset

between chip tochip




of gray m


Offset Cancellation

Voffset

VinVo=Vin+Voffset


Phase 1

Phase 2

Caz



Caz

Vo=Vin


+-

+ -

- +

- +

- +-+



Channel 384

Channel 383

Channel 382

Channel 381

Channel 4

Channel 3

Channel 2

Channel 1

Length

Height


Channel 420

Channel 419

Channel 418

Channel 417

Channel 4

Channel 3

Channel 2

Channel 1


Channel 480

Channel 479

Channel 478

Channel 477

Channel 4

Channel 3

Channel 2

Channel 1


resistor

Gammaresistor

Gammaresistor



TSMC HV Process




LCD Panel

Start pulse










dtdVCI times=

P = fdCloadVDD2

Turn on one clock




ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

clock

clock

Clock 2Clock 1

Clock 2Clock 1



Dual edge clocking

1 2 3 4

CK1XCK1CK2XCK2


Charge Sharing

To data line

DAC P


OddOutput

EvenOutput

OP

OPDAC NData

Data

Vgmama+

Vgmama-

-+

-+









CNS for Car

4~8mA

DSC Game PDA

2~3mA

05 ~ 2 mA

Mobile-phone


Large size panel









TV application


Outline









LCD TV Electronics

LCD Control Board


SDTV 720x480

cable


DCDC power




LCD Module

TTLLVDSTMDS

γ


OSD

Scaler

MCU

ADCAnalog

RGB

VideoDecoder

DigitalDVI

TMDSRx

De-interlace

Tuner

YC

SyncSep

Compositevideo

AntennaRF in

YCbCr

YPbPr



Digital TV System


MPEG2Decoder PODCI

32MB DDRSDRAM

Scaler IC







RESETRESET


SWITCHSWITCH



DiodesDiodes

LCDLCDDRIVERDRIVER


MICONMICON



INVERTERINVERTER


LCDLCDPANELPANEL

POWERAMPPOWERAMP




LA7585LA7585LA758788LA758788

LA7565LA7565


LA426061LA426061LA426570LA426570LA428082LA428082


LA7221LA7221









LA76818LA76818LA863228LA863228

FSS140132134FSS140132134CPH33043414CPH33043414


CPH5506CPH5506

LA426642674268LA426642674268LA427642774278LA427642774278








Black Insertion





DAC

γminus18R1 string

γminus22R2 string

γminus26R3 string

switch


Vref [118] Vout

8-bit Data


V0~V255




example



Over-8 bit data







Gn-1

Gn

Gray Level



Actual Response

Gn-1

Gn

Gray Level


Gn

Overdrive Response

Voltage by Driver







Overdrive Circuits

Memory

Lookup Table

Control ckts

Data

Dn

Dn+1

Ctrl

addressReadWrite

Datarsquo




ight

ness

Normal image

brig

htne

ss

bright imagebr

ight

ness


Other Technologies






LCD TV Trends


Size

BrightnessCR

Response Time

LCD Monitor

15-20rdquo

250400

25~16ms


Resolution XGA~UXGA

2002~2003

LCD TV


400~550500~700 gt550gt2k

25~16ms 16~12ms lt 8 ms

160160 176176


2004~2008

challenge

COST


Outline








TFTTFT



Controller025 μm

Sourcedriver05 μm


Gatedriver

06 μm HV



HV

Single chipHV

4 Chip TCPCOF Type

2 Chip COGCOF Type

1 Chip COG Type


HitachiSamsung

奇景聯詠

智寶科技







PWR SRAMGAMA64

APRSRAM

Gate Driver

PWR



18

64

18


Gate control

PowerSupplyCircuit

TimingGenerator

OSCSystem Interface


Indexregister

Controlregister

graylevelgenerator




Gammaadjusting

Addresscounter

VGHVGL

VgoffGVDDVGS

AVDD

18

G17

7G

176

G17

5 G

2G

1G

0

S396

S395

S394

S3 S2 S1

SPIC

ontrol

RW

Data

VDD3VDD

Latch circuitand

Vcom


Voltage Setting


VDD(20V ~ 33V)


VCI(25V ~ 33V)

BT2-0

BT2-0

VRH3-0

VREG2OUT

VCOM4-0

VGH(+9 ~ +165V)

AVDD(+35~ +55V)


VCL

VgoffH (to -50V)


VGL (-165 to -9V)

-1 times-1 times

VREG1OUT

VDV4-0

VCI1

VC2-0

VSS(0V)

VC3=1VRL3-0

GVDD(+30~ +50V)

VC3=0VRL3-0


Voltage Waveforms


sn(source output)

VCOM

Gn (Gate output)

VGH(+9 ~ +165V)


VgoffH (~to -50V)


GVDD(+30~ +50V)VDD(20V ~ 33V)

AVDD(+35~ +55V)

VSS(0V)






OVcomOUT


OVREG2OUT


OVREG1OUT


IOREGP





IOVCI



IOAVDD



-VDD

DescriptionIOSymbol




OVgoffL


OVgoffH



voltage

OVgoffOUT


IVgoff


higher than -150 V

OVGL



OVGH



OVcomL


OVcomH



IVcomR

DescriptionIOSymbol



mA2015-IVCI



by mode


Outputs


Outputs


Outputs





V5-3GVDD

V-5--16VGOFF

V-9--165VGL

V165-9VGH


V55-35AVDD

LCD Supply Voltage







Vcom


Vcom



Vgoff






V595583571VREG1OUT









VCI2

VCI VCI

VDDVSSVCIVSS

C7

int

VGL

VGH

C1VGH

C22P

C16


C11+

C1 5REGP

VCL

C31MVCI3

C22M

C12-C12+

C11-Vci1

VCIOUT

VCOMR

VGOFFOUT

VGOFFL

C20

C19

VCOMOUT

VCOMH

VREG1OUT

VREG2OUT

C 21

C 11


(Vgoffadjustment)


adjustment)

VcomHadjustment

circuit


circuit

GVDDoutput

amplifier

VcomHoutput

amplifier

VcomLoutput

amplifier

VgoffHoutput


amplifier


circuit

C12

C9GVDD

VGOFFH

C10

Voltageadjustment

circuitRegulator

Charge-pump

circuit 1

C23PC23M

C21M

Charge-pump

circuit 2

C21P

C31P Charge-pump

circuit 3

C41-Vci4

C41+ Charge-pump

circuit 4

REGN

C14C17

AVDD

C18

C4

C3

C2

C6

VC1

C5

C3


AVDD

VGL

GVDD

VCOML





GRAMMSB LSB

PKP00PKP01PKP02

PKP10PKP11PKP12

PKP20PKP21PKP22

PKP30PKP31PKP32

PKP40PKP41PKP42

PKP50PKP51PKP52

PRP00PRP01PRP02

PRP10PRP11PRP12

VRP00VRP01VRP02

VRP10VRP11VRP12

VRP03

VRP13VRP14

PKN00PKN01PKN02

PKN10PKN11PKN12

PKN20PKN21PKN22

PKN30PKN31PKN32

PKN40PKN41PKN42

PKN50PKN51PKN52

PRN00PRN01PRN02

PRN10PRN11PRN12

VRN00VRN01VRN02

VRN10VRN11VRN12

VRN03

VRN13VRN14



GrayscaleAm plifier


ltRgt

LCD driver

64 grayscalecontrol

ltG gt

LCD driver

64 grayscalecontrol

ltBgt

LCD driver

64

V1

V0

V63

6 6 6

R G BLCD


Scan Mode

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176


11


01

G176 G175 G174 G173 hellip G4 G3 G2 G110

G1 G2 G3 G4 hellip G173 G174 G175 G17600

Scan ModeGSSM

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176


A

B

C

D

A

B

C

D






33 3 3 3 54333








G V D D

V G S


V I N P N 0

V I N P N 1

V I N P N 2

V I N P N 3

V I N P N 4

V I N P N 5

V I N P N 6

V I N P N 7

V 0

V 6 3

V 6 2

V 5 5

V 4 3

V 2 0

V 8

V 1V 2V 3

V 9

V 2 1

V 4 4

V 5 6V 5 7





Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge





8080Dummy Pad1195239742


Pad sizeum


UnitSize

Pad nameItems









Technology






25532V Process










Gat

e D

river

IC


Gat

e D

river

IC

T-Con

LTPS TFT-LCD


Source Driver IC

Gat

e D

river

IC

De-MUX






Outline









Digital vs Analog




TTL vs LVDS





XGA 325M (2 ports)

67M ( 1 port)

67M (2 ports)

SXGA 54M (2 ports)

54M (2 ports)

108M (2 ports)

Frequency

UXGA - 81M 162M LCD




6-bit ~80 ~60 ~50



RSDS Definition




8 Bit RGB RSDS Data

Start pulseR0 R1

R2 R3

R4 R5

G0 G1

G2 G3G4 G5

B0 B1

B2 B3

B4 B5

Invalid data

Invalid data

Invalid data

R6 R7

G6 G7

B6 B7



Single-end

FrontBack








Mini-LVDS

Data Bus Structure


Mini-LVDS

6 bit data 5 pairs


8 bit data 6 pairs

Mini-LVDS






TQFP100


RSDS vs Mini-LVDS













PPDSRSDSParameter



PPDSTM








PPDS Protocol





10-bit(1024灰階)


Memo
















need compensation




Z1 = gmIICC

CII gtgt CI CC



loop gain F(s)=1






and the RHP zero


C

m

C

mI

Cg

CgGB 2=cong

C

m

C

mI

m

II

mII

Cm

dsdsdsds

CmII

III

Cg

Cgz

Cg

Cgp

Cggggg

CgGGp

21

2

62

6

76421

))((

=cong

minus=

minuscong

++minus=

minuscong

Unit gain bandwidth






Cm

dsdsdsds

CmII

III

Cggggg

CgGGp

6

7642

1

))(( ++minus

=minus

cong








2

62 C

gCgp m

II

mII minus=

minuscong






VsCRsCgRV

sCRRV

sCRsCRgsV

CII

CmII

CII

II

CII

CIImout 1

)1(1

1

)1()( 66

+minusminus

=⎟⎟⎠

⎞⎜⎜⎝

⎛+

+⎟⎟⎠

⎞⎜⎜⎝

⎛+

minus=

Vrsquorsquo

Vout

VDD

CC

Vrsquo

++

--

M6

RII



IC1 IC2


VocOutput offset

between chip tochip




of gray m


Offset Cancellation

Voffset

VinVo=Vin+Voffset


Phase 1

Phase 2

Caz



Caz

Vo=Vin


+-

+ -

- +

- +

- +-+



Channel 384

Channel 383

Channel 382

Channel 381

Channel 4

Channel 3

Channel 2

Channel 1

Length

Height


Channel 420

Channel 419

Channel 418

Channel 417

Channel 4

Channel 3

Channel 2

Channel 1


Channel 480

Channel 479

Channel 478

Channel 477

Channel 4

Channel 3

Channel 2

Channel 1


resistor

Gammaresistor

Gammaresistor



TSMC HV Process




LCD Panel

Start pulse










dtdVCI times=

P = fdCloadVDD2

Turn on one clock




ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

clock

clock

Clock 2Clock 1

Clock 2Clock 1



Dual edge clocking

1 2 3 4

CK1XCK1CK2XCK2


Charge Sharing

To data line

DAC P


OddOutput

EvenOutput

OP

OPDAC NData

Data

Vgmama+

Vgmama-

-+

-+









CNS for Car

4~8mA

DSC Game PDA

2~3mA

05 ~ 2 mA

Mobile-phone


Large size panel









TV application


Outline









LCD TV Electronics

LCD Control Board


SDTV 720x480

cable


DCDC power




LCD Module

TTLLVDSTMDS

γ


OSD

Scaler

MCU

ADCAnalog

RGB

VideoDecoder

DigitalDVI

TMDSRx

De-interlace

Tuner

YC

SyncSep

Compositevideo

AntennaRF in

YCbCr

YPbPr



Digital TV System


MPEG2Decoder PODCI

32MB DDRSDRAM

Scaler IC







RESETRESET


SWITCHSWITCH



DiodesDiodes

LCDLCDDRIVERDRIVER


MICONMICON



INVERTERINVERTER


LCDLCDPANELPANEL

POWERAMPPOWERAMP




LA7585LA7585LA758788LA758788

LA7565LA7565


LA426061LA426061LA426570LA426570LA428082LA428082


LA7221LA7221









LA76818LA76818LA863228LA863228

FSS140132134FSS140132134CPH33043414CPH33043414


CPH5506CPH5506

LA426642674268LA426642674268LA427642774278LA427642774278








Black Insertion





DAC

γminus18R1 string

γminus22R2 string

γminus26R3 string

switch


Vref [118] Vout

8-bit Data


V0~V255




example



Over-8 bit data







Gn-1

Gn

Gray Level



Actual Response

Gn-1

Gn

Gray Level


Gn

Overdrive Response

Voltage by Driver







Overdrive Circuits

Memory

Lookup Table

Control ckts

Data

Dn

Dn+1

Ctrl

addressReadWrite

Datarsquo




ight

ness

Normal image

brig

htne

ss

bright imagebr

ight

ness


Other Technologies






LCD TV Trends


Size

BrightnessCR

Response Time

LCD Monitor

15-20rdquo

250400

25~16ms


Resolution XGA~UXGA

2002~2003

LCD TV


400~550500~700 gt550gt2k

25~16ms 16~12ms lt 8 ms

160160 176176


2004~2008

challenge

COST


Outline








TFTTFT



Controller025 μm

Sourcedriver05 μm


Gatedriver

06 μm HV



HV

Single chipHV

4 Chip TCPCOF Type

2 Chip COGCOF Type

1 Chip COG Type


HitachiSamsung

奇景聯詠

智寶科技







PWR SRAMGAMA64

APRSRAM

Gate Driver

PWR



18

64

18


Gate control

PowerSupplyCircuit

TimingGenerator

OSCSystem Interface


Indexregister

Controlregister

graylevelgenerator




Gammaadjusting

Addresscounter

VGHVGL

VgoffGVDDVGS

AVDD

18

G17

7G

176

G17

5 G

2G

1G

0

S396

S395

S394

S3 S2 S1

SPIC

ontrol

RW

Data

VDD3VDD

Latch circuitand

Vcom


Voltage Setting


VDD(20V ~ 33V)


VCI(25V ~ 33V)

BT2-0

BT2-0

VRH3-0

VREG2OUT

VCOM4-0

VGH(+9 ~ +165V)

AVDD(+35~ +55V)


VCL

VgoffH (to -50V)


VGL (-165 to -9V)

-1 times-1 times

VREG1OUT

VDV4-0

VCI1

VC2-0

VSS(0V)

VC3=1VRL3-0

GVDD(+30~ +50V)

VC3=0VRL3-0


Voltage Waveforms


sn(source output)

VCOM

Gn (Gate output)

VGH(+9 ~ +165V)


VgoffH (~to -50V)


GVDD(+30~ +50V)VDD(20V ~ 33V)

AVDD(+35~ +55V)

VSS(0V)






OVcomOUT


OVREG2OUT


OVREG1OUT


IOREGP





IOVCI



IOAVDD



-VDD

DescriptionIOSymbol




OVgoffL


OVgoffH



voltage

OVgoffOUT


IVgoff


higher than -150 V

OVGL



OVGH



OVcomL


OVcomH



IVcomR

DescriptionIOSymbol



mA2015-IVCI



by mode


Outputs


Outputs


Outputs





V5-3GVDD

V-5--16VGOFF

V-9--165VGL

V165-9VGH


V55-35AVDD

LCD Supply Voltage







Vcom


Vcom



Vgoff






V595583571VREG1OUT









VCI2

VCI VCI

VDDVSSVCIVSS

C7

int

VGL

VGH

C1VGH

C22P

C16


C11+

C1 5REGP

VCL

C31MVCI3

C22M

C12-C12+

C11-Vci1

VCIOUT

VCOMR

VGOFFOUT

VGOFFL

C20

C19

VCOMOUT

VCOMH

VREG1OUT

VREG2OUT

C 21

C 11


(Vgoffadjustment)


adjustment)

VcomHadjustment

circuit


circuit

GVDDoutput

amplifier

VcomHoutput

amplifier

VcomLoutput

amplifier

VgoffHoutput


amplifier


circuit

C12

C9GVDD

VGOFFH

C10

Voltageadjustment

circuitRegulator

Charge-pump

circuit 1

C23PC23M

C21M

Charge-pump

circuit 2

C21P

C31P Charge-pump

circuit 3

C41-Vci4

C41+ Charge-pump

circuit 4

REGN

C14C17

AVDD

C18

C4

C3

C2

C6

VC1

C5

C3


AVDD

VGL

GVDD

VCOML





GRAMMSB LSB

PKP00PKP01PKP02

PKP10PKP11PKP12

PKP20PKP21PKP22

PKP30PKP31PKP32

PKP40PKP41PKP42

PKP50PKP51PKP52

PRP00PRP01PRP02

PRP10PRP11PRP12

VRP00VRP01VRP02

VRP10VRP11VRP12

VRP03

VRP13VRP14

PKN00PKN01PKN02

PKN10PKN11PKN12

PKN20PKN21PKN22

PKN30PKN31PKN32

PKN40PKN41PKN42

PKN50PKN51PKN52

PRN00PRN01PRN02

PRN10PRN11PRN12

VRN00VRN01VRN02

VRN10VRN11VRN12

VRN03

VRN13VRN14



GrayscaleAm plifier


ltRgt

LCD driver

64 grayscalecontrol

ltG gt

LCD driver

64 grayscalecontrol

ltBgt

LCD driver

64

V1

V0

V63

6 6 6

R G BLCD


Scan Mode

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176


11


01

G176 G175 G174 G173 hellip G4 G3 G2 G110

G1 G2 G3 G4 hellip G173 G174 G175 G17600

Scan ModeGSSM

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176


A

B

C

D

A

B

C

D






33 3 3 3 54333








G V D D

V G S


V I N P N 0

V I N P N 1

V I N P N 2

V I N P N 3

V I N P N 4

V I N P N 5

V I N P N 6

V I N P N 7

V 0

V 6 3

V 6 2

V 5 5

V 4 3

V 2 0

V 8

V 1V 2V 3

V 9

V 2 1

V 4 4

V 5 6V 5 7





Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge





8080Dummy Pad1195239742


Pad sizeum


UnitSize

Pad nameItems









Technology






25532V Process










Gat

e D

river

IC


Gat

e D

river

IC

T-Con

LTPS TFT-LCD


Source Driver IC

Gat

e D

river

IC

De-MUX






Outline









Digital vs Analog




TTL vs LVDS





XGA 325M (2 ports)

67M ( 1 port)

67M (2 ports)

SXGA 54M (2 ports)

54M (2 ports)

108M (2 ports)

Frequency

UXGA - 81M 162M LCD




6-bit ~80 ~60 ~50



RSDS Definition




8 Bit RGB RSDS Data

Start pulseR0 R1

R2 R3

R4 R5

G0 G1

G2 G3G4 G5

B0 B1

B2 B3

B4 B5

Invalid data

Invalid data

Invalid data

R6 R7

G6 G7

B6 B7



Single-end

FrontBack








Mini-LVDS

Data Bus Structure


Mini-LVDS

6 bit data 5 pairs


8 bit data 6 pairs

Mini-LVDS






TQFP100


RSDS vs Mini-LVDS













PPDSRSDSParameter



PPDSTM








PPDS Protocol





10-bit(1024灰階)


Memo



loop gain F(s)=1






and the RHP zero


C

m

C

mI

Cg

CgGB 2=cong

C

m

C

mI

m

II

mII

Cm

dsdsdsds

CmII

III

Cg

Cgz

Cg

Cgp

Cggggg

CgGGp

21

2

62

6

76421

))((

=cong

minus=

minuscong

++minus=

minuscong

Unit gain bandwidth






Cm

dsdsdsds

CmII

III

Cggggg

CgGGp

6

7642

1

))(( ++minus

=minus

cong








2

62 C

gCgp m

II

mII minus=

minuscong






VsCRsCgRV

sCRRV

sCRsCRgsV

CII

CmII

CII

II

CII

CIImout 1

)1(1

1

)1()( 66

+minusminus

=⎟⎟⎠

⎞⎜⎜⎝

⎛+

+⎟⎟⎠

⎞⎜⎜⎝

⎛+

minus=

Vrsquorsquo

Vout

VDD

CC

Vrsquo

++

--

M6

RII



IC1 IC2


VocOutput offset

between chip tochip




of gray m


Offset Cancellation

Voffset

VinVo=Vin+Voffset


Phase 1

Phase 2

Caz



Caz

Vo=Vin


+-

+ -

- +

- +

- +-+



Channel 384

Channel 383

Channel 382

Channel 381

Channel 4

Channel 3

Channel 2

Channel 1

Length

Height


Channel 420

Channel 419

Channel 418

Channel 417

Channel 4

Channel 3

Channel 2

Channel 1


Channel 480

Channel 479

Channel 478

Channel 477

Channel 4

Channel 3

Channel 2

Channel 1


resistor

Gammaresistor

Gammaresistor



TSMC HV Process




LCD Panel

Start pulse










dtdVCI times=

P = fdCloadVDD2

Turn on one clock




ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

clock

clock

Clock 2Clock 1

Clock 2Clock 1



Dual edge clocking

1 2 3 4

CK1XCK1CK2XCK2


Charge Sharing

To data line

DAC P


OddOutput

EvenOutput

OP

OPDAC NData

Data

Vgmama+

Vgmama-

-+

-+









CNS for Car

4~8mA

DSC Game PDA

2~3mA

05 ~ 2 mA

Mobile-phone


Large size panel









TV application


Outline









LCD TV Electronics

LCD Control Board


SDTV 720x480

cable


DCDC power




LCD Module

TTLLVDSTMDS

γ


OSD

Scaler

MCU

ADCAnalog

RGB

VideoDecoder

DigitalDVI

TMDSRx

De-interlace

Tuner

YC

SyncSep

Compositevideo

AntennaRF in

YCbCr

YPbPr



Digital TV System


MPEG2Decoder PODCI

32MB DDRSDRAM

Scaler IC







RESETRESET


SWITCHSWITCH



DiodesDiodes

LCDLCDDRIVERDRIVER


MICONMICON



INVERTERINVERTER


LCDLCDPANELPANEL

POWERAMPPOWERAMP




LA7585LA7585LA758788LA758788

LA7565LA7565


LA426061LA426061LA426570LA426570LA428082LA428082


LA7221LA7221









LA76818LA76818LA863228LA863228

FSS140132134FSS140132134CPH33043414CPH33043414


CPH5506CPH5506

LA426642674268LA426642674268LA427642774278LA427642774278








Black Insertion





DAC

γminus18R1 string

γminus22R2 string

γminus26R3 string

switch


Vref [118] Vout

8-bit Data


V0~V255




example



Over-8 bit data







Gn-1

Gn

Gray Level



Actual Response

Gn-1

Gn

Gray Level


Gn

Overdrive Response

Voltage by Driver







Overdrive Circuits

Memory

Lookup Table

Control ckts

Data

Dn

Dn+1

Ctrl

addressReadWrite

Datarsquo




ight

ness

Normal image

brig

htne

ss

bright imagebr

ight

ness


Other Technologies






LCD TV Trends


Size

BrightnessCR

Response Time

LCD Monitor

15-20rdquo

250400

25~16ms


Resolution XGA~UXGA

2002~2003

LCD TV


400~550500~700 gt550gt2k

25~16ms 16~12ms lt 8 ms

160160 176176


2004~2008

challenge

COST


Outline








TFTTFT



Controller025 μm

Sourcedriver05 μm


Gatedriver

06 μm HV



HV

Single chipHV

4 Chip TCPCOF Type

2 Chip COGCOF Type

1 Chip COG Type


HitachiSamsung

奇景聯詠

智寶科技







PWR SRAMGAMA64

APRSRAM

Gate Driver

PWR



18

64

18


Gate control

PowerSupplyCircuit

TimingGenerator

OSCSystem Interface


Indexregister

Controlregister

graylevelgenerator




Gammaadjusting

Addresscounter

VGHVGL

VgoffGVDDVGS

AVDD

18

G17

7G

176

G17

5 G

2G

1G

0

S396

S395

S394

S3 S2 S1

SPIC

ontrol

RW

Data

VDD3VDD

Latch circuitand

Vcom


Voltage Setting


VDD(20V ~ 33V)


VCI(25V ~ 33V)

BT2-0

BT2-0

VRH3-0

VREG2OUT

VCOM4-0

VGH(+9 ~ +165V)

AVDD(+35~ +55V)


VCL

VgoffH (to -50V)


VGL (-165 to -9V)

-1 times-1 times

VREG1OUT

VDV4-0

VCI1

VC2-0

VSS(0V)

VC3=1VRL3-0

GVDD(+30~ +50V)

VC3=0VRL3-0


Voltage Waveforms


sn(source output)

VCOM

Gn (Gate output)

VGH(+9 ~ +165V)


VgoffH (~to -50V)


GVDD(+30~ +50V)VDD(20V ~ 33V)

AVDD(+35~ +55V)

VSS(0V)






OVcomOUT


OVREG2OUT


OVREG1OUT


IOREGP





IOVCI



IOAVDD



-VDD

DescriptionIOSymbol




OVgoffL


OVgoffH



voltage

OVgoffOUT


IVgoff


higher than -150 V

OVGL



OVGH



OVcomL


OVcomH



IVcomR

DescriptionIOSymbol



mA2015-IVCI



by mode


Outputs


Outputs


Outputs





V5-3GVDD

V-5--16VGOFF

V-9--165VGL

V165-9VGH


V55-35AVDD

LCD Supply Voltage







Vcom


Vcom



Vgoff






V595583571VREG1OUT









VCI2

VCI VCI

VDDVSSVCIVSS

C7

int

VGL

VGH

C1VGH

C22P

C16


C11+

C1 5REGP

VCL

C31MVCI3

C22M

C12-C12+

C11-Vci1

VCIOUT

VCOMR

VGOFFOUT

VGOFFL

C20

C19

VCOMOUT

VCOMH

VREG1OUT

VREG2OUT

C 21

C 11


(Vgoffadjustment)


adjustment)

VcomHadjustment

circuit


circuit

GVDDoutput

amplifier

VcomHoutput

amplifier

VcomLoutput

amplifier

VgoffHoutput


amplifier


circuit

C12

C9GVDD

VGOFFH

C10

Voltageadjustment

circuitRegulator

Charge-pump

circuit 1

C23PC23M

C21M

Charge-pump

circuit 2

C21P

C31P Charge-pump

circuit 3

C41-Vci4

C41+ Charge-pump

circuit 4

REGN

C14C17

AVDD

C18

C4

C3

C2

C6

VC1

C5

C3


AVDD

VGL

GVDD

VCOML





GRAMMSB LSB

PKP00PKP01PKP02

PKP10PKP11PKP12

PKP20PKP21PKP22

PKP30PKP31PKP32

PKP40PKP41PKP42

PKP50PKP51PKP52

PRP00PRP01PRP02

PRP10PRP11PRP12

VRP00VRP01VRP02

VRP10VRP11VRP12

VRP03

VRP13VRP14

PKN00PKN01PKN02

PKN10PKN11PKN12

PKN20PKN21PKN22

PKN30PKN31PKN32

PKN40PKN41PKN42

PKN50PKN51PKN52

PRN00PRN01PRN02

PRN10PRN11PRN12

VRN00VRN01VRN02

VRN10VRN11VRN12

VRN03

VRN13VRN14



GrayscaleAm plifier


ltRgt

LCD driver

64 grayscalecontrol

ltG gt

LCD driver

64 grayscalecontrol

ltBgt

LCD driver

64

V1

V0

V63

6 6 6

R G BLCD


Scan Mode

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176


11


01

G176 G175 G174 G173 hellip G4 G3 G2 G110

G1 G2 G3 G4 hellip G173 G174 G175 G17600

Scan ModeGSSM

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176


A

B

C

D

A

B

C

D






33 3 3 3 54333








G V D D

V G S


V I N P N 0

V I N P N 1

V I N P N 2

V I N P N 3

V I N P N 4

V I N P N 5

V I N P N 6

V I N P N 7

V 0

V 6 3

V 6 2

V 5 5

V 4 3

V 2 0

V 8

V 1V 2V 3

V 9

V 2 1

V 4 4

V 5 6V 5 7





Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge





8080Dummy Pad1195239742


Pad sizeum


UnitSize

Pad nameItems









Technology






25532V Process










Gat

e D

river

IC


Gat

e D

river

IC

T-Con

LTPS TFT-LCD


Source Driver IC

Gat

e D

river

IC

De-MUX






Outline









Digital vs Analog




TTL vs LVDS





XGA 325M (2 ports)

67M ( 1 port)

67M (2 ports)

SXGA 54M (2 ports)

54M (2 ports)

108M (2 ports)

Frequency

UXGA - 81M 162M LCD




6-bit ~80 ~60 ~50



RSDS Definition




8 Bit RGB RSDS Data

Start pulseR0 R1

R2 R3

R4 R5

G0 G1

G2 G3G4 G5

B0 B1

B2 B3

B4 B5

Invalid data

Invalid data

Invalid data

R6 R7

G6 G7

B6 B7



Single-end

FrontBack








Mini-LVDS

Data Bus Structure


Mini-LVDS

6 bit data 5 pairs


8 bit data 6 pairs

Mini-LVDS






TQFP100


RSDS vs Mini-LVDS













PPDSRSDSParameter



PPDSTM








PPDS Protocol





10-bit(1024灰階)


Memo






VsCRsCgRV

sCRRV

sCRsCRgsV

CII

CmII

CII

II

CII

CIImout 1

)1(1

1

)1()( 66

+minusminus

=⎟⎟⎠

⎞⎜⎜⎝

⎛+

+⎟⎟⎠

⎞⎜⎜⎝

⎛+

minus=

Vrsquorsquo

Vout

VDD

CC

Vrsquo

++

--

M6

RII



IC1 IC2


VocOutput offset

between chip tochip




of gray m


Offset Cancellation

Voffset

VinVo=Vin+Voffset


Phase 1

Phase 2

Caz



Caz

Vo=Vin


+-

+ -

- +

- +

- +-+



Channel 384

Channel 383

Channel 382

Channel 381

Channel 4

Channel 3

Channel 2

Channel 1

Length

Height


Channel 420

Channel 419

Channel 418

Channel 417

Channel 4

Channel 3

Channel 2

Channel 1


Channel 480

Channel 479

Channel 478

Channel 477

Channel 4

Channel 3

Channel 2

Channel 1


resistor

Gammaresistor

Gammaresistor



TSMC HV Process




LCD Panel

Start pulse










dtdVCI times=

P = fdCloadVDD2

Turn on one clock




ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

clock

clock

Clock 2Clock 1

Clock 2Clock 1



Dual edge clocking

1 2 3 4

CK1XCK1CK2XCK2


Charge Sharing

To data line

DAC P


OddOutput

EvenOutput

OP

OPDAC NData

Data

Vgmama+

Vgmama-

-+

-+









CNS for Car

4~8mA

DSC Game PDA

2~3mA

05 ~ 2 mA

Mobile-phone


Large size panel









TV application


Outline









LCD TV Electronics

LCD Control Board


SDTV 720x480

cable


DCDC power




LCD Module

TTLLVDSTMDS

γ


OSD

Scaler

MCU

ADCAnalog

RGB

VideoDecoder

DigitalDVI

TMDSRx

De-interlace

Tuner

YC

SyncSep

Compositevideo

AntennaRF in

YCbCr

YPbPr



Digital TV System


MPEG2Decoder PODCI

32MB DDRSDRAM

Scaler IC







RESETRESET


SWITCHSWITCH



DiodesDiodes

LCDLCDDRIVERDRIVER


MICONMICON



INVERTERINVERTER


LCDLCDPANELPANEL

POWERAMPPOWERAMP




LA7585LA7585LA758788LA758788

LA7565LA7565


LA426061LA426061LA426570LA426570LA428082LA428082


LA7221LA7221









LA76818LA76818LA863228LA863228

FSS140132134FSS140132134CPH33043414CPH33043414


CPH5506CPH5506

LA426642674268LA426642674268LA427642774278LA427642774278








Black Insertion





DAC

γminus18R1 string

γminus22R2 string

γminus26R3 string

switch


Vref [118] Vout

8-bit Data


V0~V255




example



Over-8 bit data







Gn-1

Gn

Gray Level



Actual Response

Gn-1

Gn

Gray Level


Gn

Overdrive Response

Voltage by Driver







Overdrive Circuits

Memory

Lookup Table

Control ckts

Data

Dn

Dn+1

Ctrl

addressReadWrite

Datarsquo




ight

ness

Normal image

brig

htne

ss

bright imagebr

ight

ness


Other Technologies






LCD TV Trends


Size

BrightnessCR

Response Time

LCD Monitor

15-20rdquo

250400

25~16ms


Resolution XGA~UXGA

2002~2003

LCD TV


400~550500~700 gt550gt2k

25~16ms 16~12ms lt 8 ms

160160 176176


2004~2008

challenge

COST


Outline








TFTTFT



Controller025 μm

Sourcedriver05 μm


Gatedriver

06 μm HV



HV

Single chipHV

4 Chip TCPCOF Type

2 Chip COGCOF Type

1 Chip COG Type


HitachiSamsung

奇景聯詠

智寶科技







PWR SRAMGAMA64

APRSRAM

Gate Driver

PWR



18

64

18


Gate control

PowerSupplyCircuit

TimingGenerator

OSCSystem Interface


Indexregister

Controlregister

graylevelgenerator




Gammaadjusting

Addresscounter

VGHVGL

VgoffGVDDVGS

AVDD

18

G17

7G

176

G17

5 G

2G

1G

0

S396

S395

S394

S3 S2 S1

SPIC

ontrol

RW

Data

VDD3VDD

Latch circuitand

Vcom


Voltage Setting


VDD(20V ~ 33V)


VCI(25V ~ 33V)

BT2-0

BT2-0

VRH3-0

VREG2OUT

VCOM4-0

VGH(+9 ~ +165V)

AVDD(+35~ +55V)


VCL

VgoffH (to -50V)


VGL (-165 to -9V)

-1 times-1 times

VREG1OUT

VDV4-0

VCI1

VC2-0

VSS(0V)

VC3=1VRL3-0

GVDD(+30~ +50V)

VC3=0VRL3-0


Voltage Waveforms


sn(source output)

VCOM

Gn (Gate output)

VGH(+9 ~ +165V)


VgoffH (~to -50V)


GVDD(+30~ +50V)VDD(20V ~ 33V)

AVDD(+35~ +55V)

VSS(0V)






OVcomOUT


OVREG2OUT


OVREG1OUT


IOREGP





IOVCI



IOAVDD



-VDD

DescriptionIOSymbol




OVgoffL


OVgoffH



voltage

OVgoffOUT


IVgoff


higher than -150 V

OVGL



OVGH



OVcomL


OVcomH



IVcomR

DescriptionIOSymbol



mA2015-IVCI



by mode


Outputs


Outputs


Outputs





V5-3GVDD

V-5--16VGOFF

V-9--165VGL

V165-9VGH


V55-35AVDD

LCD Supply Voltage







Vcom


Vcom



Vgoff






V595583571VREG1OUT









VCI2

VCI VCI

VDDVSSVCIVSS

C7

int

VGL

VGH

C1VGH

C22P

C16


C11+

C1 5REGP

VCL

C31MVCI3

C22M

C12-C12+

C11-Vci1

VCIOUT

VCOMR

VGOFFOUT

VGOFFL

C20

C19

VCOMOUT

VCOMH

VREG1OUT

VREG2OUT

C 21

C 11


(Vgoffadjustment)


adjustment)

VcomHadjustment

circuit


circuit

GVDDoutput

amplifier

VcomHoutput

amplifier

VcomLoutput

amplifier

VgoffHoutput


amplifier


circuit

C12

C9GVDD

VGOFFH

C10

Voltageadjustment

circuitRegulator

Charge-pump

circuit 1

C23PC23M

C21M

Charge-pump

circuit 2

C21P

C31P Charge-pump

circuit 3

C41-Vci4

C41+ Charge-pump

circuit 4

REGN

C14C17

AVDD

C18

C4

C3

C2

C6

VC1

C5

C3


AVDD

VGL

GVDD

VCOML





GRAMMSB LSB

PKP00PKP01PKP02

PKP10PKP11PKP12

PKP20PKP21PKP22

PKP30PKP31PKP32

PKP40PKP41PKP42

PKP50PKP51PKP52

PRP00PRP01PRP02

PRP10PRP11PRP12

VRP00VRP01VRP02

VRP10VRP11VRP12

VRP03

VRP13VRP14

PKN00PKN01PKN02

PKN10PKN11PKN12

PKN20PKN21PKN22

PKN30PKN31PKN32

PKN40PKN41PKN42

PKN50PKN51PKN52

PRN00PRN01PRN02

PRN10PRN11PRN12

VRN00VRN01VRN02

VRN10VRN11VRN12

VRN03

VRN13VRN14



GrayscaleAm plifier


ltRgt

LCD driver

64 grayscalecontrol

ltG gt

LCD driver

64 grayscalecontrol

ltBgt

LCD driver

64

V1

V0

V63

6 6 6

R G BLCD


Scan Mode

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176


11


01

G176 G175 G174 G173 hellip G4 G3 G2 G110

G1 G2 G3 G4 hellip G173 G174 G175 G17600

Scan ModeGSSM

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176


A

B

C

D

A

B

C

D






33 3 3 3 54333








G V D D

V G S


V I N P N 0

V I N P N 1

V I N P N 2

V I N P N 3

V I N P N 4

V I N P N 5

V I N P N 6

V I N P N 7

V 0

V 6 3

V 6 2

V 5 5

V 4 3

V 2 0

V 8

V 1V 2V 3

V 9

V 2 1

V 4 4

V 5 6V 5 7





Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge





8080Dummy Pad1195239742


Pad sizeum


UnitSize

Pad nameItems









Technology






25532V Process










Gat

e D

river

IC


Gat

e D

river

IC

T-Con

LTPS TFT-LCD


Source Driver IC

Gat

e D

river

IC

De-MUX






Outline









Digital vs Analog




TTL vs LVDS





XGA 325M (2 ports)

67M ( 1 port)

67M (2 ports)

SXGA 54M (2 ports)

54M (2 ports)

108M (2 ports)

Frequency

UXGA - 81M 162M LCD




6-bit ~80 ~60 ~50



RSDS Definition




8 Bit RGB RSDS Data

Start pulseR0 R1

R2 R3

R4 R5

G0 G1

G2 G3G4 G5

B0 B1

B2 B3

B4 B5

Invalid data

Invalid data

Invalid data

R6 R7

G6 G7

B6 B7



Single-end

FrontBack








Mini-LVDS

Data Bus Structure


Mini-LVDS

6 bit data 5 pairs


8 bit data 6 pairs

Mini-LVDS






TQFP100


RSDS vs Mini-LVDS













PPDSRSDSParameter



PPDSTM








PPDS Protocol





10-bit(1024灰階)


Memo


TSMC HV Process




LCD Panel

Start pulse










dtdVCI times=

P = fdCloadVDD2

Turn on one clock




ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

ShiftRegister

clock

clock

Clock 2Clock 1

Clock 2Clock 1



Dual edge clocking

1 2 3 4

CK1XCK1CK2XCK2


Charge Sharing

To data line

DAC P


OddOutput

EvenOutput

OP

OPDAC NData

Data

Vgmama+

Vgmama-

-+

-+









CNS for Car

4~8mA

DSC Game PDA

2~3mA

05 ~ 2 mA

Mobile-phone


Large size panel









TV application


Outline









LCD TV Electronics

LCD Control Board


SDTV 720x480

cable


DCDC power




LCD Module

TTLLVDSTMDS

γ


OSD

Scaler

MCU

ADCAnalog

RGB

VideoDecoder

DigitalDVI

TMDSRx

De-interlace

Tuner

YC

SyncSep

Compositevideo

AntennaRF in

YCbCr

YPbPr



Digital TV System


MPEG2Decoder PODCI

32MB DDRSDRAM

Scaler IC







RESETRESET


SWITCHSWITCH



DiodesDiodes

LCDLCDDRIVERDRIVER


MICONMICON



INVERTERINVERTER


LCDLCDPANELPANEL

POWERAMPPOWERAMP




LA7585LA7585LA758788LA758788

LA7565LA7565


LA426061LA426061LA426570LA426570LA428082LA428082


LA7221LA7221









LA76818LA76818LA863228LA863228

FSS140132134FSS140132134CPH33043414CPH33043414


CPH5506CPH5506

LA426642674268LA426642674268LA427642774278LA427642774278








Black Insertion





DAC

γminus18R1 string

γminus22R2 string

γminus26R3 string

switch


Vref [118] Vout

8-bit Data


V0~V255




example



Over-8 bit data







Gn-1

Gn

Gray Level



Actual Response

Gn-1

Gn

Gray Level


Gn

Overdrive Response

Voltage by Driver







Overdrive Circuits

Memory

Lookup Table

Control ckts

Data

Dn

Dn+1

Ctrl

addressReadWrite

Datarsquo




ight

ness

Normal image

brig

htne

ss

bright imagebr

ight

ness


Other Technologies






LCD TV Trends


Size

BrightnessCR

Response Time

LCD Monitor

15-20rdquo

250400

25~16ms


Resolution XGA~UXGA

2002~2003

LCD TV


400~550500~700 gt550gt2k

25~16ms 16~12ms lt 8 ms

160160 176176


2004~2008

challenge

COST


Outline








TFTTFT



Controller025 μm

Sourcedriver05 μm


Gatedriver

06 μm HV



HV

Single chipHV

4 Chip TCPCOF Type

2 Chip COGCOF Type

1 Chip COG Type


HitachiSamsung

奇景聯詠

智寶科技







PWR SRAMGAMA64

APRSRAM

Gate Driver

PWR



18

64

18


Gate control

PowerSupplyCircuit

TimingGenerator

OSCSystem Interface


Indexregister

Controlregister

graylevelgenerator




Gammaadjusting

Addresscounter

VGHVGL

VgoffGVDDVGS

AVDD

18

G17

7G

176

G17

5 G

2G

1G

0

S396

S395

S394

S3 S2 S1

SPIC

ontrol

RW

Data

VDD3VDD

Latch circuitand

Vcom


Voltage Setting


VDD(20V ~ 33V)


VCI(25V ~ 33V)

BT2-0

BT2-0

VRH3-0

VREG2OUT

VCOM4-0

VGH(+9 ~ +165V)

AVDD(+35~ +55V)


VCL

VgoffH (to -50V)


VGL (-165 to -9V)

-1 times-1 times

VREG1OUT

VDV4-0

VCI1

VC2-0

VSS(0V)

VC3=1VRL3-0

GVDD(+30~ +50V)

VC3=0VRL3-0


Voltage Waveforms


sn(source output)

VCOM

Gn (Gate output)

VGH(+9 ~ +165V)


VgoffH (~to -50V)


GVDD(+30~ +50V)VDD(20V ~ 33V)

AVDD(+35~ +55V)

VSS(0V)






OVcomOUT


OVREG2OUT


OVREG1OUT


IOREGP





IOVCI



IOAVDD



-VDD

DescriptionIOSymbol




OVgoffL


OVgoffH



voltage

OVgoffOUT


IVgoff


higher than -150 V

OVGL



OVGH



OVcomL


OVcomH



IVcomR

DescriptionIOSymbol



mA2015-IVCI



by mode


Outputs


Outputs


Outputs





V5-3GVDD

V-5--16VGOFF

V-9--165VGL

V165-9VGH


V55-35AVDD

LCD Supply Voltage







Vcom


Vcom



Vgoff






V595583571VREG1OUT









VCI2

VCI VCI

VDDVSSVCIVSS

C7

int

VGL

VGH

C1VGH

C22P

C16


C11+

C1 5REGP

VCL

C31MVCI3

C22M

C12-C12+

C11-Vci1

VCIOUT

VCOMR

VGOFFOUT

VGOFFL

C20

C19

VCOMOUT

VCOMH

VREG1OUT

VREG2OUT

C 21

C 11


(Vgoffadjustment)


adjustment)

VcomHadjustment

circuit


circuit

GVDDoutput

amplifier

VcomHoutput

amplifier

VcomLoutput

amplifier

VgoffHoutput


amplifier


circuit

C12

C9GVDD

VGOFFH

C10

Voltageadjustment

circuitRegulator

Charge-pump

circuit 1

C23PC23M

C21M

Charge-pump

circuit 2

C21P

C31P Charge-pump

circuit 3

C41-Vci4

C41+ Charge-pump

circuit 4

REGN

C14C17

AVDD

C18

C4

C3

C2

C6

VC1

C5

C3


AVDD

VGL

GVDD

VCOML





GRAMMSB LSB

PKP00PKP01PKP02

PKP10PKP11PKP12

PKP20PKP21PKP22

PKP30PKP31PKP32

PKP40PKP41PKP42

PKP50PKP51PKP52

PRP00PRP01PRP02

PRP10PRP11PRP12

VRP00VRP01VRP02

VRP10VRP11VRP12

VRP03

VRP13VRP14

PKN00PKN01PKN02

PKN10PKN11PKN12

PKN20PKN21PKN22

PKN30PKN31PKN32

PKN40PKN41PKN42

PKN50PKN51PKN52

PRN00PRN01PRN02

PRN10PRN11PRN12

VRN00VRN01VRN02

VRN10VRN11VRN12

VRN03

VRN13VRN14



GrayscaleAm plifier


ltRgt

LCD driver

64 grayscalecontrol

ltG gt

LCD driver

64 grayscalecontrol

ltBgt

LCD driver

64

V1

V0

V63

6 6 6

R G BLCD


Scan Mode

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176


11


01

G176 G175 G174 G173 hellip G4 G3 G2 G110

G1 G2 G3 G4 hellip G173 G174 G175 G17600

Scan ModeGSSM

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176


A

B

C

D

A

B

C

D






33 3 3 3 54333








G V D D

V G S


V I N P N 0

V I N P N 1

V I N P N 2

V I N P N 3

V I N P N 4

V I N P N 5

V I N P N 6

V I N P N 7

V 0

V 6 3

V 6 2

V 5 5

V 4 3

V 2 0

V 8

V 1V 2V 3

V 9

V 2 1

V 4 4

V 5 6V 5 7





Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge





8080Dummy Pad1195239742


Pad sizeum


UnitSize

Pad nameItems









Technology






25532V Process










Gat

e D

river

IC


Gat

e D

river

IC

T-Con

LTPS TFT-LCD


Source Driver IC

Gat

e D

river

IC

De-MUX






Outline









Digital vs Analog




TTL vs LVDS





XGA 325M (2 ports)

67M ( 1 port)

67M (2 ports)

SXGA 54M (2 ports)

54M (2 ports)

108M (2 ports)

Frequency

UXGA - 81M 162M LCD




6-bit ~80 ~60 ~50



RSDS Definition




8 Bit RGB RSDS Data

Start pulseR0 R1

R2 R3

R4 R5

G0 G1

G2 G3G4 G5

B0 B1

B2 B3

B4 B5

Invalid data

Invalid data

Invalid data

R6 R7

G6 G7

B6 B7



Single-end

FrontBack








Mini-LVDS

Data Bus Structure


Mini-LVDS

6 bit data 5 pairs


8 bit data 6 pairs

Mini-LVDS






TQFP100


RSDS vs Mini-LVDS













PPDSRSDSParameter



PPDSTM








PPDS Protocol





10-bit(1024灰階)


Memo


Charge Sharing

To data line

DAC P


OddOutput

EvenOutput

OP

OPDAC NData

Data

Vgmama+

Vgmama-

-+

-+









CNS for Car

4~8mA

DSC Game PDA

2~3mA

05 ~ 2 mA

Mobile-phone


Large size panel









TV application


Outline









LCD TV Electronics

LCD Control Board


SDTV 720x480

cable


DCDC power




LCD Module

TTLLVDSTMDS

γ


OSD

Scaler

MCU

ADCAnalog

RGB

VideoDecoder

DigitalDVI

TMDSRx

De-interlace

Tuner

YC

SyncSep

Compositevideo

AntennaRF in

YCbCr

YPbPr



Digital TV System


MPEG2Decoder PODCI

32MB DDRSDRAM

Scaler IC







RESETRESET


SWITCHSWITCH



DiodesDiodes

LCDLCDDRIVERDRIVER


MICONMICON



INVERTERINVERTER


LCDLCDPANELPANEL

POWERAMPPOWERAMP




LA7585LA7585LA758788LA758788

LA7565LA7565


LA426061LA426061LA426570LA426570LA428082LA428082


LA7221LA7221









LA76818LA76818LA863228LA863228

FSS140132134FSS140132134CPH33043414CPH33043414


CPH5506CPH5506

LA426642674268LA426642674268LA427642774278LA427642774278








Black Insertion





DAC

γminus18R1 string

γminus22R2 string

γminus26R3 string

switch


Vref [118] Vout

8-bit Data


V0~V255




example



Over-8 bit data







Gn-1

Gn

Gray Level



Actual Response

Gn-1

Gn

Gray Level


Gn

Overdrive Response

Voltage by Driver







Overdrive Circuits

Memory

Lookup Table

Control ckts

Data

Dn

Dn+1

Ctrl

addressReadWrite

Datarsquo




ight

ness

Normal image

brig

htne

ss

bright imagebr

ight

ness


Other Technologies






LCD TV Trends


Size

BrightnessCR

Response Time

LCD Monitor

15-20rdquo

250400

25~16ms


Resolution XGA~UXGA

2002~2003

LCD TV


400~550500~700 gt550gt2k

25~16ms 16~12ms lt 8 ms

160160 176176


2004~2008

challenge

COST


Outline








TFTTFT



Controller025 μm

Sourcedriver05 μm


Gatedriver

06 μm HV



HV

Single chipHV

4 Chip TCPCOF Type

2 Chip COGCOF Type

1 Chip COG Type


HitachiSamsung

奇景聯詠

智寶科技







PWR SRAMGAMA64

APRSRAM

Gate Driver

PWR



18

64

18


Gate control

PowerSupplyCircuit

TimingGenerator

OSCSystem Interface


Indexregister

Controlregister

graylevelgenerator




Gammaadjusting

Addresscounter

VGHVGL

VgoffGVDDVGS

AVDD

18

G17

7G

176

G17

5 G

2G

1G

0

S396

S395

S394

S3 S2 S1

SPIC

ontrol

RW

Data

VDD3VDD

Latch circuitand

Vcom


Voltage Setting


VDD(20V ~ 33V)


VCI(25V ~ 33V)

BT2-0

BT2-0

VRH3-0

VREG2OUT

VCOM4-0

VGH(+9 ~ +165V)

AVDD(+35~ +55V)


VCL

VgoffH (to -50V)


VGL (-165 to -9V)

-1 times-1 times

VREG1OUT

VDV4-0

VCI1

VC2-0

VSS(0V)

VC3=1VRL3-0

GVDD(+30~ +50V)

VC3=0VRL3-0


Voltage Waveforms


sn(source output)

VCOM

Gn (Gate output)

VGH(+9 ~ +165V)


VgoffH (~to -50V)


GVDD(+30~ +50V)VDD(20V ~ 33V)

AVDD(+35~ +55V)

VSS(0V)






OVcomOUT


OVREG2OUT


OVREG1OUT


IOREGP





IOVCI



IOAVDD



-VDD

DescriptionIOSymbol




OVgoffL


OVgoffH



voltage

OVgoffOUT


IVgoff


higher than -150 V

OVGL



OVGH



OVcomL


OVcomH



IVcomR

DescriptionIOSymbol



mA2015-IVCI



by mode


Outputs


Outputs


Outputs





V5-3GVDD

V-5--16VGOFF

V-9--165VGL

V165-9VGH


V55-35AVDD

LCD Supply Voltage







Vcom


Vcom



Vgoff






V595583571VREG1OUT









VCI2

VCI VCI

VDDVSSVCIVSS

C7

int

VGL

VGH

C1VGH

C22P

C16


C11+

C1 5REGP

VCL

C31MVCI3

C22M

C12-C12+

C11-Vci1

VCIOUT

VCOMR

VGOFFOUT

VGOFFL

C20

C19

VCOMOUT

VCOMH

VREG1OUT

VREG2OUT

C 21

C 11


(Vgoffadjustment)


adjustment)

VcomHadjustment

circuit


circuit

GVDDoutput

amplifier

VcomHoutput

amplifier

VcomLoutput

amplifier

VgoffHoutput


amplifier


circuit

C12

C9GVDD

VGOFFH

C10

Voltageadjustment

circuitRegulator

Charge-pump

circuit 1

C23PC23M

C21M

Charge-pump

circuit 2

C21P

C31P Charge-pump

circuit 3

C41-Vci4

C41+ Charge-pump

circuit 4

REGN

C14C17

AVDD

C18

C4

C3

C2

C6

VC1

C5

C3


AVDD

VGL

GVDD

VCOML





GRAMMSB LSB

PKP00PKP01PKP02

PKP10PKP11PKP12

PKP20PKP21PKP22

PKP30PKP31PKP32

PKP40PKP41PKP42

PKP50PKP51PKP52

PRP00PRP01PRP02

PRP10PRP11PRP12

VRP00VRP01VRP02

VRP10VRP11VRP12

VRP03

VRP13VRP14

PKN00PKN01PKN02

PKN10PKN11PKN12

PKN20PKN21PKN22

PKN30PKN31PKN32

PKN40PKN41PKN42

PKN50PKN51PKN52

PRN00PRN01PRN02

PRN10PRN11PRN12

VRN00VRN01VRN02

VRN10VRN11VRN12

VRN03

VRN13VRN14



GrayscaleAm plifier


ltRgt

LCD driver

64 grayscalecontrol

ltG gt

LCD driver

64 grayscalecontrol

ltBgt

LCD driver

64

V1

V0

V63

6 6 6

R G BLCD


Scan Mode

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176


11


01

G176 G175 G174 G173 hellip G4 G3 G2 G110

G1 G2 G3 G4 hellip G173 G174 G175 G17600

Scan ModeGSSM

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176


A

B

C

D

A

B

C

D






33 3 3 3 54333








G V D D

V G S


V I N P N 0

V I N P N 1

V I N P N 2

V I N P N 3

V I N P N 4

V I N P N 5

V I N P N 6

V I N P N 7

V 0

V 6 3

V 6 2

V 5 5

V 4 3

V 2 0

V 8

V 1V 2V 3

V 9

V 2 1

V 4 4

V 5 6V 5 7





Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge





8080Dummy Pad1195239742


Pad sizeum


UnitSize

Pad nameItems









Technology






25532V Process










Gat

e D

river

IC


Gat

e D

river

IC

T-Con

LTPS TFT-LCD


Source Driver IC

Gat

e D

river

IC

De-MUX






Outline









Digital vs Analog




TTL vs LVDS





XGA 325M (2 ports)

67M ( 1 port)

67M (2 ports)

SXGA 54M (2 ports)

54M (2 ports)

108M (2 ports)

Frequency

UXGA - 81M 162M LCD




6-bit ~80 ~60 ~50



RSDS Definition




8 Bit RGB RSDS Data

Start pulseR0 R1

R2 R3

R4 R5

G0 G1

G2 G3G4 G5

B0 B1

B2 B3

B4 B5

Invalid data

Invalid data

Invalid data

R6 R7

G6 G7

B6 B7



Single-end

FrontBack








Mini-LVDS

Data Bus Structure


Mini-LVDS

6 bit data 5 pairs


8 bit data 6 pairs

Mini-LVDS






TQFP100


RSDS vs Mini-LVDS













PPDSRSDSParameter



PPDSTM








PPDS Protocol





10-bit(1024灰階)


Memo









TV application


Outline









LCD TV Electronics

LCD Control Board


SDTV 720x480

cable


DCDC power




LCD Module

TTLLVDSTMDS

γ


OSD

Scaler

MCU

ADCAnalog

RGB

VideoDecoder

DigitalDVI

TMDSRx

De-interlace

Tuner

YC

SyncSep

Compositevideo

AntennaRF in

YCbCr

YPbPr



Digital TV System


MPEG2Decoder PODCI

32MB DDRSDRAM

Scaler IC







RESETRESET


SWITCHSWITCH



DiodesDiodes

LCDLCDDRIVERDRIVER


MICONMICON



INVERTERINVERTER


LCDLCDPANELPANEL

POWERAMPPOWERAMP




LA7585LA7585LA758788LA758788

LA7565LA7565


LA426061LA426061LA426570LA426570LA428082LA428082


LA7221LA7221









LA76818LA76818LA863228LA863228

FSS140132134FSS140132134CPH33043414CPH33043414


CPH5506CPH5506

LA426642674268LA426642674268LA427642774278LA427642774278








Black Insertion





DAC

γminus18R1 string

γminus22R2 string

γminus26R3 string

switch


Vref [118] Vout

8-bit Data


V0~V255




example



Over-8 bit data







Gn-1

Gn

Gray Level



Actual Response

Gn-1

Gn

Gray Level


Gn

Overdrive Response

Voltage by Driver







Overdrive Circuits

Memory

Lookup Table

Control ckts

Data

Dn

Dn+1

Ctrl

addressReadWrite

Datarsquo




ight

ness

Normal image

brig

htne

ss

bright imagebr

ight

ness


Other Technologies






LCD TV Trends


Size

BrightnessCR

Response Time

LCD Monitor

15-20rdquo

250400

25~16ms


Resolution XGA~UXGA

2002~2003

LCD TV


400~550500~700 gt550gt2k

25~16ms 16~12ms lt 8 ms

160160 176176


2004~2008

challenge

COST


Outline








TFTTFT



Controller025 μm

Sourcedriver05 μm


Gatedriver

06 μm HV



HV

Single chipHV

4 Chip TCPCOF Type

2 Chip COGCOF Type

1 Chip COG Type


HitachiSamsung

奇景聯詠

智寶科技







PWR SRAMGAMA64

APRSRAM

Gate Driver

PWR



18

64

18


Gate control

PowerSupplyCircuit

TimingGenerator

OSCSystem Interface


Indexregister

Controlregister

graylevelgenerator




Gammaadjusting

Addresscounter

VGHVGL

VgoffGVDDVGS

AVDD

18

G17

7G

176

G17

5 G

2G

1G

0

S396

S395

S394

S3 S2 S1

SPIC

ontrol

RW

Data

VDD3VDD

Latch circuitand

Vcom


Voltage Setting


VDD(20V ~ 33V)


VCI(25V ~ 33V)

BT2-0

BT2-0

VRH3-0

VREG2OUT

VCOM4-0

VGH(+9 ~ +165V)

AVDD(+35~ +55V)


VCL

VgoffH (to -50V)


VGL (-165 to -9V)

-1 times-1 times

VREG1OUT

VDV4-0

VCI1

VC2-0

VSS(0V)

VC3=1VRL3-0

GVDD(+30~ +50V)

VC3=0VRL3-0


Voltage Waveforms


sn(source output)

VCOM

Gn (Gate output)

VGH(+9 ~ +165V)


VgoffH (~to -50V)


GVDD(+30~ +50V)VDD(20V ~ 33V)

AVDD(+35~ +55V)

VSS(0V)






OVcomOUT


OVREG2OUT


OVREG1OUT


IOREGP





IOVCI



IOAVDD



-VDD

DescriptionIOSymbol




OVgoffL


OVgoffH



voltage

OVgoffOUT


IVgoff


higher than -150 V

OVGL



OVGH



OVcomL


OVcomH



IVcomR

DescriptionIOSymbol



mA2015-IVCI



by mode


Outputs


Outputs


Outputs





V5-3GVDD

V-5--16VGOFF

V-9--165VGL

V165-9VGH


V55-35AVDD

LCD Supply Voltage







Vcom


Vcom



Vgoff






V595583571VREG1OUT









VCI2

VCI VCI

VDDVSSVCIVSS

C7

int

VGL

VGH

C1VGH

C22P

C16


C11+

C1 5REGP

VCL

C31MVCI3

C22M

C12-C12+

C11-Vci1

VCIOUT

VCOMR

VGOFFOUT

VGOFFL

C20

C19

VCOMOUT

VCOMH

VREG1OUT

VREG2OUT

C 21

C 11


(Vgoffadjustment)


adjustment)

VcomHadjustment

circuit


circuit

GVDDoutput

amplifier

VcomHoutput

amplifier

VcomLoutput

amplifier

VgoffHoutput


amplifier


circuit

C12

C9GVDD

VGOFFH

C10

Voltageadjustment

circuitRegulator

Charge-pump

circuit 1

C23PC23M

C21M

Charge-pump

circuit 2

C21P

C31P Charge-pump

circuit 3

C41-Vci4

C41+ Charge-pump

circuit 4

REGN

C14C17

AVDD

C18

C4

C3

C2

C6

VC1

C5

C3


AVDD

VGL

GVDD

VCOML





GRAMMSB LSB

PKP00PKP01PKP02

PKP10PKP11PKP12

PKP20PKP21PKP22

PKP30PKP31PKP32

PKP40PKP41PKP42

PKP50PKP51PKP52

PRP00PRP01PRP02

PRP10PRP11PRP12

VRP00VRP01VRP02

VRP10VRP11VRP12

VRP03

VRP13VRP14

PKN00PKN01PKN02

PKN10PKN11PKN12

PKN20PKN21PKN22

PKN30PKN31PKN32

PKN40PKN41PKN42

PKN50PKN51PKN52

PRN00PRN01PRN02

PRN10PRN11PRN12

VRN00VRN01VRN02

VRN10VRN11VRN12

VRN03

VRN13VRN14



GrayscaleAm plifier


ltRgt

LCD driver

64 grayscalecontrol

ltG gt

LCD driver

64 grayscalecontrol

ltBgt

LCD driver

64

V1

V0

V63

6 6 6

R G BLCD


Scan Mode

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176


11


01

G176 G175 G174 G173 hellip G4 G3 G2 G110

G1 G2 G3 G4 hellip G173 G174 G175 G17600

Scan ModeGSSM

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176


A

B

C

D

A

B

C

D






33 3 3 3 54333








G V D D

V G S


V I N P N 0

V I N P N 1

V I N P N 2

V I N P N 3

V I N P N 4

V I N P N 5

V I N P N 6

V I N P N 7

V 0

V 6 3

V 6 2

V 5 5

V 4 3

V 2 0

V 8

V 1V 2V 3

V 9

V 2 1

V 4 4

V 5 6V 5 7





Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge





8080Dummy Pad1195239742


Pad sizeum


UnitSize

Pad nameItems









Technology






25532V Process










Gat

e D

river

IC


Gat

e D

river

IC

T-Con

LTPS TFT-LCD


Source Driver IC

Gat

e D

river

IC

De-MUX






Outline









Digital vs Analog




TTL vs LVDS





XGA 325M (2 ports)

67M ( 1 port)

67M (2 ports)

SXGA 54M (2 ports)

54M (2 ports)

108M (2 ports)

Frequency

UXGA - 81M 162M LCD




6-bit ~80 ~60 ~50



RSDS Definition




8 Bit RGB RSDS Data

Start pulseR0 R1

R2 R3

R4 R5

G0 G1

G2 G3G4 G5

B0 B1

B2 B3

B4 B5

Invalid data

Invalid data

Invalid data

R6 R7

G6 G7

B6 B7



Single-end

FrontBack








Mini-LVDS

Data Bus Structure


Mini-LVDS

6 bit data 5 pairs


8 bit data 6 pairs

Mini-LVDS






TQFP100


RSDS vs Mini-LVDS













PPDSRSDSParameter



PPDSTM








PPDS Protocol





10-bit(1024灰階)


Memo


Digital TV System


MPEG2Decoder PODCI

32MB DDRSDRAM

Scaler IC







RESETRESET


SWITCHSWITCH



DiodesDiodes

LCDLCDDRIVERDRIVER


MICONMICON



INVERTERINVERTER


LCDLCDPANELPANEL

POWERAMPPOWERAMP




LA7585LA7585LA758788LA758788

LA7565LA7565


LA426061LA426061LA426570LA426570LA428082LA428082


LA7221LA7221









LA76818LA76818LA863228LA863228

FSS140132134FSS140132134CPH33043414CPH33043414


CPH5506CPH5506

LA426642674268LA426642674268LA427642774278LA427642774278








Black Insertion





DAC

γminus18R1 string

γminus22R2 string

γminus26R3 string

switch


Vref [118] Vout

8-bit Data


V0~V255




example



Over-8 bit data







Gn-1

Gn

Gray Level



Actual Response

Gn-1

Gn

Gray Level


Gn

Overdrive Response

Voltage by Driver







Overdrive Circuits

Memory

Lookup Table

Control ckts

Data

Dn

Dn+1

Ctrl

addressReadWrite

Datarsquo




ight

ness

Normal image

brig

htne

ss

bright imagebr

ight

ness


Other Technologies






LCD TV Trends


Size

BrightnessCR

Response Time

LCD Monitor

15-20rdquo

250400

25~16ms


Resolution XGA~UXGA

2002~2003

LCD TV


400~550500~700 gt550gt2k

25~16ms 16~12ms lt 8 ms

160160 176176


2004~2008

challenge

COST


Outline








TFTTFT



Controller025 μm

Sourcedriver05 μm


Gatedriver

06 μm HV



HV

Single chipHV

4 Chip TCPCOF Type

2 Chip COGCOF Type

1 Chip COG Type


HitachiSamsung

奇景聯詠

智寶科技







PWR SRAMGAMA64

APRSRAM

Gate Driver

PWR



18

64

18


Gate control

PowerSupplyCircuit

TimingGenerator

OSCSystem Interface


Indexregister

Controlregister

graylevelgenerator




Gammaadjusting

Addresscounter

VGHVGL

VgoffGVDDVGS

AVDD

18

G17

7G

176

G17

5 G

2G

1G

0

S396

S395

S394

S3 S2 S1

SPIC

ontrol

RW

Data

VDD3VDD

Latch circuitand

Vcom


Voltage Setting


VDD(20V ~ 33V)


VCI(25V ~ 33V)

BT2-0

BT2-0

VRH3-0

VREG2OUT

VCOM4-0

VGH(+9 ~ +165V)

AVDD(+35~ +55V)


VCL

VgoffH (to -50V)


VGL (-165 to -9V)

-1 times-1 times

VREG1OUT

VDV4-0

VCI1

VC2-0

VSS(0V)

VC3=1VRL3-0

GVDD(+30~ +50V)

VC3=0VRL3-0


Voltage Waveforms


sn(source output)

VCOM

Gn (Gate output)

VGH(+9 ~ +165V)


VgoffH (~to -50V)


GVDD(+30~ +50V)VDD(20V ~ 33V)

AVDD(+35~ +55V)

VSS(0V)






OVcomOUT


OVREG2OUT


OVREG1OUT


IOREGP





IOVCI



IOAVDD



-VDD

DescriptionIOSymbol




OVgoffL


OVgoffH



voltage

OVgoffOUT


IVgoff


higher than -150 V

OVGL



OVGH



OVcomL


OVcomH



IVcomR

DescriptionIOSymbol



mA2015-IVCI



by mode


Outputs


Outputs


Outputs





V5-3GVDD

V-5--16VGOFF

V-9--165VGL

V165-9VGH


V55-35AVDD

LCD Supply Voltage







Vcom


Vcom



Vgoff






V595583571VREG1OUT









VCI2

VCI VCI

VDDVSSVCIVSS

C7

int

VGL

VGH

C1VGH

C22P

C16


C11+

C1 5REGP

VCL

C31MVCI3

C22M

C12-C12+

C11-Vci1

VCIOUT

VCOMR

VGOFFOUT

VGOFFL

C20

C19

VCOMOUT

VCOMH

VREG1OUT

VREG2OUT

C 21

C 11


(Vgoffadjustment)


adjustment)

VcomHadjustment

circuit


circuit

GVDDoutput

amplifier

VcomHoutput

amplifier

VcomLoutput

amplifier

VgoffHoutput


amplifier


circuit

C12

C9GVDD

VGOFFH

C10

Voltageadjustment

circuitRegulator

Charge-pump

circuit 1

C23PC23M

C21M

Charge-pump

circuit 2

C21P

C31P Charge-pump

circuit 3

C41-Vci4

C41+ Charge-pump

circuit 4

REGN

C14C17

AVDD

C18

C4

C3

C2

C6

VC1

C5

C3


AVDD

VGL

GVDD

VCOML





GRAMMSB LSB

PKP00PKP01PKP02

PKP10PKP11PKP12

PKP20PKP21PKP22

PKP30PKP31PKP32

PKP40PKP41PKP42

PKP50PKP51PKP52

PRP00PRP01PRP02

PRP10PRP11PRP12

VRP00VRP01VRP02

VRP10VRP11VRP12

VRP03

VRP13VRP14

PKN00PKN01PKN02

PKN10PKN11PKN12

PKN20PKN21PKN22

PKN30PKN31PKN32

PKN40PKN41PKN42

PKN50PKN51PKN52

PRN00PRN01PRN02

PRN10PRN11PRN12

VRN00VRN01VRN02

VRN10VRN11VRN12

VRN03

VRN13VRN14



GrayscaleAm plifier


ltRgt

LCD driver

64 grayscalecontrol

ltG gt

LCD driver

64 grayscalecontrol

ltBgt

LCD driver

64

V1

V0

V63

6 6 6

R G BLCD


Scan Mode

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176


11


01

G176 G175 G174 G173 hellip G4 G3 G2 G110

G1 G2 G3 G4 hellip G173 G174 G175 G17600

Scan ModeGSSM

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176


A

B

C

D

A

B

C

D






33 3 3 3 54333








G V D D

V G S


V I N P N 0

V I N P N 1

V I N P N 2

V I N P N 3

V I N P N 4

V I N P N 5

V I N P N 6

V I N P N 7

V 0

V 6 3

V 6 2

V 5 5

V 4 3

V 2 0

V 8

V 1V 2V 3

V 9

V 2 1

V 4 4

V 5 6V 5 7





Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge





8080Dummy Pad1195239742


Pad sizeum


UnitSize

Pad nameItems









Technology






25532V Process










Gat

e D

river

IC


Gat

e D

river

IC

T-Con

LTPS TFT-LCD


Source Driver IC

Gat

e D

river

IC

De-MUX






Outline









Digital vs Analog




TTL vs LVDS





XGA 325M (2 ports)

67M ( 1 port)

67M (2 ports)

SXGA 54M (2 ports)

54M (2 ports)

108M (2 ports)

Frequency

UXGA - 81M 162M LCD




6-bit ~80 ~60 ~50



RSDS Definition




8 Bit RGB RSDS Data

Start pulseR0 R1

R2 R3

R4 R5

G0 G1

G2 G3G4 G5

B0 B1

B2 B3

B4 B5

Invalid data

Invalid data

Invalid data

R6 R7

G6 G7

B6 B7



Single-end

FrontBack








Mini-LVDS

Data Bus Structure


Mini-LVDS

6 bit data 5 pairs


8 bit data 6 pairs

Mini-LVDS






TQFP100


RSDS vs Mini-LVDS













PPDSRSDSParameter



PPDSTM








PPDS Protocol





10-bit(1024灰階)


Memo





Black Insertion





DAC

γminus18R1 string

γminus22R2 string

γminus26R3 string

switch


Vref [118] Vout

8-bit Data


V0~V255




example



Over-8 bit data







Gn-1

Gn

Gray Level



Actual Response

Gn-1

Gn

Gray Level


Gn

Overdrive Response

Voltage by Driver







Overdrive Circuits

Memory

Lookup Table

Control ckts

Data

Dn

Dn+1

Ctrl

addressReadWrite

Datarsquo




ight

ness

Normal image

brig

htne

ss

bright imagebr

ight

ness


Other Technologies






LCD TV Trends


Size

BrightnessCR

Response Time

LCD Monitor

15-20rdquo

250400

25~16ms


Resolution XGA~UXGA

2002~2003

LCD TV


400~550500~700 gt550gt2k

25~16ms 16~12ms lt 8 ms

160160 176176


2004~2008

challenge

COST


Outline








TFTTFT



Controller025 μm

Sourcedriver05 μm


Gatedriver

06 μm HV



HV

Single chipHV

4 Chip TCPCOF Type

2 Chip COGCOF Type

1 Chip COG Type


HitachiSamsung

奇景聯詠

智寶科技







PWR SRAMGAMA64

APRSRAM

Gate Driver

PWR



18

64

18


Gate control

PowerSupplyCircuit

TimingGenerator

OSCSystem Interface


Indexregister

Controlregister

graylevelgenerator




Gammaadjusting

Addresscounter

VGHVGL

VgoffGVDDVGS

AVDD

18

G17

7G

176

G17

5 G

2G

1G

0

S396

S395

S394

S3 S2 S1

SPIC

ontrol

RW

Data

VDD3VDD

Latch circuitand

Vcom


Voltage Setting


VDD(20V ~ 33V)


VCI(25V ~ 33V)

BT2-0

BT2-0

VRH3-0

VREG2OUT

VCOM4-0

VGH(+9 ~ +165V)

AVDD(+35~ +55V)


VCL

VgoffH (to -50V)


VGL (-165 to -9V)

-1 times-1 times

VREG1OUT

VDV4-0

VCI1

VC2-0

VSS(0V)

VC3=1VRL3-0

GVDD(+30~ +50V)

VC3=0VRL3-0


Voltage Waveforms


sn(source output)

VCOM

Gn (Gate output)

VGH(+9 ~ +165V)


VgoffH (~to -50V)


GVDD(+30~ +50V)VDD(20V ~ 33V)

AVDD(+35~ +55V)

VSS(0V)






OVcomOUT


OVREG2OUT


OVREG1OUT


IOREGP





IOVCI



IOAVDD



-VDD

DescriptionIOSymbol




OVgoffL


OVgoffH



voltage

OVgoffOUT


IVgoff


higher than -150 V

OVGL



OVGH



OVcomL


OVcomH



IVcomR

DescriptionIOSymbol



mA2015-IVCI



by mode


Outputs


Outputs


Outputs





V5-3GVDD

V-5--16VGOFF

V-9--165VGL

V165-9VGH


V55-35AVDD

LCD Supply Voltage







Vcom


Vcom



Vgoff






V595583571VREG1OUT









VCI2

VCI VCI

VDDVSSVCIVSS

C7

int

VGL

VGH

C1VGH

C22P

C16


C11+

C1 5REGP

VCL

C31MVCI3

C22M

C12-C12+

C11-Vci1

VCIOUT

VCOMR

VGOFFOUT

VGOFFL

C20

C19

VCOMOUT

VCOMH

VREG1OUT

VREG2OUT

C 21

C 11


(Vgoffadjustment)


adjustment)

VcomHadjustment

circuit


circuit

GVDDoutput

amplifier

VcomHoutput

amplifier

VcomLoutput

amplifier

VgoffHoutput


amplifier


circuit

C12

C9GVDD

VGOFFH

C10

Voltageadjustment

circuitRegulator

Charge-pump

circuit 1

C23PC23M

C21M

Charge-pump

circuit 2

C21P

C31P Charge-pump

circuit 3

C41-Vci4

C41+ Charge-pump

circuit 4

REGN

C14C17

AVDD

C18

C4

C3

C2

C6

VC1

C5

C3


AVDD

VGL

GVDD

VCOML





GRAMMSB LSB

PKP00PKP01PKP02

PKP10PKP11PKP12

PKP20PKP21PKP22

PKP30PKP31PKP32

PKP40PKP41PKP42

PKP50PKP51PKP52

PRP00PRP01PRP02

PRP10PRP11PRP12

VRP00VRP01VRP02

VRP10VRP11VRP12

VRP03

VRP13VRP14

PKN00PKN01PKN02

PKN10PKN11PKN12

PKN20PKN21PKN22

PKN30PKN31PKN32

PKN40PKN41PKN42

PKN50PKN51PKN52

PRN00PRN01PRN02

PRN10PRN11PRN12

VRN00VRN01VRN02

VRN10VRN11VRN12

VRN03

VRN13VRN14



GrayscaleAm plifier


ltRgt

LCD driver

64 grayscalecontrol

ltG gt

LCD driver

64 grayscalecontrol

ltBgt

LCD driver

64

V1

V0

V63

6 6 6

R G BLCD


Scan Mode

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176


11


01

G176 G175 G174 G173 hellip G4 G3 G2 G110

G1 G2 G3 G4 hellip G173 G174 G175 G17600

Scan ModeGSSM

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176


A

B

C

D

A

B

C

D






33 3 3 3 54333








G V D D

V G S


V I N P N 0

V I N P N 1

V I N P N 2

V I N P N 3

V I N P N 4

V I N P N 5

V I N P N 6

V I N P N 7

V 0

V 6 3

V 6 2

V 5 5

V 4 3

V 2 0

V 8

V 1V 2V 3

V 9

V 2 1

V 4 4

V 5 6V 5 7





Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge





8080Dummy Pad1195239742


Pad sizeum


UnitSize

Pad nameItems









Technology






25532V Process










Gat

e D

river

IC


Gat

e D

river

IC

T-Con

LTPS TFT-LCD


Source Driver IC

Gat

e D

river

IC

De-MUX






Outline









Digital vs Analog




TTL vs LVDS





XGA 325M (2 ports)

67M ( 1 port)

67M (2 ports)

SXGA 54M (2 ports)

54M (2 ports)

108M (2 ports)

Frequency

UXGA - 81M 162M LCD




6-bit ~80 ~60 ~50



RSDS Definition




8 Bit RGB RSDS Data

Start pulseR0 R1

R2 R3

R4 R5

G0 G1

G2 G3G4 G5

B0 B1

B2 B3

B4 B5

Invalid data

Invalid data

Invalid data

R6 R7

G6 G7

B6 B7



Single-end

FrontBack








Mini-LVDS

Data Bus Structure


Mini-LVDS

6 bit data 5 pairs


8 bit data 6 pairs

Mini-LVDS






TQFP100


RSDS vs Mini-LVDS













PPDSRSDSParameter



PPDSTM








PPDS Protocol





10-bit(1024灰階)


Memo



Over-8 bit data







Gn-1

Gn

Gray Level



Actual Response

Gn-1

Gn

Gray Level


Gn

Overdrive Response

Voltage by Driver







Overdrive Circuits

Memory

Lookup Table

Control ckts

Data

Dn

Dn+1

Ctrl

addressReadWrite

Datarsquo




ight

ness

Normal image

brig

htne

ss

bright imagebr

ight

ness


Other Technologies






LCD TV Trends


Size

BrightnessCR

Response Time

LCD Monitor

15-20rdquo

250400

25~16ms


Resolution XGA~UXGA

2002~2003

LCD TV


400~550500~700 gt550gt2k

25~16ms 16~12ms lt 8 ms

160160 176176


2004~2008

challenge

COST


Outline








TFTTFT



Controller025 μm

Sourcedriver05 μm


Gatedriver

06 μm HV



HV

Single chipHV

4 Chip TCPCOF Type

2 Chip COGCOF Type

1 Chip COG Type


HitachiSamsung

奇景聯詠

智寶科技







PWR SRAMGAMA64

APRSRAM

Gate Driver

PWR



18

64

18


Gate control

PowerSupplyCircuit

TimingGenerator

OSCSystem Interface


Indexregister

Controlregister

graylevelgenerator




Gammaadjusting

Addresscounter

VGHVGL

VgoffGVDDVGS

AVDD

18

G17

7G

176

G17

5 G

2G

1G

0

S396

S395

S394

S3 S2 S1

SPIC

ontrol

RW

Data

VDD3VDD

Latch circuitand

Vcom


Voltage Setting


VDD(20V ~ 33V)


VCI(25V ~ 33V)

BT2-0

BT2-0

VRH3-0

VREG2OUT

VCOM4-0

VGH(+9 ~ +165V)

AVDD(+35~ +55V)


VCL

VgoffH (to -50V)


VGL (-165 to -9V)

-1 times-1 times

VREG1OUT

VDV4-0

VCI1

VC2-0

VSS(0V)

VC3=1VRL3-0

GVDD(+30~ +50V)

VC3=0VRL3-0


Voltage Waveforms


sn(source output)

VCOM

Gn (Gate output)

VGH(+9 ~ +165V)


VgoffH (~to -50V)


GVDD(+30~ +50V)VDD(20V ~ 33V)

AVDD(+35~ +55V)

VSS(0V)






OVcomOUT


OVREG2OUT


OVREG1OUT


IOREGP





IOVCI



IOAVDD



-VDD

DescriptionIOSymbol




OVgoffL


OVgoffH



voltage

OVgoffOUT


IVgoff


higher than -150 V

OVGL



OVGH



OVcomL


OVcomH



IVcomR

DescriptionIOSymbol



mA2015-IVCI



by mode


Outputs


Outputs


Outputs





V5-3GVDD

V-5--16VGOFF

V-9--165VGL

V165-9VGH


V55-35AVDD

LCD Supply Voltage







Vcom


Vcom



Vgoff






V595583571VREG1OUT









VCI2

VCI VCI

VDDVSSVCIVSS

C7

int

VGL

VGH

C1VGH

C22P

C16


C11+

C1 5REGP

VCL

C31MVCI3

C22M

C12-C12+

C11-Vci1

VCIOUT

VCOMR

VGOFFOUT

VGOFFL

C20

C19

VCOMOUT

VCOMH

VREG1OUT

VREG2OUT

C 21

C 11


(Vgoffadjustment)


adjustment)

VcomHadjustment

circuit


circuit

GVDDoutput

amplifier

VcomHoutput

amplifier

VcomLoutput

amplifier

VgoffHoutput


amplifier


circuit

C12

C9GVDD

VGOFFH

C10

Voltageadjustment

circuitRegulator

Charge-pump

circuit 1

C23PC23M

C21M

Charge-pump

circuit 2

C21P

C31P Charge-pump

circuit 3

C41-Vci4

C41+ Charge-pump

circuit 4

REGN

C14C17

AVDD

C18

C4

C3

C2

C6

VC1

C5

C3


AVDD

VGL

GVDD

VCOML





GRAMMSB LSB

PKP00PKP01PKP02

PKP10PKP11PKP12

PKP20PKP21PKP22

PKP30PKP31PKP32

PKP40PKP41PKP42

PKP50PKP51PKP52

PRP00PRP01PRP02

PRP10PRP11PRP12

VRP00VRP01VRP02

VRP10VRP11VRP12

VRP03

VRP13VRP14

PKN00PKN01PKN02

PKN10PKN11PKN12

PKN20PKN21PKN22

PKN30PKN31PKN32

PKN40PKN41PKN42

PKN50PKN51PKN52

PRN00PRN01PRN02

PRN10PRN11PRN12

VRN00VRN01VRN02

VRN10VRN11VRN12

VRN03

VRN13VRN14



GrayscaleAm plifier


ltRgt

LCD driver

64 grayscalecontrol

ltG gt

LCD driver

64 grayscalecontrol

ltBgt

LCD driver

64

V1

V0

V63

6 6 6

R G BLCD


Scan Mode

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176


11


01

G176 G175 G174 G173 hellip G4 G3 G2 G110

G1 G2 G3 G4 hellip G173 G174 G175 G17600

Scan ModeGSSM

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176


A

B

C

D

A

B

C

D






33 3 3 3 54333








G V D D

V G S


V I N P N 0

V I N P N 1

V I N P N 2

V I N P N 3

V I N P N 4

V I N P N 5

V I N P N 6

V I N P N 7

V 0

V 6 3

V 6 2

V 5 5

V 4 3

V 2 0

V 8

V 1V 2V 3

V 9

V 2 1

V 4 4

V 5 6V 5 7





Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge





8080Dummy Pad1195239742


Pad sizeum


UnitSize

Pad nameItems









Technology






25532V Process










Gat

e D

river

IC


Gat

e D

river

IC

T-Con

LTPS TFT-LCD


Source Driver IC

Gat

e D

river

IC

De-MUX






Outline









Digital vs Analog




TTL vs LVDS





XGA 325M (2 ports)

67M ( 1 port)

67M (2 ports)

SXGA 54M (2 ports)

54M (2 ports)

108M (2 ports)

Frequency

UXGA - 81M 162M LCD




6-bit ~80 ~60 ~50



RSDS Definition




8 Bit RGB RSDS Data

Start pulseR0 R1

R2 R3

R4 R5

G0 G1

G2 G3G4 G5

B0 B1

B2 B3

B4 B5

Invalid data

Invalid data

Invalid data

R6 R7

G6 G7

B6 B7



Single-end

FrontBack








Mini-LVDS

Data Bus Structure


Mini-LVDS

6 bit data 5 pairs


8 bit data 6 pairs

Mini-LVDS






TQFP100


RSDS vs Mini-LVDS













PPDSRSDSParameter



PPDSTM








PPDS Protocol





10-bit(1024灰階)


Memo




ight

ness

Normal image

brig

htne

ss

bright imagebr

ight

ness


Other Technologies






LCD TV Trends


Size

BrightnessCR

Response Time

LCD Monitor

15-20rdquo

250400

25~16ms


Resolution XGA~UXGA

2002~2003

LCD TV


400~550500~700 gt550gt2k

25~16ms 16~12ms lt 8 ms

160160 176176


2004~2008

challenge

COST


Outline








TFTTFT



Controller025 μm

Sourcedriver05 μm


Gatedriver

06 μm HV



HV

Single chipHV

4 Chip TCPCOF Type

2 Chip COGCOF Type

1 Chip COG Type


HitachiSamsung

奇景聯詠

智寶科技







PWR SRAMGAMA64

APRSRAM

Gate Driver

PWR



18

64

18


Gate control

PowerSupplyCircuit

TimingGenerator

OSCSystem Interface


Indexregister

Controlregister

graylevelgenerator




Gammaadjusting

Addresscounter

VGHVGL

VgoffGVDDVGS

AVDD

18

G17

7G

176

G17

5 G

2G

1G

0

S396

S395

S394

S3 S2 S1

SPIC

ontrol

RW

Data

VDD3VDD

Latch circuitand

Vcom


Voltage Setting


VDD(20V ~ 33V)


VCI(25V ~ 33V)

BT2-0

BT2-0

VRH3-0

VREG2OUT

VCOM4-0

VGH(+9 ~ +165V)

AVDD(+35~ +55V)


VCL

VgoffH (to -50V)


VGL (-165 to -9V)

-1 times-1 times

VREG1OUT

VDV4-0

VCI1

VC2-0

VSS(0V)

VC3=1VRL3-0

GVDD(+30~ +50V)

VC3=0VRL3-0


Voltage Waveforms


sn(source output)

VCOM

Gn (Gate output)

VGH(+9 ~ +165V)


VgoffH (~to -50V)


GVDD(+30~ +50V)VDD(20V ~ 33V)

AVDD(+35~ +55V)

VSS(0V)






OVcomOUT


OVREG2OUT


OVREG1OUT


IOREGP





IOVCI



IOAVDD



-VDD

DescriptionIOSymbol




OVgoffL


OVgoffH



voltage

OVgoffOUT


IVgoff


higher than -150 V

OVGL



OVGH



OVcomL


OVcomH



IVcomR

DescriptionIOSymbol



mA2015-IVCI



by mode


Outputs


Outputs


Outputs





V5-3GVDD

V-5--16VGOFF

V-9--165VGL

V165-9VGH


V55-35AVDD

LCD Supply Voltage







Vcom


Vcom



Vgoff






V595583571VREG1OUT









VCI2

VCI VCI

VDDVSSVCIVSS

C7

int

VGL

VGH

C1VGH

C22P

C16


C11+

C1 5REGP

VCL

C31MVCI3

C22M

C12-C12+

C11-Vci1

VCIOUT

VCOMR

VGOFFOUT

VGOFFL

C20

C19

VCOMOUT

VCOMH

VREG1OUT

VREG2OUT

C 21

C 11


(Vgoffadjustment)


adjustment)

VcomHadjustment

circuit


circuit

GVDDoutput

amplifier

VcomHoutput

amplifier

VcomLoutput

amplifier

VgoffHoutput


amplifier


circuit

C12

C9GVDD

VGOFFH

C10

Voltageadjustment

circuitRegulator

Charge-pump

circuit 1

C23PC23M

C21M

Charge-pump

circuit 2

C21P

C31P Charge-pump

circuit 3

C41-Vci4

C41+ Charge-pump

circuit 4

REGN

C14C17

AVDD

C18

C4

C3

C2

C6

VC1

C5

C3


AVDD

VGL

GVDD

VCOML





GRAMMSB LSB

PKP00PKP01PKP02

PKP10PKP11PKP12

PKP20PKP21PKP22

PKP30PKP31PKP32

PKP40PKP41PKP42

PKP50PKP51PKP52

PRP00PRP01PRP02

PRP10PRP11PRP12

VRP00VRP01VRP02

VRP10VRP11VRP12

VRP03

VRP13VRP14

PKN00PKN01PKN02

PKN10PKN11PKN12

PKN20PKN21PKN22

PKN30PKN31PKN32

PKN40PKN41PKN42

PKN50PKN51PKN52

PRN00PRN01PRN02

PRN10PRN11PRN12

VRN00VRN01VRN02

VRN10VRN11VRN12

VRN03

VRN13VRN14



GrayscaleAm plifier


ltRgt

LCD driver

64 grayscalecontrol

ltG gt

LCD driver

64 grayscalecontrol

ltBgt

LCD driver

64

V1

V0

V63

6 6 6

R G BLCD


Scan Mode

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176


11


01

G176 G175 G174 G173 hellip G4 G3 G2 G110

G1 G2 G3 G4 hellip G173 G174 G175 G17600

Scan ModeGSSM

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176


A

B

C

D

A

B

C

D






33 3 3 3 54333








G V D D

V G S


V I N P N 0

V I N P N 1

V I N P N 2

V I N P N 3

V I N P N 4

V I N P N 5

V I N P N 6

V I N P N 7

V 0

V 6 3

V 6 2

V 5 5

V 4 3

V 2 0

V 8

V 1V 2V 3

V 9

V 2 1

V 4 4

V 5 6V 5 7





Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge





8080Dummy Pad1195239742


Pad sizeum


UnitSize

Pad nameItems









Technology






25532V Process










Gat

e D

river

IC


Gat

e D

river

IC

T-Con

LTPS TFT-LCD


Source Driver IC

Gat

e D

river

IC

De-MUX






Outline









Digital vs Analog




TTL vs LVDS





XGA 325M (2 ports)

67M ( 1 port)

67M (2 ports)

SXGA 54M (2 ports)

54M (2 ports)

108M (2 ports)

Frequency

UXGA - 81M 162M LCD




6-bit ~80 ~60 ~50



RSDS Definition




8 Bit RGB RSDS Data

Start pulseR0 R1

R2 R3

R4 R5

G0 G1

G2 G3G4 G5

B0 B1

B2 B3

B4 B5

Invalid data

Invalid data

Invalid data

R6 R7

G6 G7

B6 B7



Single-end

FrontBack








Mini-LVDS

Data Bus Structure


Mini-LVDS

6 bit data 5 pairs


8 bit data 6 pairs

Mini-LVDS






TQFP100


RSDS vs Mini-LVDS













PPDSRSDSParameter



PPDSTM








PPDS Protocol





10-bit(1024灰階)


Memo



TFTTFT



Controller025 μm

Sourcedriver05 μm


Gatedriver

06 μm HV



HV

Single chipHV

4 Chip TCPCOF Type

2 Chip COGCOF Type

1 Chip COG Type


HitachiSamsung

奇景聯詠

智寶科技







PWR SRAMGAMA64

APRSRAM

Gate Driver

PWR



18

64

18


Gate control

PowerSupplyCircuit

TimingGenerator

OSCSystem Interface


Indexregister

Controlregister

graylevelgenerator




Gammaadjusting

Addresscounter

VGHVGL

VgoffGVDDVGS

AVDD

18

G17

7G

176

G17

5 G

2G

1G

0

S396

S395

S394

S3 S2 S1

SPIC

ontrol

RW

Data

VDD3VDD

Latch circuitand

Vcom


Voltage Setting


VDD(20V ~ 33V)


VCI(25V ~ 33V)

BT2-0

BT2-0

VRH3-0

VREG2OUT

VCOM4-0

VGH(+9 ~ +165V)

AVDD(+35~ +55V)


VCL

VgoffH (to -50V)


VGL (-165 to -9V)

-1 times-1 times

VREG1OUT

VDV4-0

VCI1

VC2-0

VSS(0V)

VC3=1VRL3-0

GVDD(+30~ +50V)

VC3=0VRL3-0


Voltage Waveforms


sn(source output)

VCOM

Gn (Gate output)

VGH(+9 ~ +165V)


VgoffH (~to -50V)


GVDD(+30~ +50V)VDD(20V ~ 33V)

AVDD(+35~ +55V)

VSS(0V)






OVcomOUT


OVREG2OUT


OVREG1OUT


IOREGP





IOVCI



IOAVDD



-VDD

DescriptionIOSymbol




OVgoffL


OVgoffH



voltage

OVgoffOUT


IVgoff


higher than -150 V

OVGL



OVGH



OVcomL


OVcomH



IVcomR

DescriptionIOSymbol



mA2015-IVCI



by mode


Outputs


Outputs


Outputs





V5-3GVDD

V-5--16VGOFF

V-9--165VGL

V165-9VGH


V55-35AVDD

LCD Supply Voltage







Vcom


Vcom



Vgoff






V595583571VREG1OUT









VCI2

VCI VCI

VDDVSSVCIVSS

C7

int

VGL

VGH

C1VGH

C22P

C16


C11+

C1 5REGP

VCL

C31MVCI3

C22M

C12-C12+

C11-Vci1

VCIOUT

VCOMR

VGOFFOUT

VGOFFL

C20

C19

VCOMOUT

VCOMH

VREG1OUT

VREG2OUT

C 21

C 11


(Vgoffadjustment)


adjustment)

VcomHadjustment

circuit


circuit

GVDDoutput

amplifier

VcomHoutput

amplifier

VcomLoutput

amplifier

VgoffHoutput


amplifier


circuit

C12

C9GVDD

VGOFFH

C10

Voltageadjustment

circuitRegulator

Charge-pump

circuit 1

C23PC23M

C21M

Charge-pump

circuit 2

C21P

C31P Charge-pump

circuit 3

C41-Vci4

C41+ Charge-pump

circuit 4

REGN

C14C17

AVDD

C18

C4

C3

C2

C6

VC1

C5

C3


AVDD

VGL

GVDD

VCOML





GRAMMSB LSB

PKP00PKP01PKP02

PKP10PKP11PKP12

PKP20PKP21PKP22

PKP30PKP31PKP32

PKP40PKP41PKP42

PKP50PKP51PKP52

PRP00PRP01PRP02

PRP10PRP11PRP12

VRP00VRP01VRP02

VRP10VRP11VRP12

VRP03

VRP13VRP14

PKN00PKN01PKN02

PKN10PKN11PKN12

PKN20PKN21PKN22

PKN30PKN31PKN32

PKN40PKN41PKN42

PKN50PKN51PKN52

PRN00PRN01PRN02

PRN10PRN11PRN12

VRN00VRN01VRN02

VRN10VRN11VRN12

VRN03

VRN13VRN14



GrayscaleAm plifier


ltRgt

LCD driver

64 grayscalecontrol

ltG gt

LCD driver

64 grayscalecontrol

ltBgt

LCD driver

64

V1

V0

V63

6 6 6

R G BLCD


Scan Mode

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176


11


01

G176 G175 G174 G173 hellip G4 G3 G2 G110

G1 G2 G3 G4 hellip G173 G174 G175 G17600

Scan ModeGSSM

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176


A

B

C

D

A

B

C

D






33 3 3 3 54333








G V D D

V G S


V I N P N 0

V I N P N 1

V I N P N 2

V I N P N 3

V I N P N 4

V I N P N 5

V I N P N 6

V I N P N 7

V 0

V 6 3

V 6 2

V 5 5

V 4 3

V 2 0

V 8

V 1V 2V 3

V 9

V 2 1

V 4 4

V 5 6V 5 7





Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge





8080Dummy Pad1195239742


Pad sizeum


UnitSize

Pad nameItems









Technology






25532V Process










Gat

e D

river

IC


Gat

e D

river

IC

T-Con

LTPS TFT-LCD


Source Driver IC

Gat

e D

river

IC

De-MUX






Outline









Digital vs Analog




TTL vs LVDS





XGA 325M (2 ports)

67M ( 1 port)

67M (2 ports)

SXGA 54M (2 ports)

54M (2 ports)

108M (2 ports)

Frequency

UXGA - 81M 162M LCD




6-bit ~80 ~60 ~50



RSDS Definition




8 Bit RGB RSDS Data

Start pulseR0 R1

R2 R3

R4 R5

G0 G1

G2 G3G4 G5

B0 B1

B2 B3

B4 B5

Invalid data

Invalid data

Invalid data

R6 R7

G6 G7

B6 B7



Single-end

FrontBack








Mini-LVDS

Data Bus Structure


Mini-LVDS

6 bit data 5 pairs


8 bit data 6 pairs

Mini-LVDS






TQFP100


RSDS vs Mini-LVDS













PPDSRSDSParameter



PPDSTM








PPDS Protocol





10-bit(1024灰階)


Memo


Voltage Setting


VDD(20V ~ 33V)


VCI(25V ~ 33V)

BT2-0

BT2-0

VRH3-0

VREG2OUT

VCOM4-0

VGH(+9 ~ +165V)

AVDD(+35~ +55V)


VCL

VgoffH (to -50V)


VGL (-165 to -9V)

-1 times-1 times

VREG1OUT

VDV4-0

VCI1

VC2-0

VSS(0V)

VC3=1VRL3-0

GVDD(+30~ +50V)

VC3=0VRL3-0


Voltage Waveforms


sn(source output)

VCOM

Gn (Gate output)

VGH(+9 ~ +165V)


VgoffH (~to -50V)


GVDD(+30~ +50V)VDD(20V ~ 33V)

AVDD(+35~ +55V)

VSS(0V)






OVcomOUT


OVREG2OUT


OVREG1OUT


IOREGP





IOVCI



IOAVDD



-VDD

DescriptionIOSymbol




OVgoffL


OVgoffH



voltage

OVgoffOUT


IVgoff


higher than -150 V

OVGL



OVGH



OVcomL


OVcomH



IVcomR

DescriptionIOSymbol



mA2015-IVCI



by mode


Outputs


Outputs


Outputs





V5-3GVDD

V-5--16VGOFF

V-9--165VGL

V165-9VGH


V55-35AVDD

LCD Supply Voltage







Vcom


Vcom



Vgoff






V595583571VREG1OUT









VCI2

VCI VCI

VDDVSSVCIVSS

C7

int

VGL

VGH

C1VGH

C22P

C16


C11+

C1 5REGP

VCL

C31MVCI3

C22M

C12-C12+

C11-Vci1

VCIOUT

VCOMR

VGOFFOUT

VGOFFL

C20

C19

VCOMOUT

VCOMH

VREG1OUT

VREG2OUT

C 21

C 11


(Vgoffadjustment)


adjustment)

VcomHadjustment

circuit


circuit

GVDDoutput

amplifier

VcomHoutput

amplifier

VcomLoutput

amplifier

VgoffHoutput


amplifier


circuit

C12

C9GVDD

VGOFFH

C10

Voltageadjustment

circuitRegulator

Charge-pump

circuit 1

C23PC23M

C21M

Charge-pump

circuit 2

C21P

C31P Charge-pump

circuit 3

C41-Vci4

C41+ Charge-pump

circuit 4

REGN

C14C17

AVDD

C18

C4

C3

C2

C6

VC1

C5

C3


AVDD

VGL

GVDD

VCOML





GRAMMSB LSB

PKP00PKP01PKP02

PKP10PKP11PKP12

PKP20PKP21PKP22

PKP30PKP31PKP32

PKP40PKP41PKP42

PKP50PKP51PKP52

PRP00PRP01PRP02

PRP10PRP11PRP12

VRP00VRP01VRP02

VRP10VRP11VRP12

VRP03

VRP13VRP14

PKN00PKN01PKN02

PKN10PKN11PKN12

PKN20PKN21PKN22

PKN30PKN31PKN32

PKN40PKN41PKN42

PKN50PKN51PKN52

PRN00PRN01PRN02

PRN10PRN11PRN12

VRN00VRN01VRN02

VRN10VRN11VRN12

VRN03

VRN13VRN14



GrayscaleAm plifier


ltRgt

LCD driver

64 grayscalecontrol

ltG gt

LCD driver

64 grayscalecontrol

ltBgt

LCD driver

64

V1

V0

V63

6 6 6

R G BLCD


Scan Mode

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176


11


01

G176 G175 G174 G173 hellip G4 G3 G2 G110

G1 G2 G3 G4 hellip G173 G174 G175 G17600

Scan ModeGSSM

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176


A

B

C

D

A

B

C

D






33 3 3 3 54333








G V D D

V G S


V I N P N 0

V I N P N 1

V I N P N 2

V I N P N 3

V I N P N 4

V I N P N 5

V I N P N 6

V I N P N 7

V 0

V 6 3

V 6 2

V 5 5

V 4 3

V 2 0

V 8

V 1V 2V 3

V 9

V 2 1

V 4 4

V 5 6V 5 7





Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge





8080Dummy Pad1195239742


Pad sizeum


UnitSize

Pad nameItems









Technology






25532V Process










Gat

e D

river

IC


Gat

e D

river

IC

T-Con

LTPS TFT-LCD


Source Driver IC

Gat

e D

river

IC

De-MUX






Outline









Digital vs Analog




TTL vs LVDS





XGA 325M (2 ports)

67M ( 1 port)

67M (2 ports)

SXGA 54M (2 ports)

54M (2 ports)

108M (2 ports)

Frequency

UXGA - 81M 162M LCD




6-bit ~80 ~60 ~50



RSDS Definition




8 Bit RGB RSDS Data

Start pulseR0 R1

R2 R3

R4 R5

G0 G1

G2 G3G4 G5

B0 B1

B2 B3

B4 B5

Invalid data

Invalid data

Invalid data

R6 R7

G6 G7

B6 B7



Single-end

FrontBack








Mini-LVDS

Data Bus Structure


Mini-LVDS

6 bit data 5 pairs


8 bit data 6 pairs

Mini-LVDS






TQFP100


RSDS vs Mini-LVDS













PPDSRSDSParameter



PPDSTM








PPDS Protocol





10-bit(1024灰階)


Memo



mA2015-IVCI



by mode


Outputs


Outputs


Outputs





V5-3GVDD

V-5--16VGOFF

V-9--165VGL

V165-9VGH


V55-35AVDD

LCD Supply Voltage







Vcom


Vcom



Vgoff






V595583571VREG1OUT









VCI2

VCI VCI

VDDVSSVCIVSS

C7

int

VGL

VGH

C1VGH

C22P

C16


C11+

C1 5REGP

VCL

C31MVCI3

C22M

C12-C12+

C11-Vci1

VCIOUT

VCOMR

VGOFFOUT

VGOFFL

C20

C19

VCOMOUT

VCOMH

VREG1OUT

VREG2OUT

C 21

C 11


(Vgoffadjustment)


adjustment)

VcomHadjustment

circuit


circuit

GVDDoutput

amplifier

VcomHoutput

amplifier

VcomLoutput

amplifier

VgoffHoutput


amplifier


circuit

C12

C9GVDD

VGOFFH

C10

Voltageadjustment

circuitRegulator

Charge-pump

circuit 1

C23PC23M

C21M

Charge-pump

circuit 2

C21P

C31P Charge-pump

circuit 3

C41-Vci4

C41+ Charge-pump

circuit 4

REGN

C14C17

AVDD

C18

C4

C3

C2

C6

VC1

C5

C3


AVDD

VGL

GVDD

VCOML





GRAMMSB LSB

PKP00PKP01PKP02

PKP10PKP11PKP12

PKP20PKP21PKP22

PKP30PKP31PKP32

PKP40PKP41PKP42

PKP50PKP51PKP52

PRP00PRP01PRP02

PRP10PRP11PRP12

VRP00VRP01VRP02

VRP10VRP11VRP12

VRP03

VRP13VRP14

PKN00PKN01PKN02

PKN10PKN11PKN12

PKN20PKN21PKN22

PKN30PKN31PKN32

PKN40PKN41PKN42

PKN50PKN51PKN52

PRN00PRN01PRN02

PRN10PRN11PRN12

VRN00VRN01VRN02

VRN10VRN11VRN12

VRN03

VRN13VRN14



GrayscaleAm plifier


ltRgt

LCD driver

64 grayscalecontrol

ltG gt

LCD driver

64 grayscalecontrol

ltBgt

LCD driver

64

V1

V0

V63

6 6 6

R G BLCD


Scan Mode

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176


11


01

G176 G175 G174 G173 hellip G4 G3 G2 G110

G1 G2 G3 G4 hellip G173 G174 G175 G17600

Scan ModeGSSM

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176


A

B

C

D

A

B

C

D






33 3 3 3 54333








G V D D

V G S


V I N P N 0

V I N P N 1

V I N P N 2

V I N P N 3

V I N P N 4

V I N P N 5

V I N P N 6

V I N P N 7

V 0

V 6 3

V 6 2

V 5 5

V 4 3

V 2 0

V 8

V 1V 2V 3

V 9

V 2 1

V 4 4

V 5 6V 5 7





Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge





8080Dummy Pad1195239742


Pad sizeum


UnitSize

Pad nameItems









Technology






25532V Process










Gat

e D

river

IC


Gat

e D

river

IC

T-Con

LTPS TFT-LCD


Source Driver IC

Gat

e D

river

IC

De-MUX






Outline









Digital vs Analog




TTL vs LVDS





XGA 325M (2 ports)

67M ( 1 port)

67M (2 ports)

SXGA 54M (2 ports)

54M (2 ports)

108M (2 ports)

Frequency

UXGA - 81M 162M LCD




6-bit ~80 ~60 ~50



RSDS Definition




8 Bit RGB RSDS Data

Start pulseR0 R1

R2 R3

R4 R5

G0 G1

G2 G3G4 G5

B0 B1

B2 B3

B4 B5

Invalid data

Invalid data

Invalid data

R6 R7

G6 G7

B6 B7



Single-end

FrontBack








Mini-LVDS

Data Bus Structure


Mini-LVDS

6 bit data 5 pairs


8 bit data 6 pairs

Mini-LVDS






TQFP100


RSDS vs Mini-LVDS













PPDSRSDSParameter



PPDSTM








PPDS Protocol





10-bit(1024灰階)


Memo


Scan Mode

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176


11


01

G176 G175 G174 G173 hellip G4 G3 G2 G110

G1 G2 G3 G4 hellip G173 G174 G175 G17600

Scan ModeGSSM

G1 G2

TFTPanel

G175 G176

ODD EVEN

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176

G1

G2

TFTPanel

G175

G176

NT3911

G1 G2G175 G176


A

B

C

D

A

B

C

D






33 3 3 3 54333








G V D D

V G S


V I N P N 0

V I N P N 1

V I N P N 2

V I N P N 3

V I N P N 4

V I N P N 5

V I N P N 6

V I N P N 7

V 0

V 6 3

V 6 2

V 5 5

V 4 3

V 2 0

V 8

V 1V 2V 3

V 9

V 2 1

V 4 4

V 5 6V 5 7





Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge

Gra

ysca

le V

olta

ge





8080Dummy Pad1195239742


Pad sizeum


UnitSize

Pad nameItems









Technology






25532V Process










Gat

e D

river

IC


Gat

e D

river

IC

T-Con

LTPS TFT-LCD


Source Driver IC

Gat

e D

river

IC

De-MUX






Outline









Digital vs Analog




TTL vs LVDS





XGA 325M (2 ports)

67M ( 1 port)

67M (2 ports)

SXGA 54M (2 ports)

54M (2 ports)

108M (2 ports)

Frequency

UXGA - 81M 162M LCD




6-bit ~80 ~60 ~50



RSDS Definition




8 Bit RGB RSDS Data

Start pulseR0 R1

R2 R3

R4 R5

G0 G1

G2 G3G4 G5

B0 B1

B2 B3

B4 B5

Invalid data

Invalid data

Invalid data

R6 R7

G6 G7

B6 B7



Single-end

FrontBack








Mini-LVDS

Data Bus Structure


Mini-LVDS

6 bit data 5 pairs


8 bit data 6 pairs

Mini-LVDS






TQFP100


RSDS vs Mini-LVDS













PPDSRSDSParameter



PPDSTM








PPDS Protocol





10-bit(1024灰階)


Memo









Technology






25532V Process










Gat

e D

river

IC


Gat

e D

river

IC

T-Con

LTPS TFT-LCD


Source Driver IC

Gat

e D

river

IC

De-MUX






Outline









Digital vs Analog




TTL vs LVDS





XGA 325M (2 ports)

67M ( 1 port)

67M (2 ports)

SXGA 54M (2 ports)

54M (2 ports)

108M (2 ports)

Frequency

UXGA - 81M 162M LCD




6-bit ~80 ~60 ~50



RSDS Definition




8 Bit RGB RSDS Data

Start pulseR0 R1

R2 R3

R4 R5

G0 G1

G2 G3G4 G5

B0 B1

B2 B3

B4 B5

Invalid data

Invalid data

Invalid data

R6 R7

G6 G7

B6 B7



Single-end

FrontBack








Mini-LVDS

Data Bus Structure


Mini-LVDS

6 bit data 5 pairs


8 bit data 6 pairs

Mini-LVDS






TQFP100


RSDS vs Mini-LVDS













PPDSRSDSParameter



PPDSTM








PPDS Protocol





10-bit(1024灰階)


Memo


Outline









Digital vs Analog




TTL vs LVDS





XGA 325M (2 ports)

67M ( 1 port)

67M (2 ports)

SXGA 54M (2 ports)

54M (2 ports)

108M (2 ports)

Frequency

UXGA - 81M 162M LCD




6-bit ~80 ~60 ~50



RSDS Definition




8 Bit RGB RSDS Data

Start pulseR0 R1

R2 R3

R4 R5

G0 G1

G2 G3G4 G5

B0 B1

B2 B3

B4 B5

Invalid data

Invalid data

Invalid data

R6 R7

G6 G7

B6 B7



Single-end

FrontBack








Mini-LVDS

Data Bus Structure


Mini-LVDS

6 bit data 5 pairs


8 bit data 6 pairs

Mini-LVDS






TQFP100


RSDS vs Mini-LVDS













PPDSRSDSParameter



PPDSTM








PPDS Protocol





10-bit(1024灰階)


Memo


TTL vs LVDS





XGA 325M (2 ports)

67M ( 1 port)

67M (2 ports)

SXGA 54M (2 ports)

54M (2 ports)

108M (2 ports)

Frequency

UXGA - 81M 162M LCD




6-bit ~80 ~60 ~50



RSDS Definition




8 Bit RGB RSDS Data

Start pulseR0 R1

R2 R3

R4 R5

G0 G1

G2 G3G4 G5

B0 B1

B2 B3

B4 B5

Invalid data

Invalid data

Invalid data

R6 R7

G6 G7

B6 B7



Single-end

FrontBack








Mini-LVDS

Data Bus Structure


Mini-LVDS

6 bit data 5 pairs


8 bit data 6 pairs

Mini-LVDS






TQFP100


RSDS vs Mini-LVDS













PPDSRSDSParameter



PPDSTM








PPDS Protocol





10-bit(1024灰階)


Memo



Single-end

FrontBack








Mini-LVDS

Data Bus Structure


Mini-LVDS

6 bit data 5 pairs


8 bit data 6 pairs

Mini-LVDS






TQFP100


RSDS vs Mini-LVDS













PPDSRSDSParameter



PPDSTM








PPDS Protocol





10-bit(1024灰階)


Memo


8 bit data 6 pairs

Mini-LVDS






TQFP100


RSDS vs Mini-LVDS













PPDSRSDSParameter



PPDSTM








PPDS Protocol





10-bit(1024灰階)


Memo


PPDS Protocol





10-bit(1024灰階)


Memo

introduction to lcd driver ic driving circuits of tft- lcd ... · introduction to lcd driver ic •...

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