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1
Kỹ Thuật Số
Giảng viên
Lê Chí Thông
Bộ môn Điện tử; Khoa Điện-Điện tử
Đại học Bách Khoa TP.HCM
ĐT: 0902-445-012
Email: [email protected]; [email protected]
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Nội Dung Tóm Tắt
• Môn học này giới thiệu nhiều chủ đề về các nguyên tắc và
thực hành thiết kế số, bao gồm: hệ thống số; đại số Boole,
các cổng logic, tối thiểu hóa mạch; hệ tổ hợp; bộ nhớROM, RAM và logic khả lập trình, Hệ tuần tự: chốt, flip-
flop, thanh ghi, bộ đếm, máy trạng thái; các họ vi mạch số;
ngôn ngữ mô tả phần cứng. Giới thiệu chuyển đổi tương
tự-số và tổ chức máy tính.
• Sau khi đạt môn này SV có khả năng hiểu, thiết kế và
xây dựng các hệ thống số tổ hợp và tuần tự.
Sách và Tài Liệu
• John F. Wakerly – Digital Design, Principles and
Practices, 4th Ed–Prentice-Hall, 2006
• Katz and Boriello – Contemporary Logic Design, 2nd Ed.–
Prentice-Hall, 2005
• M. Morris Mano and Charles R. Kime – Logic and
Computer Design Fundamentals, 3rd Ed.–Prentice-Hall,
2004
• Nguyễn Như Anh – Kỹ Thuật Số 1, Nhà xuất bản Đại học
Quốc gia TP.HCM.
• Hồ Trung Mỹ – Kỹ Thuật Số 2, Nhà xuất bản Đại học
Quốc gia TP.HCM
• Lê Chí Thông – Kỹ Thuật Số cơ khí – Nhà xuất bản Đại
học Quốc gia TP.HCM
• Bài giảng và bài tập.
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Điểm và Cách Đánh Giá
• Kiểm tra giữa kỳ (60 – 90 phút): 20%
• Thi cuối kỳ (120 phút): 80%
Nội Dung Chương Trình
Chương 1: Hệ Thống Số Đếm
Chương 2: Đại Số Boole
Chương 3: Hệ Tổ Hợp
Chương 4: Hệ Tuần Tự
Chương 5: Các Thiết Bị Logic Lập Trình Được (PLD)
Chương 6: Ngôn Ngữ Mô Tả Phần Cứng (VHDL)
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7
Chöông 1: HEÄ THOÁNG SOÁ ÑEÁM – SOÁ NHÒ PHAÂN
I. Caùc heä thoáng soá ñeám:1. Caùc khaùi nieäm:
- Cô soá (r - radix):
- Troïng soá (weight):
- Giaù trò (value):
laø soá löôïng kyù töï chöõ soá (kyù soá - digit)
söû duïng ñeå bieåu dieãn trong heä thoáng soá ñeám
ñaïi löôïng bieåu dieãn cho vò trí cuûa 1 con soá trong chuoãi soá.
Troïng soá = Cô soá Vò trí
tính baèng toång theo troïng soá
Giaù trò = ΣΣΣΣ (Kyù soá x Troïng soá)
8
400 + 0 + 7 + 0.6 + 0.02 + 0.005 = 407.625
4 0 7 . 6 2 5
102 101 100 . 10-1 10-2 10-3
4x102 0x101 7x100 . 6x10-1 2x10-2 5x10-3
400 0 7 . 0.6 0.02 0.005
a. Soá thaäp phaân (Decimal): Cô soá r = 10
b. Soá nhò phaân (Binary): Cô soá r = 2
1 0 1 . 0 1 1
4 + 0 + 1 + 0 + 0.25 + 0.125 = 5.375
22 21 20 . 2-1 2-2 2-3
1x22 0x21 1x20 . 0x2-1 1x2-2 1x2-3
4 0 1 . 0 0.25 0.125
5
9
c. Soá thaäp luïc phaân (Hexadecimal): Cô soá r = 16
Hexadecimal Decimal Binary Hexadecimal Decimal Binary
01234567
01234567
00000001001000110100010101100111
89
ABCDEF
89
101112131415
10001001101010111100110111101111
5 A 0 . 4 D 1
1280 + 160 + 0 + 0.25 + 0.0508 + 0.0002 = 1440.301
162 161 160 . 16-1 16-2 16-3
5x162 10x161 0x160 . 4x16-1 13x16-2 1x16-3
1280 160 0 . 0.25 0.0508 0.0002
10
2. Chuyeån ñoåi cô soá:
a. Töø thaäp phaân sang nhò phaân
8 . 6258 : 2 = 4 dö 0 (LSB)4 : 2 = 2 dö 02 : 2 = 1 dö 01 : 2 = 0 dö 1
0.625 x 2 = 1.25 phaàn nguyeân 1 (MSB)0.25 x 2 = 0.5 phaàn nguyeân 00.5 x 2 = 1.0 phaàn nguyeân 1
1 0 0 0 .. 1 0 1 B
6
11
b. Töø thaäp phaân sang thaäp luïc phaân:
1 4 8 0 . 4 2 9 6 8 7 5
1480 : 16 = 92 dö 8 (LSD)92 : 16 = 5 dö 12
5 : 16 = 0 dö 5
0.4296875 x 16 = 6.875 phaàn nguyeân 6 (MSD)0.875 x 16 = 14.0 phaàn nguyeân 14
5 C 8 .. 6 E H
12
d. Töø thaäp luïc phaân sang nhò phaân:
c. Töø nhò phaân sang thaäp luïc phaân:
1 1 1 0 1 1 0 1 0 1 1 1 0 1 . 0 1 1 0 1 0 1 B0 0 0
. 6 A H
2 C 9 . E 8 H
0 0 1 0 1 1 0 0 1 0 0 1 . 1 1 1 0 1 0 0 0 B
3 B 5 D .
7
13
II. Soá nhò phaân (Binary):
1.Caùc tính chaát cuûa soá nhò phaân
- Soá nhò phaân n bit coù 2n giaù trò töø 0 ñeán 2n - 1
- Soá nhò phaân coù giaù trò 2n-1: 1 … … … 1 (n bit 1)vaø giaù trò 2n: 1 0 … … ... 0 (n bit 0)
- Soá nhò phaân coù giaù trò leû laø soá coù LSB = 1; ngöôïc laïi giaù trò chaün laø soá coù LSB = 0
- Caùc boäi soá cuûa bit:1 B (Byte) = 8 bit1 KB = 210 B = 1024 B1 MB = 210 KB = 220 B1 GB = 210 MB
14
2. Caùc pheùp toaùn soá hoïc treân soá nhò phaân:
a. Pheùp coäng:
0 + 0 = 00 + 1 = 11 + 0 = 11 + 1 = 0 nhôù 1 0
1 0 1 1 11 0 1
0111
111
b. Pheùp tröø:
0 - 0 = 00 - 1 = 1 möôïn 11 - 0 = 11 - 1 = 0 1
1 1 0 1 01 1 1
1001
-1-1-1
8
15
c. Pheùp nhaân: 1 0 1 1 1 0 0 1
1 0 1 1 0 0 0 0
0 0 0 0 1 0 1 1
1 1 0 0 0 1 1 d. Pheùp chia:
1 0 0 1 0 0 0 1 1 0 1 1 1 0 1 1
1 1 1 1
0 1
1 0 1 1
1 1 0
0
1
1
1 0 1 1
1 0
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3. Maõ nhò phaân:
Töø maõ:laø caùc toå hôïp nhò phaân ñöôïc söû duïng trong loaïi maõ nhò phaân
a. Maõ nhò phaân cho soá thaäp phaân (BCD – Binary Coded Decimal)
Soá thaäp phaân
0123456789
BCD (2 4 2 1)
0 0 0 00 0 0 10 0 1 00 0 1 10 1 0 0 1 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1
BCD quaù 3
0 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 0
Maõ 1 trong 10
0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 00 0 0 0 0 0 0 1 0 00 0 0 0 0 0 1 0 0 00 0 0 0 0 1 0 0 0 00 0 0 0 1 0 0 0 0 00 0 0 1 0 0 0 0 0 00 0 1 0 0 0 0 0 0 00 1 0 0 0 0 0 0 0 01 0 0 0 0 0 0 0 0 0
BCD (8 4 2 1)
0 0 0 00 0 0 10 0 1 00 0 1 10 1 0 0 0 1 0 10 1 1 00 1 1 11 0 0 01 0 0 1
9
17
b. Maõ Gray: laø maõ nhò phaân maø 2 giaù trò lieân tieáp nhau coù toå hôïp bit bieåu dieãn chæ khaùc nhau 1 bit
Giaù trò Binary Gray
01234
0 0 00 0 10 1 00 1 11 0 0
0 0 00 0 10 1 10 1 01 1 0
Ñoåi töø Binary sang Gray
1 0 1 1 0
1
1
1
0
1
1
0
1
1
Ñoåi töø Gray sang Binary
1 1 0 0 1
1
1
0
0
0
0
0
0
1
Gray:
Gray:
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c. Maõ LED 7 ñoaïn:
a
g
d
b
c
f
e
Giaù trò a b c d e f g
0123456789
1 1 1 1 1 1 00 1 1 0 0 0 01 1 0 1 1 0 11 1 1 1 0 0 10 1 1 0 0 1 11 0 1 1 0 1 11 0 1 1 1 1 11 1 1 0 0 0 01 1 1 1 1 1 11 1 1 1 0 1 1
d. Maõ 1 trong n:laø maõ nhò phaân n bit coù moãi töø maõ chæ coù 1 bit laø 1 (hoaëc 0) vaø n-1 bit coøn laïi laø 0 (hoaëc 1)
Maõ 1 trong 4:
1 0 0 00 1 0 00 0 1 00 0 0 1
0 1 1 11 0 1 11 1 0 11 1 1 0
hoaëc
10
19
(Coät) b6 b5 b4(Haøng) 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
b3b2b1b
0
Hex 0 1 2 3 4 5 6 7
0 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1
0123456789
ABCDEF
NULSOHSTX
ETXEOT
ENQACK
BELBS
HTLF
VTFF
CRSO
SI
DLEDC1DC2DC3DC4
NAKSYNETB
CANEM
SUBESC
FSGSRSUS
SP!
”#$
%&
’()
*+
,-./
0123456789
:;
<=>?
@ABCDEF
GH
IJ
KL
MNO
PQR
STUV
WXYZ
[\]
^_
`abcde
fgh
ij
kl
mno
pqrst
uv
wxyz{|
}~
DEL
d. Maõ kyù töï ASCII:
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III. Soá nhò phaân coù daáu :
1. Bieåu dieãn soá coù daáu:
a. Soá coù daáu theo bieân ñoä (Signed_Magnitude):
- Bit MSB laø bit daáu: 0 laø soá döông vaø 1 laø soá aâm, caùc bit coøn laïi bieåu dieãn giaù trò ñoä lôùn
+ 13 : 0 1 1 0 1
- 13 : 1 1 1 0 1
- Phaïm vi bieåu dieãn:
- (2n-1 – 1) ÷ + (2n-1 – 1)
11
21
b. Soá buø_1 (1’s Complement):
- Soá buø_1 cuûa 1 soá nhò phaân N coù chieàu daøi n bit
Buø_1 (1 0 0 1) = 24 - 1 - 1 0 0 1= 1 1 1 1 - 1 0 0 1= 0 1 1 0
- Coù theå laáy Buø_1 cuûa 1 soá nhò phaân baèng caùch laáy ñaûo töøng bit cuûa noù (0 thaønh 1 vaø 1 thaønh 0)
- Phaïm vi bieåu dieãn- (2n-1 – 1) ÷ + (2n-1 – 1)
- Bieåu dieãn soá coù daáu buø_1:* Soá coù giaù trò döông:
bit daáu = 0, caùc bit coøn laïi bieåu dieãn ñoä lôùn * Soá coù giaù trò aâm:
laáy buø_1 cuûa soá döông coù cuøng ñoä lôùn
Buø_1 (N) = 2n – 1 – N
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c. Soá buø_2 (2’s Complement):
- Soá buø_2 cuûa 1 soá nhò phaân N coù chieàu daøi n bit cuõng coù n bit
Buø_2 (N) = 2n – N = Buø_1 (N) + 1
Buø_2 (1 0 0 1) = 24 - 1 0 0 1= 1 0 0 0 0 - 1 0 0 1
= 0 1 1 1
hoaëc Buø_2 (1 0 0 1) = Buø_1 (1 0 0 1) + 1= 0 1 1 0 + 1
= 0 1 1 1
12
23
- Phaïm vi bieåu dieãn soá nhò phaân coù daáu n bit
Giaù trò döông Giaù trò aâm 000 = 0001 = + 1010 = + 2011 = + 3
100 = - 4101 = - 3110 = - 2111 = - 1
- Bieåu dieãn soá coù daáu buø_2:* Soá coù giaù trò döông:
bit daáu = 0, caùc bit coøn laïi bieåu dieãn ñoä lôùn * Soá coù giaù trò aâm:
laáy buø_2 cuûa soá döông coù cuøng ñoä lôùn
- (2n-1 ) ÷ + (2n-1 - 1)
24
- Ñeå tìm ñöôïc giaù trò cuûa soá aâm:ta laáy buø_2 cuûa noù; seõ nhaän ñöôïc soá döông coù cuøng bieân ñoä
Soá aâm 1 1 0 0 0 1 coù giaù trò : ………
Buø_2 (1 1 0 0 0 1) = 0 0 1 1 1 1 : + 15
- 15
- Môû roäng chieàu daøi bit soá coù daáu: soá döông theâm caùc bit 0 vaø soá aâm theâm caùc bit 1 vaøo tröôùc
- Laáy buø_2 hai laàn moät soá thì baèng chính soá ñoù
- Giaù trò -1 ñöôïc bieåu dieãn laø 1 …. 11 (n bit 1)
- Giaù trò -2n ñöôïc bieåu dieãn laø 1 0 0 .... 0 0 (n bit 0)- 32 = - 25 : 1 0 0 0 0 0
- 3 : 1 0 1 = 1 1 1 0 1
13
25
2. Caùc pheùp toaùn coäng tröø soá coù daáu:
- Thöïc hieän treân toaùn haïng coù cuøng chieàu daøi bit,vaø keát quaû cuõng coù cuøng soá bit
- Keát quaû ñuùng neáu naèm trong phaïm vi bieåu dieãn soá coù daáu.(neáu keát quaû sai thì caàn môû roäng chieàu daøi bit)
- Thöïc hieän gioáng nhö soá khoâng daáu.
- 6+ 3
: 1 0 1 0 : 0 0 1 1
+
1 1 0 1- 3 :
- 2- 5
: 1 1 1 0 : 1 0 1 1
+
1 0 0 1- 7 :
+ 4+ 5
: 0 1 0 0 : 0 1 0 1
+
1 0 0 1- 7 : (Kq sai)
0 0 1 0 0 0 0 1 0 1 0 1 0 0 1 (Kq ñuùng): + 9
26
- 7+ 5
: 1 0 0 1 : 0 1 0 1
-
0 1 0 0+ 4 : (Kq sai)
1 1 0 0 1 0 0 1 0 1 1 0 1 0 0 (Kq ñuùng): - 12
- 6- 2
: 1 0 1 0 : 1 1 1 0
-
1 1 0 0- 4 :
+ 2- 5
: 0 0 1 0 : 1 0 1 1
-
0 1 1 1+ 7 :
14
27
Tröø vôùi soá buø_2:
613
: 0 1 1 0 : 1 1 0 1
-
1 0 0 1- 7 :
buø_2:0 1 1 0 0 0 1 1
+
* Tröø vôùi soá khoâng coù daáu
* Tröø vôùi soá coù daáu
- 6- 3
: 1 0 1 0 : 1 1 0 1
-
1 1 0 1- 3 :
buø_2:1 0 1 0 0 0 1 1
+
A – B = A + Buø_2 (B)
28
IV. Coäng tröø soá BCD:
A + B
S = A + BNeáu toång Si ≥ 10 hoaëc coù bit nhôù
Ci = 1, thì hieäu ñính Si : Si = Si + 6 vaø Si+1 = Si+1 + Ci
A - BD = A – B
= A + Buø_2(B)
(Keát quaû boû bit Cn)
Cn = 1: keát quaû laø soá döông
(A≥B)
Neáu Ci = 1 thì khoâng hieäu ñínhNeáu Ci = 0 thì hieäu ñính Di :
Di = Di + 10
Cn = 0: keát quaû laø soá aâm (A<<<<B)
Laáy buø keát quaû
Neáu Ci = 1 thì hieäu ñính Di :Di = Di + 6
Neáu Ci = 0 thì khoâng hieäu ñính
: 0 0 1 0 1 0 0 1: 0 1 0 1 0 1 0 1
2955+
84 :
0 1 1 1 1 1 1 00 1 1 0
1 0 0 0 0 1 0 0
: 0 0 1 0 1 0 0 0: 0 0 0 1 1 0 0 1
2819+
47 :
0 1 0 0 0 0 0 10 1 1 0
0 1 0 0 0 1 1 1
1
15
29
0 1 1 0
: 0 0 1 0 1 0 0 1: 0 1 0 1 0 1 0 1
-26 :
1 1 0 1 0 1 0 0
1 1 0 1 1 0 1 0
2955-
0 0 1 0 1 0 0 11 0 1 0 1 0 1 1
1
0 0 1 0 0 1 1 0
+
30
Giaûn ñoà xung (Waveform) cuûa tín hieäu soá:
Traïng thaùi logic cuûa tín hieäu soá (Digital Signal):
1
1
Chöông 2: ÑAÏI SOÁ BOOLE – COÅNG LOGICI. Caáu truùc ñaïi soá Boole:Laø caáu truùc ñaïi soá ñöôïc ñònh nghóa treân 1 taäp phaàn töû nhòphaân B = {0, 1} vaø caùc pheùp toaùn nhò phaân: AND (.), OR (+),NOT (’).
x y x . y (x AND y)0 00 11 01 1
000 1
x y x + y (x OR y)0 00 11 01 1
011 1
x x’ (NOT x, x )
0 1
10
2
1. Caùc tieân ñeà (Axioms):a. Tính kín (Closure Property)
b. Phaàn töû ñoàng nhaát (Identity Element):
x + 0 = 0 + x = x
x . 1 = 1 . x = x
c. Tính giao hoaùn (Commutative Property):
x + y = y + x
x . y = y . x
d. Tính phaân boá (Distributive Property):
x + ( y . z ) = ( x + y ) . ( x + z )
x . ( y + z ) = x . y + x . z
e. Phaàn töû buø (Complement Element):
* Thöù töï pheùp toaùn: theo thöù töï daáu ngoaëc (), NOT, AND, OR
x + x = 1 x . x = 0
2
3
2. Caùc ñònh lyù cô baûn (Basic Theorems):
b. Ñònh lyù 2: x + x = x x . x = x
c. Ñònh lyù 3: x + 1 = 1 x . 0 = 0
d. Ñònh lyù 4: ñònh lyù haáp thu (Absorption)x + x . y = x x . (x + y) = x
e. Ñònh lyù 5: ñònh lyù keát hôïp (Associative)x + (y + z) = (x + y) + z x . (y . z) = (x . y) . z
a. Ñònh lyù 1: x = x
f. Ñònh lyù 6: ñònh lyù De Morganx + y = x . y x . y = x + y
Môû roäng: x1 + x2 + .. + xn = x1 . x2 .. xnx1 . x2 .. xn = x1 + x2 + .. + xn
4
II. Haøm Boole (Boolean Function):1. Ñònh nghóa:
* Haøm Boole laø 1 bieåu thöùc ñöôïc taïo bôûi caùc bieán nhò phaân vaø caùc pheùp toaùn nhò phaân NOT, AND, OR.
* Vôùi giaù trò cho tröôùc cuûa caùc bieán, haøm Boole seõ coù giaù trò laø 0 hoaëc 1.
* Baûng giaù trò:
F (x, y, z) = x . y + x . y . z
x y z F
0 0 00 0 10 1 00 1 11 0 0 1 0 11 1 01 1 1
0
1
0
0
0
0
1
1
3
5
2. Buø cuûa 1 haøm:
- Söû duïng ñònh lyù De Morgan:
- Laáy bieåu thöùc ñoái ngaãu vaø laáy buø caùc bieán:* Tính ñoái ngaãu (Duality): Hai bieåu thöùc ñöôïc goïi laø ñoái
ngaãu cuûa nhau khi ta thay pheùp toaùn AND baèng OR, pheùp toaùn OR baèng AND, 0 thaønh 1 vaø 1 thaønh 0.
Buø caùc bieán:
F = x . y + x . y . z
F = x . y + x . y . z
= ( x . y ) . ( x . y . z )
F = ( x + y ) . ( x + y + z )
F = x . y + x . y . z
Laáy ñoái ngaãu: ( x + y ) . ( x + y + z )
F = ( x + y ) . ( x + y + z )
6
III. Daïng chính taéc vaø daïng chuaån cuûa haøm Boole:1. Caùc tích chuaån (minterm) vaø toång chuaån (Maxterm):
- Tích chuaån (minterm): mi (0 ≤ i ≤ 2n-1) laø caùc soá haïng tích (AND) cuûa n bieán maø haøm Boole phuï thuoäc vôùi quy öôùc bieán ñoù coù buø neáu noù laø 0 vaø khoâng buø neáu laø 1.
- Toång chuaån (Maxterm): Mi (0 ≤ i ≤ 2n-1) laø caùc soá haïng toång (OR) cuûa n bieán maø haøm Boole phuï thuoäc vôùi quy öôùc bieán ñoù coù buø neáu noù laø 1 vaø khoâng buø neáu laø 0.
x y z0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1
minterm MaxtermM0 = x + y + zm0 = x y z
m1 = x y z
m2 = x y z
m3 = x y z
m4 = x y z
m5 = x y z
m6 = x y z
m7 = x y z
M1 = x + y + z
M7 = x + y + z
M2 = x + y + z
M3 = x + y + z
M4 = x + y + z
M5 = x + y + z
M6 = x + y + z
mi = Mi
4
7
2. Daïng chính taéc (Canonical Form):a. Daïng chính taéc 1:
laø daïng toång cuûa caùc tích chuaån (minterm) laøm cho haøm Boole coù giaù trò 1
x y z F0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1
01100111
F(x, y, z) = + x y z
= m1 + m2 + m5 + m6 + m7
= ΣΣΣΣ m(1, 2, 5, 6, 7)
b. Daïng chính taéc 2:laø daïng tích cuûa caùc toång chuaån (Maxterm) laøm cho haøm Boole coù giaù trò 0
F(x, y, z) = (x + y + z)
= M0 . M3 . M4
= ΠΠΠΠ M(0, 3, 4)
= ΣΣΣΣ (1, 2, 5, 6, 7)
= ΠΠΠΠ (0, 3, 4)
x y z + x y z + x y z + x y z
(x + y + z) (x + y + z)
8
* Tröôøng hôïp haøm Boole tuøy ñònh (don’t care):Haøm Boole n bieán coù theå khoâng ñöôïc ñònh nghóa heáttaát caû 2n toå hôïp cuûa n bieán phuï thuoäc. Khi ñoù taïi caùctoå hôïp khoâng söû duïng naøy, haøm Boole seõ nhaän giaù tròtuøy ñònh (don’t care), nghóa laø haøm Boole coù theå nhaängiaù tri 0 hoaëc 1.
x y z F0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1
X110011X
F (x, y, z) = ΣΣΣΣ (1, 2, 5, 6) + d (0, 7)
= ΠΠΠΠ (3, 4) . D (0, 7)
5
9
3. Daïng chuaån (Standard Form):a. Daïng chuaån 1:
laø daïng toång caùc tích (S.O.P – Sum of Product)
F (x, y, z) = x y + z
* F (x, y, z) = x y + z
= m6 + m7 + m1 + m5 + m3
= ΣΣΣΣ (1, 3, 5, 6, 7)
* F (x, y, z) = x y + z
= (x + z) (y + z)
= M2 . M0 . M4
= ΠΠΠΠ (0, 2, 4)
= x y (z + z) + (x + x) (y + y) z
= x y z + x y z + x y z + x y z + x y z + x y z
= (x + y y + z) (x x + y + z)
= (x + y + z) (x + y + z) (x + y + z) (x + y + z)
10
= (x + y + z) (x + y + z)
(x + y + z)(x + y + z)(x + y + z)(x + y + z)
= x y z + x y z + x y z + x y z
b. Daïng chuaån 2:
laø daïng tích caùc toång (P.O.S – Product of Sum)
= m4 + m5 + m0
= ΣΣΣΣ (0, 4, 5)
= M3 . M1 . M7 . M6 . M2
= ΠΠΠΠ (1, 2, 3, 6, 7)
F (x, y, z) = (x + z) y
* F (x, y, z) = (x + z) y = x y + y z
= x y (z + z) + (x + x) y z
* F (x, y, z) = (x + z) y
= (x + y y + z) (x x + y + z z)
6
11
x
IV. Coång logic:1. Coång NOT:
xxx t
2. Coång AND:
x
yz = x.y
x
y
z
Vôùi coång AND coù nhieàu ngoõ vaøo, ngoõ ra seõ laø 1 neáu taát caû caùc ngoõ vaøo ñeàu laø 1
x y z
0 00 11 01 1
0001
12
3. Coång OR:
x y z
0 00 11 01 1
0111
x
yz = x+y x
y
Vôùi coång OR coù nhieàu ngoõ vaøo, ngoõ ra seõ laø 0 neáu taát caû caùc ngoõ vaøo ñeàu laø 0
z
4. Coång NAND:x
yz = x.y
x y z
0 00 11 01 1
1110
x
y
z
Vôùi coång NAND coù nhieàu ngoõ vaøo, ngoõ ra seõ laø 0 neáu taát caû caùc ngoõ vaøo ñeàu laø 1
7
13
5. Coång NOR:
x y z
0 00 11 01 1
1000
x
y
Vôùi coång NOR coù nhieàu ngoõ vaøo, ngoõ ra seõ laø 1 neáu taát caû caùc ngoõ vaøo ñeàu laø 0
z
x
yz = x+y
6. Coång XOR (Exclusive_OR):x
yz = x⊕⊕⊕⊕y
x y z
0 00 11 01 1
0110
x
y
z
Vôùi coång XOR coù nhieàu ngoõ vaøo, ngoõ ra seõ laø 1 neáu toång soá bit 1 ôû caùc ngoõ vaøo laø soá leû
z = x⊕⊕⊕⊕y = x y + x y = (x + y)(x + y)
14
7. Coång XNOR (Exclusive_NOR):
x y z
0 00 11 01 1
1001
x
y
z
Vôùi coång XNOR coù nhieàu ngoõ vaøo, ngoõ ra seõ laø 1 neáu toång soá bit 1 ôû caùc ngoõ vaøo laø soá chaün
x
yz = x⊕⊕⊕⊕y
z = x⊕⊕⊕⊕y = x y + x y = (x + y)(x + y)
8
15
V. Ruùt goïn haøm Boole:Ruùt goïn (toái thieåu hoùa) haøm Boole nghóa laø ñöa haøm Boole
veà daïng bieåu dieãn ñôn giaûn nhaát, sao cho:
- Bieåu thöùc coù chöùa ít nhaát caùc thöøa soá vaø moãi thöøa soá chöùa ít nhaát caùc bieán.
- Maïch logic thöïc hieän coù chöùa ít nhaát caùc vi maïch soá.
1. Phöông phaùp ñaïi soá:Duøng caùc ñònh lyù vaø tieân ñeà ñeå ruùt goïn haøm.F (A, B, C) = ΣΣΣΣ (2, 3, 5, 6, 7)
= ABC + ABC + ABC + ABC + ABC
= AB(C + C) + AC(B + B) + AB(C + C)
= AB + AC + AB
= (A + A)B + AC
= B + AC
16
AB
F0 1
0
1
2. Phöông phaùp bìa KARNAUGH:a. Caùch bieåu dieãn:
- Bìa K goàm caùc oâ vuoâng, moãi oâ vuoâng bieåu dieãn cho toå hôïp n bieán. Nhö vaäy bìa K cho n bieán seõ coù 2n oâ.
- Hai oâ ñöôïc goïi laø keà caän nhau khi toå hôïp bieán maø chuùng bieåu dieãn chæ khaùc nhau 1 bieán.
- Trong oâ seõ ghi giaù trò töông öùng cuûa haøm Boole taïi toå hôïp đoù. ÔÛû daïng chính taéc 1 thì ñöa caùc giaù trò 1 vaø X leân caùc oâ, khoâng ñöa caùc giaù trò 0. Ngöôïc laïi, daïng chính taéc 2 thì chæ ñöa giaù trò 0 vaø X.
* Bìa 2 bieán:
0
1
2
3
F (A, B) = ΣΣΣΣ (0, 2) + d(3) = ∏∏∏∏ (1) . D(3)
AB
F0 1
0
1
1 1
X
AB
F0 1
0
1 0 X
9
17
* Bìa 3 bieán:AB
C
F
0
1
00 01 11 100
1
2
3
6
7
4
5
ABC
F
0
1
00 01 11 10
F (A, B, C) = ΣΣΣΣ (2, 4, 7) + d(0, 1) = ∏∏∏∏ (3, 5, 6) . D(0, 1)
X
X
1
1
1
ABC
F
0
1
00 01 11 10X
X 0
0
0
18
* Bìa 4 bieán: ABCD
F
0000 01 11 10
01
11
10
0
1
4
5
8
9
3
2
7
6 1014
15
13
12
11
* Bìa 5 bieán:
30
31
29
28
BCDE
F
0000 01 11 10
01
11
10
10 0011 01A 0 1
0
1
4
5
8
9
3
2
7
6 1014
15
13
12
11
18
19
17
16
22
23
21
20
26
27
25
24
10
19
b. Ruùt goïn bìa Karnaugh:
- Lieân keát ñoâi: Khi lieân keát (OR) hai oâ coù giaù trò 1 (OÂ_1) keà caän vôùi nhau treân bìa K, ta seõ ñöôïc 1 soá haïng tích maát ñi 1 bieán so vôùi tích chuaån (bieán maát ñi laø bieán khaùc nhau giöõa 2 oâ). Hoaëc khi lieân keát (AND) hai oâ coù giaù trò 0 (OÂ_0) keà caän vôùi nhau treân bìa K, ta seõ ñöôïc 1 soá haïng toång maát ñi 1 bieán so vôùi toång chuaån (bieán maát ñi laø bieán khaùc nhau giöõa 2 oâ).
* Nguyeân taéc:
ABC
F
0
1
00 01 11 101 1
B C
ABC
F
0
1
00 01 11 100
0
A +B
20
- Lieân keát 4: Töông töï nhö lieân keát ñoâi khi lieân keát 4 OÂ_1 hoaëc 4 OÂ_ 0 keà caän vôùi nhau, ta seõ loaïi ñi ñöôïc 2 bieán (2 bieán khaùc nhau giöõa 4 oâ)
ABC
F
0
1
00 01 11 101
1
1
1
B
ABC
F
0
1
00 01 11 10
0 0 0 0
C
11
21
- Lieân keát 8: lieân keát 8 oâ keà caän vôùi nhau, ta seõ loaïi ñi ñöôïc 3 bieán (3 bieán khaùc nhau giöõa 8 oâ)
ABCD
F00 01 11 10
00
01
11
10
1 1 1
1 1 1
1
1
D
ABCD
F00 01 11 10
00
01
11
10
0
0
0
0
0
0 0
0
B
- Lieân keát 2k: khi ta lieân keát 2k OÂ_1 hoaëc 2k OÂ_0 keà caän vôùi nhau ta seõ loaïi ñi ñöôïc k bieán (k bieán khaùc nhau giöõa 2koâ)
22
* Caùc böôùc thöïc hieän ruùt goïn theo daïng S.O.P:- Bieåu dieãn caùc OÂ_1 leân bìa Karnaugh - Thöïc hieän caùc lieân keát coù theå coù sao cho caùc OÂ_1 ñöôïc lieân keát ít nhaát 1 laàn; moãi lieân keát cho ta 1 soá haïng tích. (Neáu OÂ_1 khoâng coù keà caän vôùi caùc OÂ_1 khaùc thì ta coù lieân keát 1: soá haïng tích chính baèng minterm cuûa oâ ñoù). - Bieåu thöùc ruùt goïn coù ñöôïc baèng caùch laáy toång (OR) cuûa caùc soá hạng tích lieân keát treân.
F(A, B, C) = ΣΣΣΣ (0, 1, 3, 5, 6)
ABC
F
0
1
00 01 11 101
1 1
1
1
A C
A BB C
A B C
= A B + A C + B C + A B C
12
23
* Caùc böôùc thöïc hieän ruùt goïn theo daïng P.O.S:- Bieåu dieãn caùc OÂ_0 leân bìa Karnaugh - Thöïc hieän caùc lieân keát coù theå coù sao cho caùc OÂ_0 ñöôïc lieân keát ít nhaát 1 laàn; moãi lieân keát cho ta 1 soá haïng tổng. - Bieåu thöùc ruùt goïn coù ñöôïc baèng caùch laáy tích (AND) cuûa caùc soá hạng tổng lieân keát treân.
F(A, B, C, D) = ΠΠΠΠ (0, 4, 8, 9, 12, 13, 15)
ABCD
F00 01 11 10
00
01
11
10
(C + D)(A + C)
(A + B + D)
00
0 0 00
0
= (C + D) (A + C) (A + B + D)
24
* Tröôøng hôïp ruùt goïn haøm Boole coù tuøy ñònh: thì ta coù theå coi caùc OÂ tuøy ñònh naøy laø OÂ_1 hoaëc OÂ_0 sao cho coù lôïi khi lieân keát (nghóa laø coù ñöôïc lieân keát nhieàu OÂ keà caän nhaát)
F(A, B, C, D) = ΣΣΣΣ (0, 4, 8, 10) + d (2, 12, 15)
1 1 1
X 1
X
X
ABCD
F00 01 11 10
00
01
11
10
C D
B D
= B D + C D
13
25
F(A, B, C, D) = ΠΠΠΠ (0, 2, 3, 4, 6, 10, 14) . D (8, 9, 11, 12, 13)
D
(B + C)
0 0 X
0 0
X
X
0
0
X
X
0
ABCD
F00 01 11 10
00
01
11
10
= D (B + C)
26
* Chuù yù:
- Öu tieân lieân keát cho caùc oâ chæ coù 1 kieåu lieân keát (phaûi laø lieân keát coù nhieàu oâ nhaát).
- Khi lieân keát phaûi ñaûm baûo coù chöùa ít nhaát 1 oâ chöa ñöôïc lieân keát laàn naøo.
- Ta coi caùc tuøy ñònh nhö laø nhöõng oâ ñaõ lieân keát roài.
- Coù theå coù nhieàu caùch lieân keát coù keát quaû töông ñöông nhau
Vd: Ruùt goïn caùc haømF1(A, B, C, D) = ΣΣΣΣ (1, 3, 5, 12, 13, 14, 15) + d (7, 8, 9)
F2(A, B, C, D) = ΠΠΠΠ (1, 3, 7, 11, 15) . D(0, 2, 5)
F1(A, B, C, D, E) = ΣΣΣΣ (1, 3, 5, 7, 12, 14, 29, 31)+ d (13, 15, 17, 19, 20, 21, 22, 23)
F2(A, B, C, D, E) = ΠΠΠΠ (0, 8, 12, 13, 16, 18, 28, 30). D(2, 6, 10, 14, 15, 24, 26)
14
27
VI. Thöïc hieän haøm Boole baèng coång logic:
1. Caáu truùc coång AND _ OR:
Caáu truùc AND_OR laø sô ñoà logic thöïc hieän cho haøm Boole bieåu dieãn theo daïng toång caùc tích (S.O.P)
F(A, B, C, D) = A B D + C D
F(A, B, C, D)
A
B
C
D
AND 0R
28
2. Caáu truùc coång OR _ AND :
Caáu truùc OR_AND laø sô ñoà logic thöïc hieän cho haøm Boole bieåu dieãn theo daïng tích caùc toång (P.O.S).
F(A, B, C, D) = (A + D) (B + C+ D)
OR AND
F(A, B, C, D)
A
B
C
D
15
29
3. Caáu truùc coång AND _ OR _ INVERTER (AOI):
Caáu truùc AOI laø sô ñoà logic thöïc hieän cho haøm Boole bieåu dieãn theo daïng buø (INVERTER = NOT) cuûa toång caùc tích.
F(A, B, C, D) = A D + B C
A
B
C
D
F(A, B, C, D)
AND NOR
30
4. Caáu truùc coång OR _ AND _ INVERTER (OAI):
Caáu truùc OAI laø sô ñoà logic thöïc hieän cho haøm Boole bieåu dieãn theo daïng buø cuûa tích caùc toång.
A
B
C
D
F(A, B, C, D)
OR NAND
F(A, B, C, D) = (A + D) (B + C)
16
31
5. Caáu truùc toaøn coång NAND:Caáu truùc NAND laø sô ñoà logic thöïc hieän cho haøm Boole coù
bieåu thöùc laø daïng buø cuûa 1 soá haïng tích. - Duøng ñònh lyù De-Morgan ñeå bieán ñoåi soá haïng toång thaønh tích. - Coång NOT cuõng ñöôïc thay theá baèng coång NAND
F(A, B, C, D) = A B D + C D
= A B D . C D
A
B
C
D
F(A, B, C, D)
NANDNAND
32
F(A, B, C, D) = (A + D) (B + C+ D)
= A D . B C D
A
B
C
D
F(A, B, C, D)
17
33
- Trong thöïc teá ngöôøi ta chæ söû duïng 1 loaïi coång NAND 2 ngoõ vaøo; khi ñoù ta phaûi bieán ñoåi bieåu thöùc sao cho chæ coù daïng buø treân 1 soá haïng tích chæ coù 2 bieán
F (A, B, C, D) = A B D . C D
= A B D . C D
A
B
C
D
F(A, B, C, D)
34
6. Caáu truùc toaøn coång NOR:Caáu truùc NOR laø sô ñoà logic thöïc hieän cho haøm Boole coù
bieåu thöùc laø daïng buø cuûa 1 soá haïng toång. - Duøng ñònh lyù De-Morgan ñeå bieán ñoåi soá haïng tích thaønh toång - Coång NOT cuõng ñöôïc thay theá baèng coång NOR
F(A, B, C, D) = (A + D) (B + C+ D)
= (A + D) + (B + C+ D)
A
B
C
D
F(A, B, C, D)
NOR NOR
18
35
F(A, B, C, D) = A B D + C D
= (A + B + D) + (C + D)
A
B
C
D
F(A, B, C, D)
36
F(A, B, C, D) = (A + D) (B + C) (C + D)
= (A + D) + (B + C) + (C + D)
= (A + D) + (B + C) + (C + D)
A
B
C
D
F(A, B, C, D)
1
1
Chöông 3: HEÄ TOÅ HÔÏPI. Giôùi thieäu – Caùch thieát keá heä toå hôïp:
Maïch logic ñöôïc chia laøm 2 loaïi:- Heä toå hôïp (Combinational Circuit)- Heä tuaàn töï (Sequential Circuit).
Heä toå hôïp laø maïch maø caùc ngoõ ra chæ phuï thuoäc vaøo giaù trò cuûa caùc ngoõ vaøo. Moïi söï thay ñoåi cuûa ngoõ vaøo seõ laøm ngoõ ra thay ñoåi theo.
Ngoõ vaøo (INPUT)
Ngoõ ra (OUTPUT)
COÅNG LOGIC
2
* Caùc böôùc thieát keá:
- Phaùt bieåu baøi toaùn.
- Xaùc ñònh soá bieán ngoõ vaøo vaø soá bieán ngoõ ra.
- Thaønh laäp baûng giaù trò chæ roõ moái quan heä giöõa ngoõ vaøo vaø ngoõ ra.
- Tìm bieåu thöùc ruùt goïn cuûa töøng ngoõ ra phuï thuoäc vaøo caùc bieán ngoõ vaøo. - Thöïc hieän sô ñoà logic.
Ngoõ vaøo
Xn-1 … X1 X0
Ngoõ ra
Ym-1 … Y1 Y0
0 … 0 0
1 … 1 1
2
3
Vd: Thieát keá heä toå hôïp coù 3 ngoõ vaøo X, Y, Z; vaø 2 ngoõ ra F, G. - Ngoõ ra F laø 1 neáu nhö 3 ngoõ vaøo coù soá bit 1 nhieàu hôn soá bit
0; ngöôïc laïi F = 0. - Ngoõ ra G laø 1 neáu nhö giaù trò nhò phaân cuûa 3 ngoõ vaøo lôùn
hôn 1 vaø nhoû hôn 6; ngöôïc laïi G = 0.
X Y Z F G0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1
000 101 11
001 111 00
XYZ
F
0
1
00 01 11 10
1 1
Y Z
1
1
X Z
X Y
F = X Y + Y Z + X Z
XYZ
G
0
1
00 01 11 10
11
11
X Y X Y
G = X Y + X Y = X ⊕⊕⊕⊕ Y
4
F
F = X Y + Y Z + X Z G = X Y + X Y = X ⊕⊕⊕⊕ Y
X
Y
Z
G
3
5
Trường hợp heä toå hôïp khoâng söû duïng taát caû 2n toå hôïp cuûa ngoõ vaøo,thì taïi caùc toå hôïp khoâng söû duïng ñoù ngoõ ra coù giaù trò tuøy ñònh.
Vd: Thieát keá heä toå hôïp coù ngoõ vaøo bieåu
dieãn cho 1 soá maõ BCD. Neáu giaù trò ngoõ vaøo
nhoû hôn 3 thì ngoõ ra coù giaù trò baèng bình
phöông giaù trò ngoõ vaøo; ngöôïc laïi giaù trò
ngoõ ra baèng giaù trò ngoõ vaøo tröø ñi 3.
A B C D0 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1
F2 F1 F0
X X XX X X X X X X X X X X X X X X
0 0 0 0 0 1 1 0 00 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0
F2 = A + B C D + B C D
F1 = A D + B C D + B C D
F0 = A D + B D + A B C D
6
II. Boä coäng - tröø nhò phaân:1. Boä coäng (Adder):a. Boä coäng baùn phaàn (Half Adder – H.A):Boä coäng baùn phaàn laø heä toå hôïp coù nhieäm vuï thöïc hieän
pheùp coäng soá hoïc x + y (x, y laø 2 bit nhò phaân ngoõ vaøo); heä coù 2 ngoõ ra: bit toång S (Sum) vaø bit nhôù C (Carry).
x y C S0 00 11 01 1
0 00 10 11 0
S = x y + x y = x ⊕⊕⊕⊕ y C = x y
x
yS
C
x
y
S
CH.A
4
7
b. Boä coäng toaøn phaàn (Full Adder – F.A):Boä coäng toaøn phaàn thực hiện pheùp coäng soá hoïc 3 bit x + y + z
(z bieåu dieãn cho bit nhôù töø vị trí coù troïng soá nhoû hôn gôûi tôùi)
x
y
S
C
F.A
z
x y z C S0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1
0 00 10 11 00 11 01 01 1
xyz
S
0
1
00 01 11 10
1
1
1
1
S = x y z + x y z + x y z + x y z
xyz
C
0
1
00 01 11 10
11 1
1
C = x y + x z + y z
8
S = x y z + x y z + x y z + x y z
= z (x y + x y) + z (x y + x y)
= z (x ⊕⊕⊕⊕ y) + z (x ⊕⊕⊕⊕ y)
S = z ⊕⊕⊕⊕ (x ⊕⊕⊕⊕ y)
C = x y + x z + y z
= x y + x y z + x y z + x y z
= x y (1 + z) + z (x y + x y)
C = x y + z (x ⊕⊕⊕⊕ y)
x
y
z
S
C
5
9
2. Boä tröø (Subtractor):a. Boä tröø baùn phaàn (Half Subtractor – H.S):Boä tröø baùn phaàn coù nhieäm vuï thöïc hieän pheùp tröø soá
hoïc x - y (x, y laø 2 bit nhò phaân ngoõ vaøo); heä coù 2 ngoõ ra: bit hieäu D (Difference) vaø bit möôïn B (Borrow).
x
y
D
BH.S
x y B D0 00 11 01 1
0 01 10 10 0
D = x y + x y = x ⊕⊕⊕⊕ y B = x y
x
yD
B
10
b. Boä tröø toaøn phaàn (Full Subtractor – F.S):Boä tröø toaøn phaàn thực hiện pheùp tröø soá hoïc 3 bit x - y - z
(z bieåu dieãn cho bit möôïn töø ví trò coù troïng soá nhoû hôn)
x
y
D
B
F.S
z
x y z B D0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1
0 01 11 11 00 10 00 01 1
xyz
D
0
1
00 01 11 10
1
1
1
1
xyz
B
0
1
00 01 11 10
11 1
1
S = x y z + x y z + x y z + x y z
C = x y + x z + y z
S = z ⊕⊕⊕⊕ (x ⊕⊕⊕⊕ y)
C = x y + z (x ⊕⊕⊕⊕ y)
6
11
74283
3. Boä coäng/tröø nhò phaân song song:a. Boä coäng nhò phaân:
M: M3 M2 M1 M0
N: N3 N2 N1 N0
S0S1S2S3
C1C2
+
C3
C4
x y
zC
S
F.Ax y
zC
S
F.Ax y
zC
S
F.Ax y
zC
S
F.A
M0 N0M1 N1M2 N2M3 N3
S0
C0
= 0
C1 C2 C3
S1 S2 S3 C4
12
b. Boä tröø nhò phaân:- Söû duïng caùc boä tröø toaøn phaàn F.S- Thöïc hieän baèng pheùp coäng vôùi buø 2 cuûa soá tröø
M – N = M + Buø_2(N) = M + Buø_1(N) + 1
M0 N0M1 N1M2 N2M3 N3
C0
= 1
x y
zC
S
F.Ax y
zC
S
F.Ax y
zC
S
F.Ax y
zC
S
F.A C1 C2 C3
S0 S1 S2 S3 C4
Keát quaû: - C4 = 1 keát quaû laø soá döông- C4 = 0 keát quaû laø soá aâm
7
13
c. Boä coäng/tröø nhò phaân:
M0 N0M1 N1M2 N2M3 N3
C0
x y
zC
S
F.Ax y
zC
S
F.Ax y
zC
S
F.Ax y
zC
S
F.A C1 C2 C3
S0 S1 S2 S3 C4
Pheùp toaùn C0 yi0 NiCOÄNG
TRÖØ 1 Ni
T = 0: Coäng
T = 1: Tröø
Ngoõ vaøo ñieàu khieån
C0 = T
yi = T⊕⊕⊕⊕ Ni
T
14
III. Heä chuyeån maõ (Code Conversion):
- Heä chuyeån maõ laø heä toå hôïp coù nhieäm vuï laøm cho 2 heä thoáng töông thích vôùi nhau, maëc duø moãi heä thoáng duøng maõ nhò phaân khaùc nhau.
- Heä chuyeån maõ coù ngoõ vaøo cung caáp caùc toå hôïp maõ nhò phaân A vaø caùc ngoõ ra taïo ra caùc toå hôïp maõ nhò phaân B. Nhö vaäy, ngoõ vaøo vaø ngoõ ra phaûi coù soá löôïng töø maõ baèng nhau.
Maõ nhò phaân B
Heä chuyeån maõ
Maõ nhò phaân A
8
15
Vd: Thieát keá heä chuyeån maõ töø maõ BCD thaønh maõ BCD quaù 3.
A B C D0 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1
W X Y Z
X X X XX X X X X X X X X X X X X X X XX X X X
0 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 0
W = A + B (C + D)
X = B ⊕⊕⊕⊕ (C + D)
Y = C ⊕⊕⊕⊕ D
Z = D
A
B
C
D
W
X
Z
Y
16
IV. Boä giaûi maõ (DECODER):1. Giôùi thieäu:
- Boä giaûi maõ laø heä chuyeån maõ coù nhieäm vuï chuyeån töø maõ nhò phaân cô baûn n bit ôû ngoõ vaøo thaønh maõ nhò phaân 1 trong m ôû ngoõ ra.
Maõ 1 trong m
X0
X1
Xn-1
Maõ nhò phaân
Y0
Y1
Ym-1
m = 2n
- Coù 2 daïng: ngoõ ra tích cöïc cao (möùc 1) vaø ngoõ ra tích cöïcthaáp (möùc 0).
- Với giaù trị i của tổ hợp nhị phaân ở ngoõ vaøo, thì ngoõ ra Yi sẽtích cực vaø caùc ngoõ ra coøn lại sẽ khoâng tích cực.
9
17
a. Boä giaûi maõ ngoõ ra tích cöïc cao:
X0 (LSB)
X1
Y0
Y1
Y2
Y3
X1 X0 Y3 Y2 Y1 Y0
0 00 11 01 1
0 0 0 10 0 1 00 1 0 01 0 0 0
Y0 = X1 X0 = m0
Y1 = X1 X0 = m1
Y2 = X1 X0 = m2
Y3 = X1 X0 = m3
X0
X1
Y0
Y1
Y2
Y3Ngoõ ra: Yi = mi
(i = 0, 1, .., 2n-1)
18
b. Boä giaûi maõ ngoõ ra tích cöïc thaáp:
X1 X0 Y3 Y2 Y1 Y0
0 00 11 01 1
1 1 1 01 1 0 11 0 1 10 1 1 1
X0
X1
Ngoõ ra: Yi = Mi
(i = 0, 1, .., 2n-1)
X0 (LSB)
X1
Y0
Y1
Y2
Y3
Y0 = X1 + X0 = M0 = m0
Y1 = X1 + X0 = M1 = m1
Y2 = X1 + X0 = M2 = m2
Y3 = X1 + X0 = M3 = m3
Y0
Y1
Y2
Y3
10
19
c. Boä giaûi maõ coù ngoõ vaøo cho pheùp:- Ngoaøi caùc ngoõ vaøo döõ lieäu, boä giaûi maõ coù theå coù 1 hay
nhieàu ngoõ vaøo cho pheùp. - Khi caùc ngoõ vaøo cho pheùp ôû traïng thaùi tích cöïc thì maïch
giaûi maõ môùi ñöôïc hoaït ñoäng. Ngöôïc laïi, maïch giaûi maõ seõ khoâng hoaït ñoäng; khi ñoù caùc ngoõ ra ñeàu ôû traïng thaùi khoâng tích cöïc.
Y0
Y1
Y2
Y3
X0 (LSB)
X1
EN
EN X1 X0 Y3 Y2 Y1 Y0
0 X X1 0 01 0 11 1 01 1 1
0 0 0 00 0 0 10 0 1 00 1 0 01 0 0 0
X0
X1
Y0
Y1
Y2
Y3
EN
20
2. IC giaûi maõ:
a. IC 74139: goàm 2 boä giaûi maõ 2 sang 4 ngoõ ra tích cöïc thaáp
1Y0
1Y1
1Y2
1Y3
1A (LSB)
1B
1G
2Y0
2Y1
2Y2
2Y3
2A (LSB)
2B
2G
1
2
3
15
14
13
4
5
6
7
12
11
10
9
G B A Y3 Y2 Y1 Y0
1 X X0 0 00 0 10 1 00 1 1
1 1 1 11 1 1 01 1 0 11 0 1 10 1 1 1
11
21
b. IC 74138: boä giaûi maõ 3 sang 8 ngoõ ra tích cöïc thaáp
Y0
Y1
Y2
Y3
A (LSB)
B
C
Y4
Y5
Y6
Y7
G1
G2A
G2B
1
2
3
4
6
59
12
11
10
7
15
14
13
G1 G2A G2B C B A Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
0 X X X X XX 1 X X X XX X 1 X X X1 0 0 0 0 01 0 0 0 0 11 0 0 0 1 01 0 0 0 1 11 0 0 1 0 01 0 0 1 0 11 0 0 1 1 01 0 0 1 1 1
1 1 1 1 1 1 1 11 1 1 1 1 1 1 1 1 1 1 1 1 1 1 11 1 1 1 1 1 1 01 1 1 1 1 1 0 11 1 1 1 1 0 1 1 1 1 1 1 0 1 1 11 1 1 0 1 1 1 11 1 0 1 1 1 1 11 0 1 1 1 1 1 10 1 1 1 1 1 1 1
22
3. Söû duïng boä giaûi maõ thöïc hieän haøm Boole:Ngoõ ra cuûa boä giaûi maõ laø minterm (ngoõ ra tích cöïc cao)
hoaëc maxterm (ngoõ ra tích cöïc thaáp) cuûa n bieán ngoõ vaøo. Do ñoù, ta coù theå söû duïng boä giaûi maõ thöïc hieän haøm Boole theo daïng chính taéc.
z
y
x
0
1
0
F1 (x, y, z) = ∑∑∑∑ (2, 5, 7)
= m2 + m5 + m7
= M2 + M5 + M7
= M2 M5 M7
F2 (x, y, z) = ∏∏∏∏ (0, 1, 4)
= M0 M1 M4
F1
F2
Y0
Y1
Y2
Y3
A (LSB)
B
C
Y4
Y5
Y6
Y7
G1
G2A
G2B
74138
12
23
V. Boä maõ hoùa (ENCODER):1. Giôùi thieäu:- Encoder laø heä chuyeån maõ thöïc hieän hoaït ñoäng ngöôïc laïi vôùidecoder. Nghóa laø encoder coù m ngoõ vaøo theo maõ nhò phaân 1trong m vaø n ngoõ ra theo maõ nhò phaân cô baûn (vôùi m ≤ 2n).
- Vôùi ngoõ vaøo Ii ñöôïc tích cöïc thì ngoõ ra chính laø toå hôïp giaù trònhò phaân i töông öùng.
I0I1I2I3
(LSB)Z0
Z1
I3 I2 I1 I0 Z1 Z0
0 00 11 01 1
0 0 0 10 0 1 00 1 0 01 0 0 0
Z1 = I3 + I2
Z0 = I3 + I1
Z1
Z0
I3
I2
I1
24
* Boä maõ hoùa coù öu tieân (Priority Encoder):Boä maõ hoùa coù öu tieân laø maïch maõ hoùa sao cho neáu coù nhieàu
hôn 1 ngoõ vaøo cuøng tích cöïc thì ngoõ ra seõ laø giaù trò nhò phaâncuûa ngoõ vaøo coù öu tieân cao nhaát.
I0I1I2I3
(LSB)Z0
Z1
V
I3 I2 I1 I0 Z1 Z0 VX X 0 0 0 10 1 11 0 11 1 1
0 0 0 00 0 0 10 0 1 X0 1 X X1 X X X
Z1 = I3 + I2
Z0 = I3 + I2 I1
V = I3 + I2 + I1 + I0
I3
I2
I1
I0
Z1
Z0
V
Thöù töï öu tieân: I3 >>>> I2 >>>> I1 >>>> I0
13
25
2. IC maõ hoùa öu tieân 8 →→→→3 (74148):
EI I7 I6 I5 I4 I3 I2 I1 I0 A2 A1 A0 GS EO
1 X X X X X X X X0 0 X X X X X X X0 1 0 X X X X X X0 1 1 0 X X X X X0 1 1 1 0 X X X X0 1 1 1 1 0 X X X0 1 1 1 1 1 0 X X0 1 1 1 1 1 1 0 X0 1 1 1 1 1 1 1 00 1 1 1 1 1 1 1 1
1 1 1 1 10 0 0 0 10 0 1 0 10 1 0 0 10 1 1 0 11 0 0 0 11 0 1 0 11 1 0 0 11 1 1 0 11 1 1 1 0
EI
I7I6I5I4I3I2I1I0
1
5
3
1214
9
A2A1
(LSB)A0
GSEO
7
6
15
4
2
13
11
10
26
VI. Boä doàn keânh (Multiplexer - MUX):1. Giôùi thieäu:- MUX 2n →→→→1 laø heä toå hôïp coù nhiều ngoõ vaøo nhöng chæ coù 1 ngoõ ra. Ngoõ vaøo goàm 2 nhoùm: m ngoõ vaøo döõ lieäu (data input) vaø n ngoõ vaøo löïa choïn (select input).
- Vôùi 1 giaù trò i cuûa toå hôïp nhò phaân caùc ngoõ vaøo löïa choïn, ngoõ vaøo döõ lieäu Di seõ ñöôïc choïn ñöa ñeán ngoõ ra. (m = 2n)
D0D1:Dm-1
S0(LSB)S1:Sn-1
Y
Ngoõ vaøo döõ lieäu(Data Input)
Ngoõ vaøo löïa choïn(Select Input)
14
27
* Boä MUX 4 →→→→ 1:
D0D1D2D3
S0(LSB)S1
Y
S1 S0 Y0 00 1 1 01 1
D0D1D2D3
= m0 D0 + m1 D1 + m2 D2 + m3 D3
= ∑∑∑∑ mi Di (i = 0, 1, 2, 3)
Y = S1 S0 D0 + S1 S0 D1 + S1 S0 D2 + S1 S0 D3
S1
S0
D0
D1
D2
D3
Y
Toång quaùt: Y = ∑∑∑∑ mi Di (vôùi i = 0, 1, .., 2n-1)
28
2. IC doàn keânh:a. 74LS153: goàm 2 boä MUX 4 →→→→1
1G1C01C11C21C3
A(LSB)B
1Y
2G2C02C12C22C3
2Y
14
15
10
11
12
13
2
1
6
5
4
3
7
9
G B A Y1 X X0 0 00 0 1 0 1 00 1 1
0C0C1C2C3
15
29
b. 74151: boä MUX 8 →→→→1
ENA(LSB)BC
YD0D1D2D3D4D5D6D7
Y
15
14
13
12
9
4
3
2
1
5
6
11
10
7
EN C B A Y1 X X X0 0 0 00 0 0 1 0 0 1 00 0 1 10 1 0 00 1 0 1 0 1 1 00 1 1 1
0D0D1D2D3D4D5D6D7
30
3. Söû duïng boä MUX thöïc hieän haøm Boole:
a. Boä MUX 2n thöïc hieän haøm Boole n bieán:
ENA(LSB)BC
YD0D1D2D3D4D5D6D7
Y
F(x, y, z) = ∑∑∑∑ (0, 1, 4, 7)
= m0 + m1 + m4 + m7
= m0 1 + m1 1 + m2 0 + m3 0 + m4 1 + m5 0 + m6 0 + m7 1
Y = ∑∑∑∑ mi Di
= m0D0 + m1D1 + m2D2 + m3D3
+ m4D4 + m5D5 + m6D6 + m7D7
D0 = D1 = D4 = D7 = 1
D2 = D3 = D5 = D6 = 0
zyx
0
1
0
F
16
31
b. Boä MUX 2n thöïc hieän haøm Boole n+1 bieán:
F(x, y, z) = ∑∑∑∑ (0, 1, 4, 7)
= x y z + x y z + x y z + x y z
= x y .1 + x y .0 + x y .z + x y .z
Y = m0D0 + m1D1 + m2D2 + m3D3
D0 = 1; D1 = 0; D2 = z; D3 = z
1G1C01C11C21C3
A(LSB)B
1Y
2G2C02C12C22C3
2Y
yx
010
zF
= m0 .1 + m1 .0 + m2 .z + m3 .z
x y z F0 0 00 0 1 0 1 00 1 11 0 01 0 1 1 1 01 1 1
11001001
D0 = 1
D1 = 0
D3 = z
D2 = z
32
VII. Boä phaân keânh (DEMUX):1. Giôùi thieäu:- Boä DEMUX 1→→→→2n coù chöùc naêng thöïc hieän hoaït ñoäng ngöôïclaïi vôùi boä MUX. Maïch coù 1 ngoõ vaøo döõ lieäu, n ngoõ vaøo löïachoïn vaø 2n ngoõ ra.
- Vôùi 1 giaù trò i cuûa toå hôïp nhò phaân caùc ngoõ vaøo löïa choïn, ngoõ vaøo döõ lieäu D seõ ñöôïc ñöa ñeán ngoõ ra Yi.
Y0Y1:
Ym-1
S0(LSB)S1:Sn-1
DNgoõ vaøo döõ lieäu(Data Input)
Ngoõ vaøo löïa choïn(Select Input)
Ngoõ vaøo döõ lieäu(Data Input) Ngoõ ra
17
33
* Boä DEMUX 1 →→→→ 4:
Y0
Y1
Y2
Y3
D
S0 (LSB)
S1
S1 S0 Y3 Y2 Y1 Y0
0 00 11 01 1
0 0 0 D0 0 D 00 D 0 0D 0 0 0
Y0 = S1 S0 D = m0 D
Y1 = S1 S0 D = m1 D
Y2 = S1 S0 D = m2 D
Y3 = S1 S0 D = m3 D
Y0
Y1
Y2
Y3
S1
S0
D
34
B A 1G 1C 1Y0 1Y1 1Y2 1Y3
2. IC phaân keânh 74LS155: goàm 2 boä phaân keânh 1 →→→→ 4
1Y0
1Y1
1Y2
1Y3A (LSB)
B 2Y0
2Y1
2Y2
2Y3
2G
2C
1
2
15
13
3
7
6
5
4
12
10
11
9
14
1G
1CX XX X0 00 11 01 1
1 XX 00 10 10 10 1
1 1 1 11 1 1 10 1 1 11 0 1 11 1 0 11 1 1 0
B A 2G 2C 2Y0 2Y1 2Y2 2Y3
X XX X0 00 11 01 1
1 XX 10 00 00 00 0
1 1 1 11 1 1 10 1 1 11 0 1 11 1 0 11 1 1 0
18
35
VIII. Boä so saùnh đoä lôùn (Comparator):1. Giôùi thieäu:- Boä so saùnh laø heä toå hôïp coù nhieäm vuï so saùnh 2 soá nhị phaân khoâng daáu A vaø B (moãi soá n bit). - Boä so saùnh coù 3 ngoõ ra (A>B), (A=B) vaø (A<B); chæ coù 1 ngoõ ra tích cöïc theo keát quaû so saùnh.
* Boä so saùnh 3 bit:
A: A2 A1 A0B: B2 B1 B0
Söû duïng bieán trung gian:xi = Ai ⊕⊕⊕⊕ Bi (i = 0, 1, 2)
(A = B) = x2 x1 xo
(A > B) = A2 B2 + x2 A1 B1 +x2x1 A0 B0
(A < B) = A2 B2 + x2 A1 B1 +x2x1 A0 B0
(A>B)
(A=B)
(A<B)
A
B
= (A=B) + (A>B)
36
x0
x1
x2
(A=B)
B0
A0
B1
A1
B2
A2
(A>B)
(A<B)
19
37
2. IC so saùnh 74LS85:
3
4
9
ALTBINAEQBINAGTBIN
B0B1B2B3
10
12
13
15
11
14
1
7
5
A0A1A2A3 ALTBOUT
AEQBOUTAGTBOUT
6
2
AGTBOUT = (A>B) + (A=B)AGTBIN
AEQBOUT = (A=B) AEQBIN
ALTBOUT = (A<B) + (A=B)ALTBIN
1
NguyenTrongLuat 1
Chöông 4: HEÄ TUAÀN TÖÏI. Giôùi thieäu:
Ngoõ vaøo (INPUT)
Ngoõ ra (OUTPUT)
COÅNG LOGIC
Heä tuaàn töï laø heä maø ngoõ ra khoâng chæ phuï thuoäc vaøo caùc ngoõ vaøo maø coøn phuï thuoäc vaøo 1 soá ngoõ ra ñöôïc hoài tieáp trôû thaønh ngoõ vaøo thoâng qua phaàn töû nhôù.
PHAÀN TÖÛ NHÔÙ
Phaàn töû nhôù thöôøng söû duïng laø Flip_Flop.
Heä tuaàn töï ñöôïc chia thaønh 2 loaïi: - Heä tuaàn töï ñoàng boä (Synchronous)- Heä tuaàn töï baát ñoàng boä (Asynchronous)
II. Maïch Choát (Latch) vaø Flip-Flop (FF):
Flip_Flop: laø maïch tuaàn töï maø noù thöôøng laáy maãu caùc ngoõ vaøo vaø laøm thay ñoåi caùc ngoõ ra taïi nhöõng thôøi ñieåm xaùc ñònh bôûi xung clock.
Latch (choát): laø maïch tuaàn töï maø noù lieân tuïc xem xeùt caùcngoõ vaøo vaø laøm thay ñoåi caùc ngoõ ra baát cöù thôøi ñieåm naøokhoâng phuï thuoäc vaøo xung clock.
Caùc maïch choát vaø FF coù 2 ngoõ ra Q vaø Q. Hai ngoõ ra naøycoù giaù trò logic laø buø cuûa nhau.
NguyenTrongLuat 2
2
1. Caùc maïch choát:
a. Choát SR: coù 2 loaïi
* Coång NOR:
R(reset)
QS(set)
Q
0 00 11 01 1
0 11 00 0
Q+ Q+S R
Q Q
Baûng hoaït ñoäng:
Caám söû duïng
Q+ laø traïng thaùi keá tieáp cuûa Q
Kyù hieäu:
S
R
Q
Q
NguyenTrongLuat 3
* Coång NAND:Baûng hoaït ñoäng:
Kyù hieäu:
R(reset)
Q
S(set) Q
Q+ Q+S R
0 00 11 01 1
1 00 1
1 1 Caám söû duïng
Q Q
S
R
Q
Q
NguyenTrongLuat 4
3
b. Choát SR coù ngoõ vaøo cho pheùp:
0 X X1 0 01 0 11 1 01 1 1
0 11 0 1 1
R(reset)
Q
S(set) Q
C(enable)
Q+ Q+C S R
Q QQ Q
Kyù hieäu choát SR coù ngoõ vaøo cho pheùp tích cöïc cao:
S
C
R
Q
Q
Baûng hoaït ñoäng:
NguyenTrongLuat 5
* Khaûo saùt giaûn ñoà xung:
S
R
C
Q(Cho Q ban ñaàu laø 0)
Kyù hieäu choát SR coù ngoõ vaøo cho pheùp tích cöïc thaáp:
S
C
R
Q
Q
1 X X0 0 00 0 10 1 00 1 1
0 11 0 1 1
Q QQ QQ+ Q+C S R
NguyenTrongLuat 6
4
c. Choát D:
Kyù hieäu choát D:
D
C
Q
Q
Baûng hoaït ñoäng:
C D Q+ Q+
0 X Q Q
Q
D(set) Q
C(enable)
1 01 1
0 11 0
NguyenTrongLuat 7
2. Flip_Flop (FF):Traïng thaùi keá tieáp cuûa ngoõ ra FF seõ thay ñoåi theo ngoõ vaøo vaø
traïng thaùi tröôùc ñoù cuûa ngoõ ra taïi thôøi ñieåm thay ñoåi cuûa xungclock (caïnh leân hoaëc caïnh xuoáng)
* Baûng ñaëc tính vaø phöông trình ñaëc tính:Bieåu dieãn moái quan heä cuûa ngoõ ra keá tieáp Q+ phuï thuoäc vaøo
caùc ngoõ vaøo vaø traïng thaùi ngoõ ra hieän taïi Q.* Baûng kích thích:Bieåu dieãn giaù trò cuûa caùc ngoõ vaøo caàn phaûi coù khi ta caàn ngoõ
ra chuyeån töø traïng thaùi hieän taïi Q sang traïng thaùi keá tieáp Q+.
X
CK
Q
Q
X
CK
Q
Q
Xung clock caïnh leân Xung clock caïnh xuoáng
NguyenTrongLuat 8
5
a. Flip_Flop D (D-FF):
D
CK
Q
Q
Baûng hoaït ñoäng:
CK D Q+ Q+
0 11 0
0, 1, X Khoâng thay ñoåi
01
D
CK
Q
Q
CK D Q+ Q+
0 11 0
Khoâng thay ñoåi0, 1, X01
NguyenTrongLuat 9
* Khaûo saùt giaûn ñoà xung:
CK
D
Q(Cho Q ban ñaàu laø 0)
* Baûng ñaëc tính vaø phöông trình ñaëc tính:
D Q Q+
0 00 11 01 1
0011
Q+ = D
* Baûng kích thích:
Q Q+ D0 00 11 01 1
0101
D = Q+
NguyenTrongLuat 10
6
T Q+
Q
b. Flip_Flop T (T-FF):
T
CK
Q
Q
Baûng hoaït ñoäng:T
CK
Q
QQ0 1
* Baûng ñaëc tính vaø phöông trình ñaëc tính:
T Q Q+
0 00 11 01 1
0110
Q+ = T ⊕⊕⊕⊕ Q
* Baûng kích thích:
Q Q+ T0 00 11 01 1
0110
T = Q ⊕⊕⊕⊕ Q+
NguyenTrongLuat 11
c. Flip_Flop SR (SR-FF):
S
CK
R
Q
Q
S
CK
R
Q
Q
* Baûng hoaït ñoäng:
S R Q Q+
0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1
0
* Baûng ñaëc tính vaø pt ñaëc tính:
1
S R Q+
0 00 11 01 1
Q01X
0011XX
Q+ = S + R QS R = 0
* Baûng kích thích:
Q Q+ S R0 00 11 01 1
0 X1 00 1X 0
NguyenTrongLuat 12
7
d. Flip_Flop JK (JK-FF):
J
CK
K
Q
Q
J
CK
K
Q
Q
* Baûng hoaït ñoäng:
J K Q+
0 00 11 01 1
Q01Q
J K Q Q+
0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1
0
* Baûng ñaëc tính vaø pt ñaëc tính:
1001110
* Baûng kích thích:
Q Q+ J K0 00 11 01 1
0 X1 XX 1X 0
Q+ = J Q + K Q
NguyenTrongLuat 13
e. Caùc ngoõ vaøo baát ñoàng boä:
- Caùc ngoõ vaøo naøy seõ laøm thay ñoåi giaù trò ngoõ ra töùc thôøi,baát chaáp xung clock.- Coù 2 ngoõ vaøo vaøo baát ñoàng boä: Preset (Pr) vaø Clear (Cl).
+ Khi ngoõ vaøo Preset tích cöïc thì ngoõ ra Q ñöôïc set leân 1.+ Khi ngoõ vaøo Clear tích cöïc thì ngoõ ra Q ñöôïc xoùa veà 0.
J
CK
K
Q
Q
Pr
Cl
J
CK
K
Q
Q
Pr
Cl
+ Khi ngoõ vaøo Preset vaø Clear khoâng tích cöïc thì FF môùi hoaït ñoäng.
NguyenTrongLuat 14
8
III. Boä ñeám (COUNTER):1. Giôùi thieäu:
- Boä ñeám laø heä tuaàn töï coù 1 ngoõ vaøo xung clock vaø nhieàu ngoõ ra. Ngoõ ra cuûa boä ñeám chính laø ngoõ ra cuûa caùc Flip-Flop caáu thaønh boä ñeám.
- Noäi dung cuûa boä ñeám taïi 1 thôøi ñieåm goïi laø traïng thaùi cuûa boä ñeám. Khi coù xung clock vaøo boä ñeám seõ chuyeån traïng thaùi töø 1 traïng thaùi hieän taïi chuyeån sang 1 traïng thaùi keá tieáp. Cöù tieáp tuïc nhö vaäy seõ taïo ra 1 voøng ñeám kheùp kín.
- Giaûn ñoà traïng thaùi cuûa boä ñeám:Bieåu dieãn caùc traïng thaùi coù
trong voøng ñeám vaø höôùng chuyeån traïng thaùi cuûa boä ñeám.
000Q2Q1Q0
100
011010
110-Modulo cuûa boä ñeám:Laø soá caùc traïng thaùi khaùc nhau
trong voøng ñeám: m ≤ 2n
NguyenTrongLuat 15
* Boä ñeám ñöôïc chia thaønh 2 loaïi:- Boä ñeám noái tieáp (boä ñeám baát ñoàng boä): laø boä ñeám maø
ngoõ ra cuûa FF tröôùc seõ laø ngoõ vaøo xung clock cho FF sau.- Boä ñeám song song (boä ñeám ñoàng boä): laø boä ñeám maø
ngoõ vaøo xung clock cuûa caùc FF ñöôïc noái chung vôùi nhau.2. Boä ñeám noái tieáp (Asynchronous Counter): :
- Boä ñeám noái tieáp thöïc hieän caùc voøng ñeám leân hoaëc xuoáng:+ Ñeám leân (Count Up): noäi dung boä ñeám taêng theâm 1 khi
coù xung clock.+ Ñeám xuoáng (Count Down): noäi dung boä ñeám giaûm ñi 1
khi coù xung clock.- Boä ñeám ñöôïc taïo töø caùc FF ñeám 2, gheùp noái tieáp vôùi nhau.
J
CK
K
Q
Q
1
1
T
CK
Q
Q
1
NguyenTrongLuat 16
9
a. Boä ñeám ñaày ñuû (m = 2n):
CK
T
CK
Q
Q
1 T
CK
Q
Q
1 T
CK
Q
Q
1
Q2(MSB)Q1Q0(LSB)
CKQ0
Q1
Q2
(LSB)
(MSB)
Khaûo saùt giaûn ñoà xung: ñaây laø boä ñeám leân (Count Up)
* Gheùp Cki+1 = Qi
NguyenTrongLuat 17
J
CK
K
Q
Q
1
1
J
CK
K
Q
Q
1
1
J
CK
K
Q
Q
1
1
Q2(MSB)Q0(LSB) Q1
CK
Khaûo saùt giaûn ñoà xung:
CK
Q0
Q1
Q2
(LSB)
(MSB)
laø boä ñeám xuoáng (Count Down)
NguyenTrongLuat 18
10
* Gheùp Cki+1 = Qi
CK
T
CK
Q
Q
1 T
CK
Q
Q
1 T
CK
Q
Q
1
Q2(MSB)Q1Q0(LSB)
Q2(MSB)Q0(LSB) Q1
CK
J
CK
K
Q
Q
1
1
J
CK
K
Q
Q
1
1
J
CK
K
Q
Q
1
1
+ Boä ñeám xuoáng (Count Down):
+ Boä ñeám leân (Count Up):
NguyenTrongLuat 19
b. Boä ñeám khoâng ñaày ñuû (m<<<< 2n):- Boä ñeám khoâng ñaày ñuû thöïc hieän döïa vaøo boä ñeám ñaày ñuû.
Ta caàn xaùc ñònh traïng thaùi keá tieáp khoâng mong muoán cuûa voøng ñeám khoâng ñaày ñuû. - Duøng traïng thaùi naøy ñeå taïo ra tín hieäu taùc ñoäng tích cöïc vaøo
caùc ngoõ vaøo baát ñoàng boä Preset hoaëc Clear ñeå ñöa boä ñeám trôû veà traïng thaùi ban ñaàu (thường gọi laø traïng thaùi reset). Vd: Söû duïng T-FF coù xung clock caïnh xuoáng vaø ngoõ vaøo Preset,
Clear tích cöïc cao; thieát keá boä ñeám leân coù m = 5 vaø bắt ñaàu từ giaù trò 0.
Q2 Q1 Q0
0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1
000001XX
Ta gọi Z laø tín hiệu để reset bộ đếm. Z
Q2Q1Q0
Z
0
1
00 01 11 10
1
X
X
Z = Q2 Q0NguyenTrongLuat 20
11
CK
Q2(MSB)Q1Q0(LSB)
T
Ck
Q
Q
1 Pr
Cl
T
Ck
Q
Q
1 Pr
Cl
T
Ck
Q
Q
1 Pr
Cl
Z
0 0 0
Khaûo saùt giaûn ñoà xung:
CKQ0
Q1
Q2
(LSB)
(MSB)NguyenTrongLuat 21
Vd: Söû duïng JK-FF coù xung clock caïnh xuoáng vaø ngoõ vaøo Pr, Cl tích cöïc thaáp; thieát keá boä ñeám xuoáng coù m = 5 vaø bắt ñaàu từ giaù trò 2.
Q2 Q1 Q00 1 00 0 10 0 01 1 11 1 01 0 1
Tín hiệu reset: Z = Q2 Q1 (tích cöïc thaáp)
Q2(MSB)Q0(LSB) Q1
CK
J
CK
K
Q
Q
1
1
Pr
Cl
J
CK
K
Q
Q
1
1
Pr
Cl
J
CK
K
Q
Q
1
1
Pr
Cl
1 1
1
NguyenTrongLuat 22
12
CLR CK QD QC QB QA
IC 74393: 2 boä ñeám leân đầy đủ 4 bit
1QA
1QB
1QC
(MSB) 1QD
3
4
5
6
1CK
1CLR
1
2
2QA
2QB
2QC
(MSB) 2QD
11
10
9
8
2CK
2CLR
13
12
1 X0 0, 1, 0
0 0 0 0NO CHANGECOUNT UP
NguyenTrongLuat 23
Reset/Set INPUTMR1 MR2 MS1 MS2
OUTPUTQD QC QB QA
1 1 0 X 1 1 X 0X X 1 11 X 1 XX 1 X 11 X X 1X 1 1 X
IC 7490: goàm 2 boä ñeám - boä ñeám 2 vaø boä ñeám 5 (ñeám leân)
QA12
11
9
CKA
QB
QC
(MSB)QD8
MR1
MR2
2
14
1 CKB
MS1
MS2
3
6
7
5
VCC
GND
10
0 0 0 00 0 0 01 0 0 1
Counting
NguyenTrongLuat 24
13
3. Boä ñeám song song (Synchronous Counter): :- Laø boä ñeám maø caùc FF ñeàu söû duïng chung nguoàn xung clock;
khi coù xung clock vaøo thì taát caû caùc ngoõ ra FF ñeàu thay ñoåi. - Khi thieát keá boä ñeám, chæ quan taâm ñeán traïng thaùi hieän taïi
vaø traïng thaùi keá tieáp cuûa FF, maø khoâng quan taâm ñeán daïng xung clock (caïnh leân hoaëc caïnh xuoáng).
- Coù theå thieát keá boä ñeám coù voøng ñeám baát kyø.
Baûng haøm kích thích:
D = Q+
* D-FF:
T = Q ⊕⊕⊕⊕ Q+
* T-FF:
* SR-FFS RQ Q+ J K
0 00 11 01 1
0 X1 00 1X 0
* JK-FF
0 X1 XX 1X 0
NguyenTrongLuat 25
* Caùc böôùc thieát keá:- Töø phaùt bieåu baøi toaùn xaùc ñònh soá FF söû duïng vaø daõy ñeám.- Laäp baûng chuyeån traïng thaùi chæ roõ moái quan heä giöõa traïngthaùi hieän taïi vaø traïng thaùi keá tieáp (döïa vaøo daõy ñeám).
T/t hieän taïiQn-1 … Q1 Q0
T/t keá tieápQ+
n-1 … Q+1 Q+
0
0 … 0 0
1 … 1 1
- Tìm caùc giaù trò ngoõ vaøo FF caàn phaûi coù töø giaù trò hieän taïi Qi vaøkeá tieáp Q+
i cuûa töøng FF (döïa vaøo baûng kích thích cuûa FF).
Caùc ngoõ vaøo FF
- Tìm bieåu thöùc ruùt goïn cuûa moãi ngoõ vaøo FF phuï thuoäc vaøo caùcbieán traïng thaùi hieän taïi.- Thöïc hieän sô ñoà logic.
NguyenTrongLuat 26
14
a. Boä ñeám ñaày ñuû (m = 2n):
Vd: Söû duïng T-FF kích theo caïnh leân, thieát keá boä ñeám coù daõy ñeám sau: Q2Q1Q0 : 010, 101, 110, 001, 000, 111, 100, 011, 010, …
T/t hieän taïiQ2 Q1 Q0
T/t keá tieápQ+
2 Q+1 Q+
0
Caùc ngoõ vaøoT2 T1 T0
0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1
1 1 10 0 01 0 10 1 00 1 11 1 00 0 11 0 0
10101010
10101111
11111111
Q2Q1Q0
T2
0
1
00 01 11 101 1 1 1
Q2Q1Q0
T1
0
1
00 01 11 101 1 1 1
1 1
T2 = Q0 T1 = Q0 + Q2 T0 = 1
NguyenTrongLuat 27
T2 = Q0 T1 = Q0 + Q2 T0 = 1
CK
Q0(LSB)Q1Q2(MSB)
T2
CK2
Q2
Q
2
T1
CK1
Q1
Q
1
T0
CK0
Q0
Q
0
1
NguyenTrongLuat 28
15
0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1
b. Boä ñeám khoâng ñaày ñuû (m < 2n):Caùc traïng thaùi coù trong voøng ñeám seõ thieát keá nhö boä ñeám
ñaày ñuû; coøn caùc traïng thaùi dö khoâng coù trong voøng ñeám seõgiaûi quyeát theo 2 caùch sau:
* Caùch 1: Caùc traïng thaùi dö coù traïng thaùi keá tieáp laø tuøy ñònh. Khi thieát keá caàn khôûi ñoäng giaù trò ban ñaàu cho boä ñeám; giaù trò naøy phaûi laø 1 trong nhöõng traïng thaùi coù trong voøng ñeám.
T/t hieän taïiQ2 Q1 Q0
T/t keá tieápQ+
2 Q+1 Q+
0
Vd: Thieát keá boä ñeám duøng D-FF caïnh leân, coù ngoõ vaøo Pr vaø Cl tích cöïc cao, coù giaûn ñoà traïng thaùi sau:
000Q2Q1Q0
100
011010
110
1 0 0X X X1 1 00 1 00 1 1X X X0 0 0X X X
D2 D1 D0NguyenTrongLuat 29
D2 = Q2 Q0 D1 = Q2 ⊕⊕⊕⊕ Q1 D0 = Q2 Q1
CK
Q0(LSB)Q1Q2(MSB)
D2
Ck2
Q2
Q
2
Pr
Cl
D1
Ck1
Q1
Q
1
Pr
Cl
D0
Ck0
Q0
Q
0
Pr
Cl
RS
0
0 0
NguyenTrongLuat 30
16
* Caùch 2: Cho caùc traïng thaùi dö khoâng coù voøng ñeám coù traïng thaùi keá tieáp laø 1 trong nhöõng traïng thaùi coù trong voøng ñeám.
000Q2Q1Q0
100
011010
110101
001
111
T/t hieän taïiQ2 Q1 Q0
T/t keá tieápQ+
2 Q+1 Q+
0
Caùc ngoõ vaøoT2 T1 T0
0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1
1 0 01 1 01 1 00 1 00 1 11 0 00 0 01 0 0
11101010
01001011
01011101
T2 = Q0 + Q2 Q1
T1 = Q2 ⊕⊕⊕⊕ (Q1 Q0)
T0 = Q0 + Q2 Q1
NguyenTrongLuat 31
* Phaân tích boä ñeám song song:- Töø sô ñoà logic cuûa boä ñeám xaùc ñònh haøm kích thích (bieåu
thöùc cuûa caùc ngoõ vaøo cuûa töøng FF phuï thuoäc vaøo caùc ngoõ ra Qi)
- Laäp baûng traïng thaùi: töø traïng thaùi hieän taïi Qi vaø giaù tròngoõ vaøo ta xaùc ñònh ñöôïc traïng thaùi keá tieáp cuûa FF Q+
i.
- Töø baûng chuyeån traïng thaùi xaùc ñònh ñöôïc giaûn ñoà traïng thaùi hoaëc khaûo saùt giaûn ñoà xung cuûa boä ñeám.
QA
QA
QA
CK
JA
CK
KA1
QB QC
QB
QB
JB
CK
KB
QC
QC
JC
CK
KC1
NguyenTrongLuat 32
17
JA = QB QC
KA = 1
JB = QA QC
KB = QA + QC
JC = QA
KC = 1
T/t hieän taïiQA QB QC
Caùc ngoõ vaøoJA KA JB KB JC KC
T/t keá tieápQ+
A Q+B Q+
C0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1
00010001
11111111
01010000
01011111
11110000
11111111
00010000
01100000
10100000
000QAQBQC
001
010011
100
101110
111
NguyenTrongLuat 33
IC 74193: boä ñeám leân/xuoáng ñoàng boä 4 bit
CLR LOAD UP DOWN MODE
QA
QB
QC
(MSB) QD
CO
BO
3
2
6
7
13
12
A
B
C
D
15
1
10
9
LOAD
CLR
UP
DOWN
11
14
5
4
RESET (Asyn.) PRESET (Asyn.)No changeCOUNT UPCOUNT DOWN
CO (Carry Out) = QDQCQBQAUP
BO (Borrow Out) = QDQCQBQADOWN
1 X X X0 0 X X0 1 1 10 1 10 1 1
NguyenTrongLuat 34
18
NguyenTrongLuat 35
IV. Thanh ghi dòch (Shift Register):Thanh ghi dòch laø heä tuaàn töï coù khaû naêng löu tröõ vaø dòch
chuyeån döõ lieäu.
NguyenTrongLuat 36
19
1. Thanh ghi dòch nhaäp noái tieáp - xuaát noái tieáp (SISO):
D
Ck
Q
Q
D
Ck
Q
Q
D
Ck
Q
QCK
SERIN SEROUT
2. Thanh ghi dòch nhaäp noái tieáp – xuaát song song (SIPO):
D
Ck
Q
Q
D
Ck
Q
Q
D
Ck
Q
QCK
SERIN
1Q 2Q nQ
NguyenTrongLuat 37
38
3. Thanh ghi dòch nhaäp song song - xuaát noái tieáp (PISO):
D
Ck
Q
Q
SERIN
D
Ck
Q
Q
D
Ck
Q
Q
X1
X0S
Y
X1
X0S
Y
X1
X0S
Y1D
2D
nD
CLOCK
SHIFT / LOAD
SEROUT
20
39
4. Thanh ghi dòch nhaäp song song - xuaát song song (PIPO):
D
Ck
Q
Q
SERIN
D
Ck
Q
Q
D
Ck
Q
Q
X1
X0S
Y
X1
X0S
Y
X1
X0S
Y1D
2D
nD
CLOCK
SHIFT / LOAD
1Q
2Q
nQ
InputsCLR CLK A B
OutputsQA QB … QH
IC 74164: SIPO – Thanh ghi dịch nối tiếp thaønh song song
0 0 0
QA0 QB0 QH0
1 QAn QGn
0 QAn QGn
0 QAn QGn
QA
QB
QC
QD
QE
QF
QG
QH
3
4
5
6
12
13
A
B
1
2
CLR
CLK
9
8
10
11
0 X X X
1 0 X X
1 1 1
1 0 X
1 X 0
NguyenTrongLuat 40
21
NguyenTrongLuat 41
InputsSH/LD CLKINH CLK SER A …
H
OutputQA QB … QH
IC 74165: PISO – Thanh ghi dịch song song thaønh nối tiếp
a b h
QA0 QB0 QH0
1 QAn QGn
0 QAn QGn
QA0 QB0 QH0
0 X X X a … h
1 0 0 X X
1 0 1 X
1 0 0 X
1 1 X X X
QH
QH
ABCDEFGH 9
SH/LDCLK INHCLKSER
1
2
15
10
11
12
13
14
3
4
5
6
7
NguyenTrongLuat 42
22
NguyenTrongLuat 43
VI. Boä ñeám thanh ghi dòch (Shift Register Counter):1. Boä ñeám voøng (Ring Counter):
Q2
D2
Ck
Q2
Q
2
D1
Ck
Q1
Q
1
D0
Ck
Q0
Q
0
CK
Q1 Q0
ClCl
Pr
RS
CK
Q2
Q1
Q0
Clock Q2 Q1 Q0
1 1 0 02 0 1 03 0 0 1
NguyenTrongLuat 44
23
2. Boä ñeám voøng xoaén (Twisted-ring Counter): boä ñeám JohnsonQ2
D2
Ck
Q2
Q
2
D1
Ck
Q1
Q
1
D0
Ck
Q0
Q
0
CK
Q1 Q0
ClClCl
RS
CK
Q2
Q1
Q0
Clock Q2 Q1 Q0
1 0 0 02 1 0 03 1 1 04 1 1 15 0 1 16 0 0 1
NguyenTrongLuat 45
VI. Phaân tích Heä tuaàn töï:Heä tuaàn töï ñöôïc chia thaønh 2 loïai tuøy thuoäc vaøo tính
chaát cuûa ngoõ ra.
X1
X2
Xn
Z1
Z2
Zm
Q+1 D1
D2
Dk
Q+2
Q+k
Q1
Q2
Qk
HEÄ TOÅ HÔÏP
NGOÕ RANGOÕ VAØO
Clock
1. Kieåu MEALY:
Traïng thaùi keá tieáp = F (traïng thaùi hieän taïi Qi vaø caùc ngoõ vaøo Xj)Giaù trò ngoõ ra = G (traïng thaùi hieän taïi Qi vaø caùc ngoõ vaøo Xj)
NguyenTrongLuat 46
24
DA = X QA + X QB
Z = X (QA + QB)
DB = X QA
DA
CK
QA
QA
X
Z
DB
CK
QB
QB
CK
* P/trình ngoõ ra:
* P/t ngoõ vaøo FF:
NguyenTrongLuat 47
DA = X QA + X QB
Z = X (QA + QB)
DB = X QA
Baûng traïng thaùi: Ngoõ vaøoX
T/t hieän taïiQA QB
Ngoõ raZ
T/t keá tieápQ+
A Q+B
00000111
0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1
00001100
01110000
T/t hieän taïiQA QB
Tt keá tieáp (Q+A Q+
B)X = 0 X = 1
Ngoõ ra (Z)X = 0 X = 1
0 0 0 0 0 1 0 0 0 1 0 0 1 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 0 1 0
= Q+A
= Q+B
NguyenTrongLuat 48
25
T/t hieän taïiQA QB
Tt keá tieáp (Q+A Q+
B)X = 0 X = 1
Ngoõ ra (Z)X = 0 X = 1
0 0 0 0 0 1 0 0 0 1 0 0 1 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 0 1 0
ABCD
Giaûn ñoà traïng thaùi (state graph):
00 01
10 11
0/0X/Z =1/0
0/1
1/00/1
1/0
0/1
1/0
AAAA
BDCC
A B
C D
0/01/0
0/1
1/00/1
1/0
0/1
1/0NguyenTrongLuat 49
2. Kieåu MOORE:
X1
X2
Xn
Z1
Z2
Zm
Q+1 D1
D2
Dk
Q+2
Q+k
Q1
Q2
Qk
HEÄ TOÅ HÔÏPCHO NGOÕ VAØO
Clock
Q1
Q2
Qk
HEÄ TOÅ HÔÏPCHO NGOÕ RA
Traïng thaùi keá tieáp = F (traïng thaùi hieän taïi Qi vaø caùc ngoõ vaøo Xj)Giaù trò ngoõ ra = G (traïng thaùi hieän taïi Qi)
NguyenTrongLuat 50
26
X1
Z
CK
J
CK
K
Q
Q
X2Z = Q
K = X1 X2
J = X 1 ⊕⊕⊕⊕ X2
Ngoõ vaøoX1 X2
TTHTQ
Ngoõ raZ
Ngoõ vaøo FFJ K
TTKTQ +
0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1
10101010
11000011
11111100
10000011
NguyenTrongLuat 51
TTHTQ
T/t keá tieáp (Q+)X1X2 = 0 0 0 1 1 0 1 1
Ngoõ ra (Z)
01
1
0
0
0
0
0
1
1
1
0
X1X2 =
01, 10
00, 11
01
10
00, 01, 10
11
NguyenTrongLuat 52
27
VII. Thiết kế Heä tuaàn töï:
* Caùc böôùc thieát keá:
- Töø phaùt bieåu baøi toaùn thaønh laäp graph traïng thaùi hoaëc baûng chuyeån traïng thaùi
- Ruùt goïn traïng thaùi
- Gaùn traïng thaùi.
- Choïn FF (D.FF, T.FF, JK.FF) vaø thieát keá phaàn toå hôïp ñeå taïo ra ngoõ ra vaø traïng thaùi keá (coång logic, ROM, PLA, PAL).
NguyenTrongLuat 53
Ví duï: Moät heä tuaàn töï coù 1 ngoõ vaøo X vaø 1 ngoõ ra Z. Ngoõ raseõ laø 1 neáu ngoõ vaøo nhaän ñöôïc chuoãi vaøo lieân tieáp 101.
* Kieåu MEALY:
TT hieän taïi
TT keá tieáp Ngoõ ra (Z)X = 0 X = 1 X = 0 X = 1
S0 S0 0S1 0S1 S2 0S2
S1 0S0 0S1 1
1. Thaønh laäp graph traïng thaùi hoaëc baûng chuyeån traïng thaùi:
X = 0 1 1 0 0 1 0 1 0 1 1 0 0Z = 0 0 0 0 0 0 0 1 0 1 0 0 0
NguyenTrongLuat 54
28
Kieåu MOORE:
TT hieän taïi
TT keá tieáp Ngoõ ra(Z)X = 0 X = 1
S0 0S0 S1S1 0S2S2 0
S1S0 S3
S3 1S2 S1
Ví duï: Moät heä tuaàn töï coù 1 ngoõ vaøo X vaø 1 ngoõ ra Z. Ngoõ raseõ laø 1 neáu ngoõ vaøo nhaän ñöôïc chuoãi vaøo lieân tieáp 101.
X = 0 1 1 0 0 1 0 1 0 1 1 0 0Z = 0 0 0 0 0 0 0 1 0 1 0 0 0
NguyenTrongLuat 55
2. Ruùt goïn traïng thaùi:
- Vôùi m traïng thaùi ta söû duïng n FF: 2n-1 < m ≤ 2n
- Traïng thaùi töông ñöông:
Hai traïng thaùi töông ñöông laø 2 traïng thaùi maø khi cuøng giaù trò vaøo maø chuùng coù caùc giaù trò ra gioáng nhau vaø caùc traïng thaùi keá tieáp maø chuùng chuyeån tôùi töông ñöông nhau.
PS NS OUTPUTX = 0 X = 1 X = 0 X = 1
A C D 0 1B C D 0 1
NguyenTrongLuat 56
29
Ví duï: Ruùt goïn baûng traïng thaùi sau
Ta có: S3 ≡≡≡≡ S5 và S4 ≡≡≡≡ S6
⇒⇒⇒⇒ S1 ≡≡≡≡ S2
TTHT TTKT Ngoõ ra (Z)
X = 0 X = 1 X = 0 X = 1
S0S1S2S3S4S5S6
S1S3S5S0S0S0S0
S2S4S6S0S0S0S0
0000101
0000000
S3 S4
S1
TTHT TTKT Ngoõ ra (Z)
X = 0 X = 1 X = 0 X = 1
S0S1S3S4
S1S3S0S0
S1S4S0S0
0001
0000
Baûng ruùt goïn:
NguyenTrongLuat 57
* PP ruùt goïn baèng baûng keùo theo (Implication Table)- Thaønh laäp baûng keùo theo cuûa baûng coù n traïng thaùi: coù n-1 coät vaø n-1 haøng. Moãi oâ vuoâng laø caëp traïng thaùi caàn xeùt töông ñöông.
S0 S1 S2 S3 S4
S1
S2
S3
S4
S5
- Töø baûng traïng thaùi tìm caùc traïng thaùi coù ngoõ ra gioáng nhau laäp thaønh nhoùm coù theå töông ñöông.- Taïi moãi oâ vuoâng cuûa 2 traïng thaùi khoâng cuøng nhoùm thì seõ khoâng töông ñöông ⇒⇒⇒⇒ gaïch cheùo oâ vuoâng.
- Taïi moãi oâ vuoâng cuûa 2 traïng thaùi cuøng nhoùm thì ta ghi ñieàu kieän traïng thaùi keá tieáp caàn xeùt töông ñöông.- Kieåm tra caùc ñieàu kieän trong caùc oâ vuoâng: gaïch cheùo caùc oâ khoâng thoûa ñieàu kieän. Caùc oâ coøn laïi khoâng bò gaïch cheùo laø keát quaû töông ñöông.
S0-S4S2-S3
NguyenTrongLuat 58
30
PS NS ZX=0 X=1
A D C 0B F H 0C E D 1D A E 0E C A 1F F B 1G B H 0H C G 1
A B C D E F G
B
C
D
E
F
G
H
(A, B, D, G)(C, E, F, H)
D - F
C - H
C - E
B - D
C - H
A - F
E - H
B - F
A - D
E - F
B - D
C - E
D - G
A - B
E - H
C - F
A - B
A - GC - F
B - G
A
C A
* PP ruùt goïn baèng baûng keùo theo (Implication Table)
Theo ngoõ ra: ta coù 2 nhoùm
Ta ñöôïc: (A, D)(C, E)
NguyenTrongLuat 59
3. Gaùn traïng thaùi:
4. Choïn FF vaø thieát keá phaàn toå hôïp:
Ngoõ vaøo Traïng thaùi hieän taïi Ngoõ ra Traïng thaùi keá tieáp
- Choïn FF (D-FF, T-FF, JK-FF) vaø maïch toå hôïp (coång logic, ROM, PLA, ..).
Moãi traïng thaùi ñöôïc gaùn baèng 1 toå hôïp caùc bieán traïng thaùiVí duï: Heä coù 3 traïng thaùi A, B, C
Ta caàn 2 bieán traïng thaùi Q1 vaø Q2 ñeå gaùn cho 3 traïng thaùi
Tthaùi A: Q1Q2 = 00B: Q1Q2 = 01C: Q1Q2 = 11
A -B C
Q1Q2
0 101
- Laäp baûng traïng thaùi
NguyenTrongLuat 60
31
TTHT TTKT Ngoõ ra (Z)
X = 0 X = 1 X = 0 X = 1S0S1S3S4
S1S3S0S4
S1S4S0S0
0001
0000
Ví duï: Thöïc hieän heä tuaàn töï sau
S0 S1
S4 S3
Q1Q2
0 101
Gaùn traïng thaùi
TTHT(Q1Q2)
TTKT (Q+1Q+
2) Ngoõ ra (Z)
X = 0 X = 1 X = 0 X = 1S0 : 00S1 : 10S3 : 11S4 : 01
10110001
10010000
0001
0000
NguyenTrongLuat 61
* Laäp baûng traïng thaùiNg.vaøo
XTTHTQ1 Q2
Ngoõ raZ
TTKTQ+
1 Q+2
0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1
TTHT(Q1Q2)
TTKT (Q+1Q+
2) Ngoõ ra (Z)X = 0 X = 1 X = 0 X = 1
S0 : 00S1 : 10S3 : 11S4 : 01
10110001
10010000
0001
0000
0 1 01 0 10 1 10 0 00 1 00 0 00 0 10 0 0
T.FFT1 T2
JK.FFJ1 K1 J2 K2
* Choïn FF:
10011011
00110111
1 X0 XX 0 X 11 X0 XX 1 X 1
0 XX 01 X X 10 XX 11 X X 1
NguyenTrongLuat 62
32
* Thöïc hieän baèng ROM vaø T.FF kích caïnh leân:
CK
X A2
A1
A0
D2
D1
D0
Z
T1 Q1
T2 Q2
23 x 3 (bit)
X Q1 Q2A2 A1 A0
Z T1 T2D2 D1 D0
0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1
0 1 01 0 00 0 10 1 10 1 00 0 10 1 10 1 1
Baûng naïp ROM
NguyenTrongLuat 63
* Thöïc hieän baèng coång logic vaø JK.FF kích caïnh xuoáng:
Töø baûng traïng thaùi, ruùt goïn:Z = X Q1 Q2
J1 = Q2
J2 = Q1
K2 = X + Q1
K1 = X + Q2
J1
K1
Q1
Q1
J2
K2
Q2
Q2
X
Z
CKNguyenTrongLuat 64
33
* Thöïc hieän baèng PLA vaø JK.FF kích caïnh leân:
X Q1 Q2 Z J1 K1 J2 K2
0 0 1
Baûng naïp PLA
CK
X
Q1
Q2
Z
J1
J2
Z
J1 Q1
K1
K2
K1
J2 Q2
K2
X
Z = X Q1 Q2 J1 = Q2 J2 = Q1 K2 = X + Q1 K1 = X + Q2
1 0 0 0 0- - 0 0 1 0 0 0
1 - - 0 0 1 0 1
- - 1 0 0 1 0 0- 1 - 0 0 0 1 1
NguyenTrongLuat 65
Vd: Thieát keá boä (chuyeån) ñoåi maõ töø BCD sang BCD quaù 3.Ngoõ vaøo vaø ra laø noái tieáp vôùi LSB ñi tröôùc.
X: INPUT (BCD) Z: OUTPUT (BCD+3)0 0 0 0 0 0 1 10 0 0 1 0 1 0 00 0 1 0 0 1 0 10 0 1 1 0 1 1 00 1 0 0 0 1 1 10 1 0 1 1 0 0 00 1 1 0 1 0 0 10 1 1 1 1 0 1 01 0 0 0 1 0 1 11 0 0 1 1 1 0 0
t0 t0t1 t1t2 t2t3 t3
NguyenTrongLuat 66
34
Thôøiñieåm
Chuoãi vaøo nhaän ñöôïc(LSB ñöôïc nhaän ñaàu tieân)
T/ thaùihieän taïi
T/thaùi keá Giaù trò ra (Z)X = 0 1 X = 0 1
t0 Reset A B 1C 0
B0
C1t1
D 1E 0
F 0G 1
D0 0
E0 1
F1 0
G1 1
t2
H
H0 0 0
0
I
I0 0 1
1
J
J0 1 0
1
K
K0 1 1
1
L
L1 0 0
1
M
M1 0 1
0
N
N1 1 0
0
P
P1 1 1
0
t3
A 0
A 0
A 0
A 0
A 0
A 1
A 1
A 1
A 1
A 1
- -- -- -- -- -- -
M
M
H
H
H
H
EE
NguyenTrongLuat 67
* Baûng traïng thaùi ñöôïc ruùt goïn cuûa boä chuyeån ñoåi maõ
Thôøi gian Traïng thaùihieän taïi
Traïng thaùi keáX=0 1
Giaù trò ra (Z)X=0 1
t0 A B C 1 0t1 B
CD EE E
1 00 1
t2 DE
H HH M
0 11 0
t3 HM
A AA -
0 11 -
NguyenTrongLuat 68
35
36
37
- Heä tuaàn töï coøn ñöôïc goïi laø maùy traïng thaùi thuaät toaùn (ASM - algorithmic state machine) hay ñôn giaûn hôn laø maùy traïng thaùi (SM - state machine), goïi taét laø SM.
IIX. LÖU ÑOÀ MAÙY TRAÏNG THAÙI:
- Löu ñoà SM ñöôïc taïo bôûi caùc khoái SM; moãi khoái SM moâ taû hoaït ñoäng cuûa heä trong 1 traïng thaùi.
- Moät khoái SM bao goàm moät Hoäp traïng thaùi (state box),caùc Hoäp quyeát ñònh (decision box) vaø caùc Hoäp xuaát theo ñieàu kieän (conditional ouput box).
Hoäp traïng thaùi
ÑIEÀU KIEÄN 10
Hoäp quyeát ñònh Hoäp xuaát theo ñkieänNguyenTrongLuat 74
38
ÑIEÀU KIEÄN10
STeân traïng thaùi xxx Maõ traïng thaùi
Lieät keâ bieán ra coù giaù trò 1 (bieán Moore)
Lieät keâ bieán ra coù giaù trò 1 theo ñieàu kieän (bieán Mealy)
Ñöôøng vaøo cuûa khoái SM
Caùc ñöôøng ra ñeán caùc khoái SM khaùcMoät khoái SM coù chính xaùc moät ñöôøng vaøo vaø moät hoaëc nhieàu ñöôøng ra.
NguyenTrongLuat 75
Z1, Z2
S1
X1
X3Z3, Z4
X2Z5
10
10
10
1 2 3 n
- Moät ñöôøng daãn ñi qua khoái SM töø ngoõ vaøo ñeán ngoõ ra ñöôïc goïi laø ñöôøng daãn lieân keát (link path).
NguyenTrongLuat 76
39
- Khoái SM coù theå ñöôïc bieåu dieãn baèng nhieàu daïng khaùc nhau.
- Moät löu ñoà SM coù theå bieåu dieãn moät heä toå hôïp khi chæ coù
moät traïng thaùi vaø khoâng coù söï thay ñoåi traïng thaùi xaûy ra.
Z1 = A + A’BC = A + BC
NguyenTrongLuat 78
40
- Ta phaûi tuaân theo moät soá qui taéc khi xaây döïng moät khoái SM.
* Khoâng cho pheùp coù ñöôøng hoài tieáp noäi trong moät khoái SM.
* Vôùi moïi keát hôïp caùc bieán vaøo hôïp leä phaûi coù chính xaùc moät ñöôøng ra ñöôïc ñònh nghóa. Ñieàu naøy laø caàn thieát vì moãi toå hôïp vaøo ñöôïc cho pheùp phaûi daãn ñeán moät traïng thaùi keá duy nhaát.
NguyenTrongLuat 79
S0Za
S1Zb
S2Zc
1/0
0/00/0
1/0
0/Z1
1/Z2S0
S1
S2
Za
X0 1
Zb
X0 1
X0 1
Zc
Z1 Z2
00 = AB
01
11
NguyenTrongLuat 80
41
S0
Za
X0 1
Zb
X0 1
X0 1
Zc
Z1 Z2
S1
S2
Giản đồ định thìClock
State
X
Za
Zb
Zc
Z1
Z2
S0 S1 S2 S2 S0 S0
NguyenTrongLuat 81
42
CAØI ÑAËT LÖU ÑOÀ MAÙY TRAÏNG THAÙI:
- Vieäc caøi ñaët (realization) löu ñoà SM laø tìm ñöôïc phöông trình cuûa caùc bieán ra vaø caùc bieán traïng thaùi keá tieáp.
- Caùc böôùc thöïc hieän nhö sau:
* Thöïc hieän gaùn traïng thaùi cho caùc hoäp traïng thaùi.
* Xaùc ñònh phöông trình cuûa bieán ra Zi
- Tìm caùc traïng thaùi coù xuaát hieän bieán ra (Zi = 1)
- Nếu laø bieán MOORE thì ta ñöôïc tích soá (AND) cuûacaùc bieán traïng thaùi; coøn neáu laø bieán MEALY thì ta coù tích soácuûa caùc bieán traïng thaùi vaø bieán ñieàu kieän vaøo.
- Phöông trình cuûa bieán ra baèng toång (OR) caùc tích soáñaõ tìm thaáy ôû caùc böôùc treân laïi vôùi nhau.
NguyenTrongLuat 83
S0
S1
S2
Za
X0 1
Zb
X0 1
X0 1
Zc
Z1 Z2
00 = AB
01
11
* Gaùn traïng thaùi: S0: AB = 00; S1: AB = 01 vaø S2: AB = 11
* Phöông trình cuûa caùc bieán ra:
Za = A B
Zb = A BZc = A B
Z1 = A B X
Z2 = A B X
NguyenTrongLuat 84
43
* Xaùc ñònh phöông trình caùc bieán traïng thaùi keá Q+j
- Tìm ra taát caû caùc traïng thaùi trong ñoù Qj=1
- Taïi moãi traïng thaùi naøy, tìm taát caû caùc ñöôøng daãn lieân keát(link path) maø daãn vaøo traïng thaùi ñoù.
- Vôùi moãi ñöôøng daãn lieân keát naøy, tìm ra moät soá haïng laø 1khi ñi theo ñöôøng daãn lieân keát naøy. Nghóa laø, vôùi ñöôøng daãnlieân keát töø Sa ñeán Sb, soá haïng seõ laø 1 tích soá cuûa caùc bieántraïng thaùi ôû traïng thaùi Sa vaø caùc bieán ñieàu kieän ñeå coù theådaãn ñeán Sb.
- Bieåu thöùc Q+j ñöôïc taïo thaønh baèng caùch laáy toång (OR) caùc
tích soá ñöôïc tìm thaáy ôû böôùc treân laïi vôùi nhau
NguyenTrongLuat 85
S0
S1
S2
Za
X0 1
Zb
X0 1
X0 1
Zc
Z1 Z2
00 = AB
01
11
A+ = A B X(S1→→→→ S2)
* Phöông trình caùc bieán traïng thaùi keá:
+ A B X(S2→→→→ S2)
B+ = A B X + A B X(S0→→→→ S1)(S1→→→→ S2) (S2→→→→ S2)
+ A B X
NguyenTrongLuat 86
13-Sep-10
1
PLDTHIẾT BỊ LOGIC LẬP TRÌNH ĐƯỢC
(Programmable Logic Device)
NguyenTrongLuat 1
BOÄ NHÔÙ BAÙN DAÃN
Boä nhôù baùn daãn
Boä nhôù baûng Boä nhôù haøm
RAM ROM
tónh ñoäng MROMPROMEPROMEEPROM
PLD
PLA PAL LCAPPALEPLPALEEPPAL
EPLD PEEL GAL
NguyenTrongLuat 2
13-Sep-10
2
BOÄ NHÔÙ ROM
Input: caùc tín hieäu ñòa chæ (Address)
Output: caùc tín hieäu döõ lieäu (Data)
A0A1
An-1
D0
D1
Dm-1
INPUT
(n ñöôøng)
OUTPUT
(m ñöôøng)
Kích thöôùc ROM: 2n x m (bit)
NguyenTrongLuat 3
word line
bit line
101
1
0
0
1
1
1
1
1
1
1
1
0
1
0
0
Baûng naïp ROMA2 A1 A0 D3 D2 D1 D0
0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1
1 1 1 01 1 0 11 0 1 10 1 1 10 0 0 10 0 1 00 1 0 01 0 0 0
Caáu truùc noäi ROM 8 x 4 (bit)
1
NguyenTrongLuat 4
13-Sep-10
3
ROM 128 x 1 (bit) giaûi maõ 2 chieàu
NguyenTrongLuat 5
ROM 32Kx 8 (bit) = 32KB
NguyenTrongLuat 6
13-Sep-10
4
Caáu truùc ROM coù ngoõ vaøo ñieàu khieån
NguyenTrongLuat 7
Coång ñeäm ba traïng thaùi (Tristate Output Buffer):
- 3 traïng thaùi (tristate): LOW / HIGH / HIGH impedance
- Traïng thaùi toång trôû cao (HIGH impedance): ngoõ ra hôû maïch
- Ngoõ ñieàu khieån 3 traïng thaùi: * HIGH: The buffer is Active* LOW: HIGH impedance
NguyenTrongLuat 8
13-Sep-10
5
Caùc EPROM thoâng duïng
NguyenTrongLuat 9
PLA(PROGRAMMABLE LOGIC ARRAY)
INPUT
(n bit)
OUTPUT
(m bit)
k product term (soá haïng tích)
Daõy AND
Daõy OR
NguyenTrongLuat 10
13-Sep-10
6
Daõy AND coù theå laäp trình
Daõy OR coù theå laäp trìnhNguyenTrongLuat 11
0
1
A Caáu truùc PLA 3 x 2, 4 soá haïng tích
B
C
C AB ABC
A B
A C
B C
A B C
F1
F1 = A B + A C + A B C
F2 = A C + B C
F2
Baûng naïp PLAA B C F2 (C) F1 (T)
1 0 -A B
A C 1 - 1 B C - 1 1
A B C 0 1 0
0 1
1 1 1 0
0 1 NguyenTrongLuat 12
13-Sep-10
7
PAL(PROGRAMMABLE ARRAY LOGIC )
- Daõy AND laäp trình, daõy OR coá ñònh
- Caáu truùc PLA: soá ngoõ vaøo, soá ngoõ ra vaø soá coång AND treân 1 coång OR
- Moãi ngoõ ra laø coång OR coù soá ngoõ vaøo coá ñònh
- Soá haïng tích khoâng söû duïng chung cho caùc ngoõ ra
NguyenTrongLuat 13
Caáu truùc PAL 3 ngoõ vaøo, 3 ngoõ ra, 3 coång AND / OR
1
2
3
4
5
6
7
8
9
I1
I2
I3
F1
F2
F3
NguyenTrongLuat 14
13-Sep-10
8
A
1
2
3
4
5
6
7
8
9
B
C
X
Y
Z
A A B B C C X X
X = A B + B C Z = A B + B C + B C + A C Y = A + B C
= X + B C + A C
NguyenTrongLuat 15
X = A B + B C Z = A B + B C + B C + A C Y = A + B C
= X + B C + A C
Baûng naïp PAL
A B C X OUTPUT
X = A B+ B C
1 1 1 1
0 Y = A 0 0 + B C
Z = X10 0 + B C
0 1 + A C
123
456
789
NguyenTrongLuat 16
13-Sep-10
1
VHDL
- VHDL laø ngoân ngöõ moâ taû phaàn cöùng.
- VHDL vieát taét cuûa VHSIC (Very High Speed Integrated Circuit) Hardware Description Language
- VHDL khoâng phaân bieät chöõ vieát hoa vaø chöõ thöôøng.databus Databus DataBus DATABUS
- VHDL laø ngoân ngöõ “ñònh daïng töï do”.
if (a=b) then
if (a=b) then
if (a =
b) then
NguyenTrongLuat 1
Thuaät ngöõ COMPONENT:
- Laø khaùi nieäm trung taâm moâ taû phaàn cöùng baèng VHDL ñeå bieåu dieãn caùc caáp thieát keá töø coång ñôn giaûn ñeán 1 heä thoáng phöùc taïp.
- Moâ taû component bao goàm ENTITY vaø ARCHITECTURE.
- Moät component coù theå söû duïng caùc component khaùc.
d0
d1 y
sel
mux2to1
a
bz
nand2
NguyenTrongLuat 2
13-Sep-10
2
Maõ VHDL cô baûn
LIBRARYkhai baùo thö vieän
ENTITYthöïc theå
ARCHITECTUREkieán truùc
NguyenTrongLuat 3
Ví duï:Maõ VHDL moâ taû component NAND 2 ngoõ vaøo
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY nand_gate IS
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC;
z : OUT STD_LOGIC);
END nand_gate;
ARCHITECTURE model OF nand_gate IS
BEGIN
z <= a NAND b;
END model;
a
bz
NguyenTrongLuat 4
13-Sep-10
3
LIBRARY LIBRARY ieee;
USE ieee.std_logic_1164.all;
- LIBRARY: khai baùo thö vieän ieeeieeeieeeieee
- USE: söû duïng caùc ñònh nghóa goùi (package) std_logic_1164std_logic_1164std_logic_1164std_logic_1164
ENTITY nand_gate IS
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC;
z : OUT STD_LOGIC);
END nand_gate;
ENTITY
- ENTITY: ñaët teân cho entity (nand_gatenand_gatenand_gatenand_gate)- PORT: khai baùo caùc chaân xuaát/nhaäp
* Teân port (portname): a, b, z* Kieåu port (mode): IN, OUT* Kieåu tín hieäu (type): STD_LOGIC
a
bz
Moâ taû caùc tín hieäu xuaát/nhaäp cuûa khoái component
NguyenTrongLuat 5
* Caùc kieåu chaân PORT I/0IN: döõ lieäu ñi vaøo entity qua port vaø coù theå ñöôïc ñoïc trong entity. OUT: döõ lieäu xuaát ra ngoaøi entity qua chaân port.
Port OUT khoâng theå ñoïc veà laïi entity.INOUT: laø port 2 chieàu, cho pheùp döõ lieäu ñi vaøo hoaëc ra. BUFFER: töông töï port OUT, nhöng ñöôïc pheùp ñoïc laïi bôûi entity.
IN
IN
IN
OUT
BUFFER
OUT
INOUT
NguyenTrongLuat 6
13-Sep-10
4
ARCHITECTURE
ARCHITECTURE model OF nand_gate IS
BEGIN
z <= a NAND b;
END model;
- ARCHITECTURE: ñaët teân cho architecture (modelmodelmodelmodel)
Moâ taû thieát keá beân trong cuûa khoái, chæ roõ moái quan heä giöõa caùc ngoõ vaøo vaø ngoõ ra.
- Coù 3 loaïi moâ taû architecture
* Moâ taû caáu truùc (Structural)
* Moâ taû luoàng döõ lieäu (Dataflow)* Moâ taû haønh vi (Behavioral)
a
bz
NguyenTrongLuat 7
ÑOÁI TÖÔÏNG DÖÕ LIEÄU (Data object)* Tín hieäu (signal): bieåu dieãn cho caùc daây keát noái cuûa maïch.
Noù ñöôïc khai baùo trong phaàn PORT cuûa khai baùo entity hoaëc trong phaàn ñaàu trong architecture (tröôùc BEGIN).
SIGNAL signal_name : signal_type;
* Bieán (Variable): ñöôïc khai baùo vaø söû duïng trong process. Bieán khoâng phaûi laø tín hieäu logic thaät.
VARIABLE variable_name : variable_type;
* Haèng soá (Constant): giöõ moät giaù trò khoâng ñöôïc thay ñoåiCONSTANT constant_name : constant_type;
SIGNAL a : std_logic;
VARIABLE b : std_logic;
CONSTANT max : integer;
Caùc ñoái töôïng döõ lieäu coù theå ñöôïc ñaët giaù trò ñaàu, khai baùo sau phaàn khai baùo kieåu döõ lieäu _type:= value;
CONSTANT max : integer : = 25;NguyenTrongLuat 8
13-Sep-10
5
- Leänh gaùn tín hieäu: signal_name <= expression;
a <= NOT b AND c;
variable_name := expression;
y := NOT a;
- Leänh gaùn bieán:
- Bieán (Variable) laø cuïc boä trong process.
- Pheùp gaùn bieán (Variable) cho giaù trò töùc thôøi, pheùp gaùn cuûa tín hieäu (signal) bò treã (delay)
- Tín hieäu (Signal) coù theå quan saùt daïng soùng (waveform), nhöng bieán (Variable) thì khoâng.
* Söï khaùc nhau giöõa Tín hieäu (Signal) vaø Bieán (Variable)
NguyenTrongLuat 9
KIEÅU DÖÕ LIEÄU (Data type)- Caùc kieåu döõ lieäu laø ñaëc tính cuûa signal, variable, …
- Coù theå taïo ra caùc kieåu döõ lieäu môùi baèng leänh TYPE hoaëc SUBTYPE
- Caùc döõ lieäu cuøng kieåu môùi ñöôïc gaùn hoaëc keát noái vôùi nhau
* Kieåu BIT vaø BIT_VECTOR:- BIT coù giaù trò ‘0’ vaø ‘1’.- BIT_VECTOR laø daõy (array) cuûa BIT.
* Kieåu INTEGER
* Kieåu BOOLEAN: coù giaù trò TRUE vaø FALSE.
* Kieåu lieät keâ (ENUMERATION) do ngöôøi söû duïng ñònh nghóa.
* Kieåu CHARACTER
* . . .NguyenTrongLuat 10
13-Sep-10
6
SIGNAL a: STD_LOGIC;
SIGNAL b: STD_LOGIC_VECTOR(7 DOWNTO 0);
a laø tín hieäu STD_LOGIC kieåu 1 bit
b,c laø tín hieäu STD_LOGIC kieåu bus coù 8 bit
* STD_LOGIC: Value Meaning ‘X’ Forcing (Strong driven) Unknown‘0’ Forcing (Strong driven) 0‘1’ Forcing (Strong driven) 1‘Z’ High Impedance‘W’ Weak (Weakly driven) Unknown
‘L’ Weak (Weakly driven) 0.Models a pull down.
‘H’ Weak (Weakly driven) 1. Models a pull up.
‘-’ Don't Care‘U’ Uninitialized
- Coù 9 giaù trò- Höõu ích khi moâ phoûng- Chæ coù 3 giaù trò ‘0’, ‘1’, ‘Z’ laø coù theå toång hôïp
SIGNAL c: STD_LOGIC_VECTOR(0 TO 7);
- Laø kieåu tín hieäu quyeát ñònh (coù theå ñöôïc laùi baèng 2 ngoõ vaøo)
NguyenTrongLuat 11
SIGNAL a: STD_LOGIC;
SIGNAL b: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL c: STD_LOGIC_VECTOR(0 TO 3);
SIGNAL d: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL e: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL f: STD_LOGIC_VECTOR(8 DOWNTO 0);
a <= ’1’; -- giaù trò gaùn ñaët giöõa 1 daáu nhaùy ñôn ‘ ’a <= b(2); -- a <= b(2), b <= "0000”; -- giaù trò gaùn ñaët giöõa 1 daáu nhaùy keùp “ ”c <= B”0000”; -- B laø kyù hieäu cô soá 2 (coù theå boû)d <= ”0110_0111”; -- bieåu dieãn töøng nhoùm 4 bit phaân caùch _e <= X”AF67”; -- X laø kyù hieäu cô soá 16 (Hex)f <= O”723”; -- O laø kyù hieäu cô soá 8 (Octal) b <= c; -- b(3) <= c(0), b(2) <= c(1),
-- b(1) <= c(2), b(0) <= c(3)d(7 downto 6)<= ”11”;
c(0 to 2)<= e(7 downto 5);
Pheùp gaùn tín hieäu kieåu STD_LOGIC
NguyenTrongLuat 12
13-Sep-10
7
SIGNAL a: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL b: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL c, d, e: STD_LOGIC_VECTOR(7 DOWNTO 0);
a <= ”0000”;
b <= ”1111”;
c <= a & b; -- c = “00001111”
d <= ’0’ & ”0001111”; -- d = “00001111”
e <= ’0’ & ’0’ & ’0’ & ’0’ & ’1’ & ’1’ &
’1’ & ’1’; -- e = “00001111”
Gheùp noái chuoãi (Concatenation)
NguyenTrongLuat 13
PHEÙP TOAÙN (Operator)
* Pheùp toaùn Logic (Logical Operator):
NOT AND OR NAND NOR XOR XNOR
Söû duïng cho kieåu: bit, bit_vector, boolean, std_logic, std_logic_vector.
* Pheùp toaùn quan heä (Relationship Operator):
= /= < <= > >=
So saùnh 2 toaùn haïng cuøng kieåu vaø keát quaû traû veà kieåu boolean
* Pheùp toaùn dòch (Shift Operator):
SLL SRL SLA SRA ROL ROR
* Pheùp toaùn coäng (Adding Operator): + -
NguyenTrongLuat 14
13-Sep-10
8
* Pheùp toaùn nhaân (Multiplying Operator):
* / MOD REM
* Pheùp toaùn daáu (Sign Operator): - +
* Pheùp toaùn khaùc (Operator): ** ABS ** ABS
* Thöù töï öu tieân thöïc hieän caùc pheùp toaùn
** ABS NOT
* / MOD REM
+ - (Daáu)+ - &
= /= < <= > >=
AND OR NAND NOR XOR XNOR
Caùc pheùp toaùn cuøng loaïi khoâng coù öu tieân, neáu caàn söû duïng ( )NguyenTrongLuat 15
MOÂ TAÛ THIEÁT KEÁ (Design description)
MOÂ TAÛ THIEÁT KEÁ
(Design description)
CAÁU TRUÙC
(Structural)
LUOÀNG DÖÕ LIEÄU
(Dataflow)
HAØNH VI
(Behavioral)
NguyenTrongLuat 16
13-Sep-10
9
MOÂ TAÛ CAÁU TRUÙC (Structural description)
- Söû duïng caùc khoái component coù caáp thaáp hôn.- Caùc khoái component naøy ñöôïc keát noái theo thöù baäc.
- Caùc component caáp thaáp ñöôïc khai baùo baèng leänh COMPONENT, ñaët ôû phaàn ARCHITECTURE (tröôùc BEGIN).
- Ñeå keát noái component caáp thaáp, thöïc hieän leänh thay theá trò soá component (component instantiation) PORT MAP.
COMPONENT and2
PORT (x1,x2:IN STD_LOGIC;
y: OUT STD_LOGIC);
END COMPONENT;
x1y
x2
* Keát hôïp vò trí (positional association)
* Keát hôïp theo teân (named association)
Coù 2 caùch:
NguyenTrongLuat 17
COMPONENT and2
PORT (x1,x2:IN STD_LOGIC;
y: OUT STD_LOGIC);
END COMPONENT;
BEGIN
user1: and2 PORT MAP ( x1 => a, x2 => b,
y => c );
...
* Keát hôïp theo teân (named association)
COMPONENT component_name
port declarations;
END COMPONENT;
...
Label: component_name PORT MAP (
port_name1 => sig_name1,
port_name2 => sig_name2 );
NguyenTrongLuat 18
13-Sep-10
10
COMPONENT and2
PORT (x1,x2:IN STD_LOGIC;
y: OUT STD_LOGIC);
END COMPONENT;
BEGIN
user1: and2 PORT MAP ( a, b, c );
...
COMPONENT and2
PORT (x1,x2:IN STD_LOGIC;
y: OUT STD_LOGIC);
END COMPONENT;
BEGIN
user1: and2 PORT MAP ( a, b, c );
...
* Keát hôïp vò trí (positional association)
COMPONENT component_name
port declarations;
END COMPONENT;
...
Label: component_name PORT MAP (
sig_name1, sig_name2, ... );
NguyenTrongLuat 19
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY xor3 IS
PORT ( a, b, c : IN STD_LOGIC;
result : OUT STD_LOGIC);
END xor3;
ARCHITECTURE structural OF xor3 IS
SIGNAL u1_out: STD_LOGIC;
COMPONENT xor2
PORT ( i1, i2 : IN STD_LOGIC;
y : OUT STD_LOGIC );
END COMPONENT;
BEGIN
u1: xor2 PORT MAP ( i1 => a, i2 => b,
y => u1_out);
u2: xor2 PORT MAP ( i1 => u1_out, i2 => c,
y => result);
END structural;
a
b
c
result
VD: Thieát keá XOR 3 ngoõ vaøo u1_out
NguyenTrongLuat 20
13-Sep-10
11
MOÂ TAÛ LUOÀNG DÖÕ LIEÄU (Dataflow description)
- Moâ taû luoàng döõ lieäu di chuyeån töø ngoõ vaøo ñeán ngoõ ra.
- Söû duïng caùc phaùt bieåu ñoàng thôøi (Concurrent statement):
* Pheùp gaùn baèng pheùp toaùn
- Caùc phaùt bieåu naøy ñöôïc thöïc thi cuøng thôøi ñieåm, vì vaäy thöù töï caùc phaùt bieåu laø nhö nhau
* Pheùp gaùn WHEN - ELSE
* Pheùp gaùn WITH – SELECT - WHEN
* Pheùp taïo GENERATE
NguyenTrongLuat 21
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY xor3 IS
PORT ( a, b, c : IN STD_LOGIC;
result : OUT STD_LOGIC);
END xor3;
ARCHITECTURE dataflow OF xor3 IS
SIGNAL u1_out: STD_LOGIC;
BEGIN
u1_out <= a XOR b;
Result <= u1_out XOR c;
END dataflow;
Result <= u1_out XOR c;
u1_out <= a XOR b;
a
b
c
result
u1_out
Pheùp gaùn baèng pheùp toaùn (OPERATOR)
NguyenTrongLuat 22
13-Sep-10
12
Pheùp gaùn tín hieäu theo ñieàu kieän (Condition Signal Assigment)WHEN - ELSE
signal_name <= value1 WHEN condition1 ELSE
{value2 WHEN condition2 ELSE}
valueN ;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY mux2to1 IS
PORT ( d0, d1 : IN STD_LOGIC;
sel : IN STD_LOGIC;
y : OUT STD_LOGIC);
END mux2to1;
ARCHITECTURE dataflow1 OF mux2to1 IS
BEGIN
y <= d0 WHEN sel = ’0’ ELSE d1;
END dataflow1;
d0
d1 y
sel
mux2to1
sel y01
d0d1
y <= d0 WHEN sel = ’0’ ELSE
d1 WHEN OTHERS;
VD: Mux2to1
NguyenTrongLuat 23
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY xnor2 IS
PORT ( a, b : IN STD_LOGIC;
c : OUT STD_LOGIC);
END xnor2;
ARCHITECTURE dataflow1 OF xnor2 IS
BEGIN
c <= ’1’ WHEN a = ’0’ AND b = ’0’ ELSE
’0’ WHEN a = ’0’ AND b = ’1’ ELSE
’0’ WHEN a = ’1’ AND b = ’0’ ELSE
’1’ WHEN a = ’1’ AND b = ’1’ ELSE
’0’ WHEN OTHERS;
END dataflow1;
xnor2 a b c0 00 11 01 1
1001
VD: xnor2a
bc
NguyenTrongLuat 24
13-Sep-10
13
Pheùp gaùn tín hieäu coù choïn loïc (Select Signal Assigment)WITH – SELECT - WHEN
WITH select_signal SELECT
signal_name <= value1 WHEN const1_of_select_signal,
{value2 WHEN const2_of_select_signal,}
valueN WHEN OTHERS;
d0
d1 y
sel
mux2to1
sel y01
d0d1
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY mux2to1 IS
PORT ( d0, d1 : IN STD_LOGIC;
sel : IN STD_LOGIC;
y : OUT STD_LOGIC);
END mux2to1;
ARCHITECTURE dataflow2 OF mux2to1 IS
BEGIN
WITH sel SELECT
y <= d0 WHEN ’0’,
d1 WHEN OTHERS;
END dataflow2;NguyenTrongLuat 25
WITH select_signal SELECT
signal_name <= value1 WHEN const1_of_select_signal,
{value2 WHEN const2_of_select_signal,}
valueN WHEN OTHERS;
Tham soá const_of_select_signal coù theå bieåu dieãn nhieàu giaù trò rieâng bieät hoaëc 1 daõi giaù trò lieân tieáp.
PORT ( d0, d1, d2, d3 : IN STD_LOGIC;
sel : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
y : OUT STD_LOGIC );
...
...
WITH sel SELECT
y <= d0 WHEN ”001”,
d1 WHEN ”011” to ”101”,
d2 WHEN ”000” | ”111”,
d3 WHEN OTHERS;
PORT ( d0, d1, d2, d3 : IN STD_LOGIC;
sel : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
y : OUT STD_LOGIC );
...
...
WITH sel SELECT
y <= d0 WHEN ”001”,
d1 WHEN ”011” to ”101”,
d2 WHEN ”000” | ”111”,
d3 WHEN OTHERS;
NguyenTrongLuat 26
13-Sep-10
14
xnor2 a b c0 00 11 01 1
1001
VD: xnor2a
bc
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY xnor2 IS
PORT ( a, b : IN STD_LOGIC;
c : OUT STD_LOGIC);
END xnor2;
ARCHITECTURE dataflow2 OF xnor2 IS
SIGNAL ab : STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
ab <= a & b;
WITH ab SELECT
c <= ’1’ WHEN ”00” | ”11”,
’0’ WHEN OTHERS;
END dataflow2;
NguyenTrongLuat 27
Phaùt bieåu FOR - GENERATE
GENERATE laø caùch ñeå taïo ra nhieàu tình huoáng (instance) cho caùc phaùt bieåu ñoàng thôøi, thöôøng duøng cho caùc pheùp gaùn thay theá trò soá töông ñöông component (component instantitation).
[Name:] FOR index_variable IN range GENERATE
concurent_statements;
END GENERATE [name] ;
g0: FOR i IN 0 to 3 GENERATE
z(i) <= x(i) and y(i+8);
END GENERATE;
xor_array: FOR i IN 7 downto 0 GENERATE
user: xor2 PORT MAP (
x(i), y(i), z(i) );
END GENERATE;
NguyenTrongLuat 28
13-Sep-10
15
GENERIC
- Laø caáu truùc ñeå ñöa 1 haèng soá vaøo trong entity gioáng khai baùo CONSTANT.- Tieän lôïi cuûa generic laø coù theå söû duïng noù trong pheùp gaùn thay theá trò soá töông ñöông component (component instantitation), ñeå söû duïng caùc giaù trò haèng soá khaùc nhau khi tham chieáu component.
ENTITY entity_name IS
GENERIC (
generic_name1: data_type := default_values;
generic_name2: data_type := default_values;
)
PORT (
port_name: mode data_type;
... )
END entity_name;
NguyenTrongLuat 29
* Pheùp gaùn thay theá trò soá component coù GENERIC
Label: component_name
GENERIC MAP (
generic_name1 => sig_name1,
gereric_name2 => sig_name2 );
PORT MAP (
port_name => sig_name);
* Khai baùo component coù GENERICCOMPONENT component_name
GENERIC (
generic_name1: data_type := default_values;
...)
PORT (
port_name: mode data_type;
...)
END COMPONENT;
NguyenTrongLuat 30
13-Sep-10
16
MOÂ TAÛ HAØNH VI ( Behavioral description)
- Moâ taû söï ñaùp öùng cuûa ngoõ ra theo ngoõ vaøo.
- Caùc phaùt bieåu tuaàn töï (Sequential statement): cho pheùp moâ taû hoaït ñoäng tuaàn töï cuûa caùc tín hieäu
* Phaùt bieåu IF
* Phaùt bieåu CASE
* Phaùt bieåu LOOP
- Söû duïng phaùt bieåu PROCESS chöùa caùc leänh ñöôïc thöïc thi tuaàn töï, phuï thuoäc vaøo thöù töï cuûa noù
NguyenTrongLuat 31
PROCESS
- Process thöïc hieän caùc leänh beân trong noù 1 caùch tuaàn töï. Vì vaäy thöù töï cuûa caùc leänh raát quan troïng.
- Moät Architecture coù nhieàu Process. Caùc Process laø caùc phaùt bieåu ñoàng thôøi
- Process ñöôïc kích hoaït khi coù söï thay ñoåi cuûa 1 tín hieäu.
[Name:] PROCESS (sensitivity list)
variable declarations
BEGIN
sequential statements
END PROCESS [Name];
Sensitivity list: danh saùch caûm nhaänVariable declarations: khai baùo bieán
NguyenTrongLuat 32
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17
* Danh saùch caûm nhaän (sensitivity list):- Khai baùo caùc tín hieäu duøng ñeå kích hoaït Process khi tín hieäu thay ñoåi (thöôøng goïi laø söï kieän event). Thöôøng laø caùc tín hieäu ngoõ vaøo.
- Khi Process ñöôïc kích hoaït thì caùc phaùt bieåu beân trong process ñöôïc thöïc hieän tuaàn töï. Khi thöïc hieän xong phaùt bieåu cuoái cuøng thì Process vaøo traïng thaùi chôø (suspend).
* Khai baùo bieán (variable declaration):Khai baùo caùc bieán cuïc boä söû duïng trong Process
* Phaùt bieåu tuaàn töï :
- Ñaët giöõa BEGIN vaø END cuûa Process.
- Goàm caùc pheùp gaùn tín hieäu vaø bieán, caùc phaùt bieåu tuaàn töï IF, CASE, LOOP…
NguyenTrongLuat 33
Phaùt bieåu IF - THEN - ELSEIF condition1 THEN sequential_statements_1;
{ELSIF condition2 THEN sequential_statements_1;}
{ELSE sequential_statements_1;}
END IF;
d0
d1 y
sel
mux2to1
sel y01
d0d1
VD: Mux2to1
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY mux2to1 IS
PORT ( d0, d1 , sel : IN STD_LOGIC;
y : OUT STD_LOGIC);
END mux2to1;
ARCHITECTURE behavior1 OF mux2to1 IS
BEGIN
PROCESS (d0, d1, sel)
BEGIN
IF sel = ’0’ THEN y <= d0 ;
ELSE y <= d1 ;
END IF;
END PROCESS;
END behavior1;NguyenTrongLuat 34
13-Sep-10
18
Phaùt bieåu CASE - WHENCASE select_signal IS
WHEN value1 => sequential_statements_1;
WHEN value2 => sequential_statements_2;
WHEN OTHERS => sequential_statements_N;
END CASE;
d0
d1 y
sel
mux2to1
sel y01
d0d1
VD: Mux2to1LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY mux2to1 IS
PORT ( d0, d1 , sel : IN STD_LOGIC;
y : OUT STD_LOGIC);
END mux2to1;
ARCHITECTURE behavior2 OF mux2to1 IS
BEGIN
PROCESS (d0, d1, sel)
BEGIN
CASE sel IS
WHEN ’0’ => y <= d0 ;
WHEN OTHERS => y <= d1 ;
END CASE;
END PROCESS;
END behavior2;NguyenTrongLuat 35
Phaùt bieåu FOR - LOOP
[Name:] FOR variable_name IN range LOOP
sequential_statements;
END LOOP [name] ;
sqr: FOR i IN 1 to 10 LOOP
a(i) := i*i;
END LOOP sqr;
FOR j IN 3 downto 0 LOOP
IF reset(j) = ’1’ THEN data(j) := ’0’;
END IF;
END LOOP;
Töông töï nhö phaùt bieåu ñoàng thôøi FOR_GENERATE.
NguyenTrongLuat 36
13-Sep-10
19
Phaùt bieåu WHILE - LOOP
i:=0;
WHILE (i<10) LOOP
s <= i;
i := i+1;
END LOOP;
[Name:] WHILE condition LOOP
sequential_statements;
END LOOP [name] ;
NguyenTrongLuat 37
THIEÁT KEÁ HEÄ TOÅ HÔÏP BAÈNG VHDL
- Heä toå hôïp coù theå ñöôïc thöïc hieän baèng caùc phaùt bieåu ñoàng thôøi (concurent statement) vaø tuaàn töï (sequential statement).
- Phaùt bieåu ñoàng thôøi (concurent staement) ñöôïc duøng trong moâ taû caáu truùc (structural description) vaø luoàng döõ lieäu (dataflow description)
- Phaùt bieåu tuaàn töï (sequent statement) ñöôïc duøng trong moâ taû haønh vi (dataflow description)
NguyenTrongLuat 38
13-Sep-10
20
BOÄ COÄNGADDER
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fulladder IS
PORT ( x , y , z : IN STD_LOGIC;
s , c : OUT STD_LOGIC);
END fulladder;
ARCHITECTURE Function OF fulladder IS
BEGIN
s <= x XOR y XOR z ;
C <= (x AND y) OR (y AND z) OR (x AND z);
END Function;
fulladder
x
ys
zc
NguyenTrongLuat 39
s = x ⊕⊕⊕⊕ y ⊕⊕⊕⊕ z
c = x y + y z + x z
adder4
a3
Cout
Cin
a2
a1
a0
b3
b2
b1
b0
s3
s2
s1
s0
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY adder4 IS
PORT ( Cin : IN STD_LOGIC;
a, b : IN STD_LOGIC_VECTOR(3 downto 0);
s : OUT STD_LOGIC_VECTOR(3 downto 0);
Cout : OUT STD_LOGIC);
END adder4;
ARCHITECTURE Structure OF adder4 IS
SIGNAL c : STD_LOGIC_VECTOR(1 to 3);
COMPONENT fulladder
PORT ( x , y , z : IN STD_LOGIC;
s , c : OUT STD_LOGIC);
END COMPONENT;
BEGIN
stage0: fulladder PORT MAP(a(0),b(0),Cin,s(0),c(1)) ;
stage1: fulladder PORT MAP(a(1),b(1),c(1),s(1),c(2)) ;
stage2: fulladder PORT MAP(a(2),b(2),c(2),s(2),c(3)) ;
stage3: fulladder PORT MAP(a(3),b(3),c(3),s(3),Cout) ;
END Structure;
Thieát keá boä coäng 4 bit adder4 söû duïng fulladder
NguyenTrongLuat 40
13-Sep-10
21
Leänh USE ieee.std_logic_signed.all cho pheùp söû duïnggoùi (package) std_logic_signed, ñeå thöïc hieän pheùp toaùn soá hoïc treân caùc tín hieäu std_logic.
Boä coäng 4 bit adder4 söû duïng pheùp coäng soá hoïcLIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
ENTITY adder4 IS
PORT ( Cin : IN STD_LOGIC;
a, b : IN STD_LOGIC_VECTOR(3 downto 0);
s : OUT STD_LOGIC_VECTOR(3 downto 0);
Cout : OUT STD_LOGIC);
END adder4;
ARCHITECTURE Arithmetic OF fulladder IS
SIGNAL sum : STD_LOGIC_VECTOR(4 downto 0);
BEGIN
sum <= (’0’& a ) + b + Cin ;
s <= sum(3 downto 0) ;
Cout <= sum(4) ;
END Arithmetic;
NguyenTrongLuat 41
BOÄ DOÀN KEÂNH
MUX
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY mux4 IS
PORT (
d0 , d1 , d2 , d3 : IN STD_LOGIC;
s : IN STD_LOGIC_VECTOR(1 downto 0);
y : OUT STD_LOGIC);
END mux4;
ARCHITECTURE Function OF mux4 IS
BEGIN
y <= (NOT s(1) AND NOT s(0) AND d0) OR
(NOT s(1) AND s(0) AND d1) OR
(s(1) AND NOT s(0) AND d2) OR
(s(1) AND s(0) AND d3 );
END Function;
MUX4
d0
d1d2
d3
s1s0
y
s1 s0 y0 0 0 11 01 1
d0d1d2d3
NguyenTrongLuat 42
ARCHITECTURE Dataflow OF mux4 IS
BEGIN
y <= d0 WHEN s = ”00” ELSE
d1 WHEN s = ”01” ELSE
d2 WHEN s = ”10” ELSE
d3 WHEN OTHERS;
END Dataflow;
WITH s SELECT
y <= d0 WHEN ”00”,
d1 WHEN ”01”,
d2 WHEN ”10”,
d3 WHEN OTHERS;
13-Sep-10
22
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY mux16 IS
PORT (
d : IN STD_LOGIC_VECTOR(15 downto 0);
c : IN STD_LOGIC_VECTOR(3 downto 0);
f : OUT STD_LOGIC);
END mux16;
ARCHITECTURE Structure OF mux16 IS
SIGNAL w : STD_LOGIC_VECTOR(0 to 3);
COMPONENT mux4
PORT (
d0 , d1 , d2 , d3 : IN STD_LOGIC;
s : IN STD_LOGIC_VECTOR(1 downto 0);
y : OUT STD_LOGIC);
END COMPONENT;
BEGIN
M0: mux4 PORT MAP (d(0),d(1),d(2),d(3),c(1 downto 0),w(0));
M1: mux4 PORT MAP (d(4),d(5),d(6),d(7),c(1 downto 0),w(1));
M2: mux4 PORT MAP (d(8),d(9),d(10),d(11),c(1 downto 0),w(2));
M3: mux4 PORT MAP (d(12),d(13),d(14),d(15),c(1 downto 0),w(3));
M4: mux4 PORT MAP (w(0),w(1),w(2),w(3),c(3 downto 2),f);
END Structure;
NguyenTrongLuat 43
c3 c2 c1 c0 f0 0 0 0 0 0 0 10 0 1 00 0 1 1 0 1 0 0 0 1 0 10 1 1 00 1 1 11 0 0 0 1 0 0 11 0 1 01 0 1 1 1 1 0 0 1 1 0 11 1 1 01 1 1 1
d0d1d2d3d4d5d6d7 d8d9d10d11d12d13d14d15
Thieát keá MUX 16 ����1 söû duïng MUX 4 ����1mux16
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY mux16 IS
PORT (
d : IN STD_LOGIC_VECTOR(15 downto 0);
c : IN STD_LOGIC_VECTOR(3 downto 0);
f : OUT STD_LOGIC);
END mux16;
ARCHITECTURE Structure2 OF mux16 IS
SIGNAL w : STD_LOGIC_VECTOR(0 to 3);
COMPONENT mux4
PORT (
d0 , d1 , d2 , d3 : IN STD_LOGIC;
s : IN STD_LOGIC_VECTOR(1 downto 0);
y : OUT STD_LOGIC);
END COMPONENT;
BEGIN
G0: FOR i IN 0 to 3 GENERATE
MUXES: mux4 PORT MAP (
d(4*i),d(4*i+1),d(4*i+2),d(4*i+3),c(1 downto 0),w(i));
END GENERATE;
M4: mux4 PORT MAP (w(0),w(1),w(2),w(3),c(3 downto 2),f);
END Structure2;
NguyenTrongLuat 44
Söû duïng
GENERATE
13-Sep-10
23
BOÄ GIAÛI MAÕ DECODER
en x1 x0 y3 y2 y1 y0
0 X X 1 0 01 0 11 1 01 1 1
0 0 0 00 0 0 10 0 1 00 1 0 01 0 0 0
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY dec2x4 IS
PORT ( en : IN STD_LOGIC;
x : IN STD_LOGIC_VECTOR(1 downto 0);
y : OUT STD_LOGIC_VECTOR(3 downto 0));
END dec2x4;
ARCHITECTURE flow OF dec2x4 IS
SIGNAL
temp: STD_LOGIC_VECTOR(3 downto 0);
BEGIN
WITH x SELECT
temp <= ”0001” WHEN ”00” ,
”0010” WHEN ”01” ,
”0100” WHEN ”10” ,
”1000” WHEN ”11” ,
”0000” WHEN OTHERS;
y <= temp WHEN en = ’1’
ELSE ”0000”;
END flow;
NguyenTrongLuat 45
y0
y1
y2
y3
x0
x1
en
dec2x4
ARCHITECTURE flow2 OF
dec2x4 ISSIGNAL
en_x: STD_LOGIC_VECTOR(
2 downto 0);BEGINen_x <= en & x;
WITH en_x SELECT
f <= ”0001” WHEN ”100” ,
”0010” WHEN ”101” ,
”0100” WHEN ”110” ,
”1000” WHEN ”111” ,
”0000” WHEN OTHERS;END flow2;
Thieát keá IC DECCODER 74138LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY dec138 IS
PORT ( c, b, a : IN STD_LOGIC;
g1,g2a,g2b: IN STD_LOGIC;
y : OUT STD_LOGIC_VECTOR(7 downto 0));
END dec138;
ARCHITECTURE flow OF dec138 IS
SIGNAL
data: STD_LOGIC_VECTOR(2 downto 0);
temp: STD_LOGIC_VECTOR(7 downto 0);
BEGIN
data <= c & b & a;WITH data SELECT temp <= ”11111110” WHEN ”000” ,
”11111101” WHEN ”001” ,”11111011” WHEN ”010” ,”11110111” WHEN ”011” ,”11101111” WHEN ”100” ,”11011111” WHEN ”101” ,”10111111” WHEN ”110” ,”01111111” WHEN ”111” ,”11111111” WHEN OTHERS;
y <= temp WHEN (g1 AND NOT g2a AND NOT g2b) = ’1’
ELSE ”11111111”;
END flow;NguyenTrongLuat 46
13-Sep-10
24
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY dec3to8 IS
PORT (x : IN STD_LOGIC_VECTOR(2 downto 0);
en: IN STD_LOGIC;
y : OUT STD_LOGIC_VECTOR(7 downto 0));
END dec3to8;
ARCHITECTURE behavior OF dec3to8 IS
BEGIN
PROCESS (x, en)
BEGIN
y <= ”11111111”;
IF (en = ’1’) THEN
CASE x IS WHEN ”000” => y(0) <= ’0’;
WHEN ”001” => y(1) <= ’0’;
WHEN ”010” => y(2) <= ’0’;
WHEN ”011” => y(3) <= ’0’;
WHEN ”100” => y(4) <= ’0’;
WHEN ”101” => y(5) <= ’0’;
WHEN ”110” => y(6) <= ’0’;
WHEN ”111” => y(7) <= ’0’;END CASE;
END IF;END PROCESS;
END behavior;
Söû duïng PROCESS
NguyenTrongLuat 47
Phaùt bieåu
If ….
Case ….
BOÄ GIAÛI MAÕ3 ���� 8
BOÄ GIAÛI MAÕ3 ���� 8
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY decode38 IS
PORT ( x : IN STD_LOGIC_VECTOR(2 downto 0);
y : OUT STD_LOGIC_VECTOR(0 to 7));
END decode38;
ARCHITECTURE behavior OF decode38 IS
BEGIN
PROCESS(x)
VARIABLE j: integer;
BEGIN
j := CONV_INTEGER(x);
FOR i IN 0 to 7 LOOP
IF (i = j) THEN
y(i) <= ’0’;
ELSE y(i) <= ’1’;
END IF;
END LOOP;
END PROCESS;
END behavior;
Söû duïng PROCESS
Phaùt bieåu
For …. loop
NguyenTrongLuat 48
Söû duïng haøm CONV_INTEGER ñeå ñoåi döõ lieäu kieåu STD_LOGIC_VECTOR thaønh kieåu INTEGER.
Ñeå söû duïng haøm naøy, trong phaàn LIBRARY caàn phaûi khai baùo goùi (package) - STD_LOGIC_ARITH - STD_LOGIC_UNSIGNED
BOÄ GIAÛI MAÕ3 ���� 8
BOÄ GIAÛI MAÕ3 ���� 8
13-Sep-10
25
NguyenTrongLuat 49
BOÄ MAÕ HOÙA ÖU TIEÂNENCODER
i3 i2 i1 i0 x1 x0 v
0 0 0 00 0 0 10 0 1 X0 1 X X1 X X X
d d 0 0 0 10 1 11 0 11 1 1
i0
i1
i2
i3
x0
x1
v
encoder
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY encoder IS
PORT ( i : IN STD_LOGIC_VECTOR(3 downto 0);
x : OUT STD_LOGIC_VECTOR(1 downto 0);
v : OUT STD_LOGIC);
END encoder;
ARCHITECTURE flow OF encoder IS
BEGIN
x <= ”11” WHEN i(3) = ’1’ ELSE
”10” WHEN i(2) = ’1’ ELSE
”01” WHEN i(1) = ’1’ ELSE
”00” ;
v <= ’0’ WHEN i = ”0000”
ELSE ’1’;
END flow;
WITH i SELECTx <=”00” WHEN ”0001” ,
”01” WHEN ”0010”|”0011”,”10” WHEN ”0100”
to ”0111”,”11” WHEN OTHERS;
WITH i SELECTV <=’0’ WHEN ”0000”,
’1’ WHEN OTHERS;
NguyenTrongLuat 50
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY encoder2 IS
PORT ( i : IN STD_LOGIC_VECTOR(3 downto 0);
x : OUT STD_LOGIC_VECTOR(1 downto 0);
v : OUT STD_LOGIC);
END encoder2;
ARCHITECTURE behavior OF encoder2 IS
BEGIN
PROCESS (i)
BEGIN
IF i(3) = ’1’ THEN x <= ”11”;
ELSIF i(2) = ’1’THEN
x <= ”10”;
ELSIF i(1) = ’1’THEN
x <= ”01”;
ELSIF x <= ”00”;
END IF;
END PROCESS;
v <= ’0’ WHEN i = ”0000”
ELSE ’1’;
END behavior;
PROCESS (i)
BEGIN
x <= ”00”;
IF i(1)=’1’ THEN x <=”01”;
END IF;
IF i(2)=’1’ THEN x <=”10”;
END IF;
IF i(3)=’1’ THEN x <=”11”;
END IF;
v <= ’1’;
IF i=”0000” THEN v <=’0’;
END IF;
END PROCESS;
Söû duïng PROCESS
13-Sep-10
26
NguyenTrongLuat 51
BOÄ SO SAÙNH COMPARATOR
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY compare IS
PORT (a, b : IN STD_LOGIC_VECTOR(3 downto 0);
aeqb, agtb, altb : OUT STD_LOGIC);
END compare;
ARCHITECTURE behavior1 OF compare IS
BEGIN
aeqb <= ’1’ WHEN a = b ELSE ’0’;
agtb <= ’1’ WHEN a > b ELSE ’0’;
altb <= ’1’ WHEN a < b ELSE ’0’;
END behavior1;ARCHITECTURE behavior2 OF compare IS
BEGIN
PROCESS (a, b)
BEGIN
aeqb <= ’0’; agtb <= ’0’; altb <= ’0’;
IF a = b THEN aeqb <= ’1’; END IF;
IF a > b THEN agtb <= ’1’; END IF;
IF a < b THEN altb <= ’1’; END IF;
END PROCESS;
END behavior2;
BOÄ SO SAÙNH 4 BIT
LIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY led IS
PORT ( bcd : IN STD_LOGIC_VECTOR(3 downto 0);segs : OUT STD_LOGIC_VECTOR(6 downto 0);
END led;ARCHITECTURE Behavioral OF led ISBEGIN
PROCESS(bcd)BEGIN
CASE bcd IS -- abcdefgWHEN "0000" => segs <= "1111110"; WHEN "0001" => segs <= "0110000"; WHEN "0010" => segs <= "1101101"; WHEN "0011" => segs <= "1111001"; WHEN "0100" => segs <= "0110011"; WHEN "0101" => segs <= "1011011";WHEN "0110" => segs <= "1011111";WHEN "0111" => segs <= "1110000";WHEN "1000" => segs <= "1111111";WHEN "1001" => segs <= "1111011";WHEN OTHERS => segs <= "0000000";-- ALL OFF
END CASE;END PROCESS;
END Behavioral;
a
b
c
d
e
f
g
a
b
c
d
e
f
g
BOÄ GIAÛI MAÕ LED 7 ÑOAÏN
BCDTO
7SEGS
NguyenTrongLuat 52
13-Sep-10
27
THIEÁT KEÁ HEÄ TUAÀN TÖÏ BAÈNG VHDL
- Heä tuaàn töï chæ ñöôïc thöïc hieän baèng caùc phaùt bieåu tuaàn töï (sequential statement).
- Thöïc hieän: maïch choát, FF, thanh ghi, boä ñeám, maùy traïng thaùi.
- Bieán (Variable) chæ toàn taïi cuïc boä trong Process, vì vaäy muoán laáy giaù trò cuûa bieán ra ngoaøi Process thì ta phaûi gaùn bieán cho tín hieäu (Signal).
NguyenTrongLuat 53
- Trong Process, bieán ñöôïc caäp nhaät giaù trò sau moãi phaùt bieåu; coøn tín hieäu chæ ñöôïc caäp nhaät ôû cuoái Process.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY Dlatch IS
PORT (D, Clk : IN STD_LOGIC;
Q, Qn : OUT STD_LOGIC);
END Dlatch;
ARCHITECTURE behavior OF Dlatch IS
BEGIN
PROCESS (D, Clk)
BEGIN
IF Clk = ’1’ THEN
Q <= D;
Qn <= NOT Q;
END IF;
END PROCESS;
END behavior;
D
Clk
Q
Q
Dlatch
clk D Q+ Q+
0 X Q Q1 01 1
0 11 0
NguyenTrongLuat 54
MAÏCH CHOÁT
13-Sep-10
28
NguyenTrongLuat 55
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY Dflipflop IS
PORT (D, Clk : IN STD_LOGIC;
Q, Qn : OUT STD_LOGIC);
END Dflipflop;
ARCHITECTURE behavior OF Dflipflop IS
BEGIN
PROCESS (Clk)
BEGIN
IF Clk’event AND Clk = ’1’ THEN
Q <= D;
Qn <= NOT Q;
END IF;
END PROCESS;
END behavior;
D
clk
Q
Q
Dflipflop
FLIP - FLOP
- clk’event phaùt hieän söï thay ñoåi tín hieäu clk töø 0 leân 1 hoaëc töø 1 veà 0.- Goùi std_logic_1164 coù ñònh nghóa 2 haøm (function): rising_edge ñeå phaùt hieän caïnh leân vaø falling_edge ñeå phaùt hieän caïnh xuoáng cuûa tín hieäu.
IF rising_edge(clk) THEN
NguyenTrongLuat 56
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY DFF IS
PORT (D, Clk, Pr, Cl : IN STD_LOGIC;
Q, Qn : OUT STD_LOGIC);
END DFF;
ARCHITECTURE behavior OF DFF IS
BEGIN
PROCESS (Clk, Pr, Cl)
BEGIN
IF Pr = ’0’ THEN Q <= ’1’;
Qn <= ’0’;
ELSIF Cl = ’0’ THEN Q <= ’0’;
Qn <= ’1’;
ELSIF Clk’event AND Clk = ’0’ THEN
Q <= D;
Qn <= NOT Q;
END IF;
END PROCESS;
END behavior;
D
Clk
Q
Q
DFF
Pr
Cl
13-Sep-10
29
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY regn IS
GENRERIC (n : NATURAL := 4);
PORT (D : IN STD_LOGIC_VECTOR(n-1 downto 0);
Clk, Reset : _VECTORIN STD_LOGIC;
Q : OUT STD_LOGIC(n-1 downto 0));
END regn;
ARCHITECTURE behavioral OF regn IS
BEGIN
PROCESS (Clk, Reset, D)
BEGIN
IF (Reset = '0') THEN
Q <= (others => '0');
ELSIF rising_edge(Clock) THEN
Q <= D;
END IF;
END PROCESS;
END behavioral; Q <= (Others=> ‘0’) töông ñöông vôùi Q <= “0000”
GENRERIC (n : NATURAL := 4) Khai baùo generic n laø natural (soá nguyeân döông)
NguyenTrongLuat 57
D
Clk
Q
regn
Reset
n n
Thanh ghi (register)
NguyenTrongLuat 58
BOÄ ÑEÁM (COUNTER)
Söû duïng bieán count ñeå thöïc hieän chöùc naêng boä ñeám
LIBRARY ieee;
USE ieee.std_logic_1164.all
USE ieee.std_logic_unsigned.all;
ENTITY Upcnt4 IS
PORT (Clk, Rst : IN STD_LOGIC;
Q: OUT STD_LOGIC_VECTOR(3 downto 0));
END Upcnt4;
ARCHITECTURE Behavioral OF Upcnt4 IS
BEGIN
PROCESS (Clk, Rst)
VARIABLE count: STD_LOGIC_VECTOR (3 downto 0);
BEGIN
IF Rst ='1' THEN
count := (others=>'0');
ELSIF rising_edge(clk) THEN
count := count + "0001";
END IF;
Q <= count;
END PROCESS;
END Behavioral;
BOÄ ÑEÁM LEÂN 4 BITcoù Reset baát ñoàng boä
Bieán count ñöôïc gaùn cho ngoõ ra Q ôû cuoái Process,vì bieán laø giaù trò cuïc boä trong Process
Rst
Clk
Q0
Upcnt4
Q1
Q2
Q3
13-Sep-10
30
LIBRARY ieee;
USE ieee.std_logic_1164.all
USE ieee.std_logic_unsigned.all;
ENTITY Upcnt4 IS
PORT ( Clk, Rst : IN STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR(3 downto 0));
END Upcnt4;
ARCHITECTURE Behavioral OF Upcnt4 IS
SIGNAL count: STD_LOGIC_VECTOR (3 downto 0);
BEGIN
PROCESS (Clk, Rst)
BEGIN
IF rising_edge(clk) THEN
IF Rst ='1' THEN
count <= (others=>'0');
ELSE
count <= count + "0001";
END IF;
END IF;
END PROCESS;
Q <= count;
END Behavioral;
NguyenTrongLuat 59
Boä ñeám coù reset ñoàng boä
Söû duïng tín hieäu count thay cho bieán count.Tín hieäu count ñöôïc gaùn cho ngoõ ra Q beân
ngoaøi Process.
LIBRARY ieee;USE ieee.std_logic_1164.allUSE ieee.std_logic_unsigned.all;ENTITY Upcnt10 IS
PORT ( Clk, Rst : IN STD_LOGIC;Q : OUT STD_LOGIC_VECTOR(3 downto 0));
END Upcnt10;ARCHITECTURE Behavioral OF Upcnt10 ISBEGIN
PROCESS (Clk, Rst)VARIABLE count: STD_LOGIC_VECTOR (3 downto 0);
BEGINIF Rst ='1' THEN
count := (others=>'0'); ELSIF rising_edge(clk) THEN
IF count = "1001" then
count := (others=>'0');
ELSE count := count + "0001";
END IF;
END IF;Q <= count;
END PROCESS; END Behavioral;
NguyenTrongLuat 60
BOÄ ÑEÁM LEÂN THAÄP PHAÂN
13-Sep-10
31
NguyenTrongLuat 61
LIBRARY ieee;
USE ieee.std_logic_1164.all
USE ieee.std_logic_unsigned.all;
ENTITY Updncnt4 IS
PORT ( Clk, Rst, Updn: IN STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR(3 downto 0));
END Updncnt4;
ARCHITECTURE Behavioral OF Updncnt4 IS
SIGNAL count: STD_LOGIC_VECTOR (3 downto 0);
BEGIN
PROCESS (Clk, Rst)
BEGIN
IF Rst = ’1’ THEN
count <= (others =>’0’);
ELSIF rising_edge(Clk) THEN
IF Updn = ’1’ THEN
count <= count + ”0001”;
ELSE count <= count - ”0001”;
END IF;
END IF;
END PROCESS;
Q <= count;
END Behavioral;
BOÄ ÑEÁM 4 bit LEÂN / XUOÁNG
Updn
Clk
Q0
Updncnt4
RstQ1
Q2
Q3
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY sipo IS
GENERIC (n: NATURAL := 8);
PORT (Serin, Clk : IN STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR(
n-1 downto 0));
END sipo;
ARCHITECTURE shiftreg OF sipo IS
SIGNAL reg : STD_LOGIC_VECTOR(n-1 downto 0);
BEGIN
PROCESS (Clk)
BEGIN
IF rising_edge(Clk) THEN
reg <= reg(n-2 downto 0) & Serin;
END IF;
END PROCESS;
Q <= reg;
END shiftreg;
Thanh ghi dòch (shift reg.)
NguyenTrongLuat 62
SIPO
Serin
Clk
Q
sipo
n
13-Sep-10
32
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY siso IS
GENERIC (n : NATURAL := 8);
PORT (Clk, Serin : IN STD_LOGIC;
Serout : OUT STD_LOGIC);
END siso;
ARCHITECTURE shiftreg OF siso IS
SIGNAL reg : STD_LOGIC_VECTOR(n-1 downto 0);
BEGIN
PROCESS (Clk)
BEGIN
IF rising_edge(Clk) THEN
reg <= reg(n-2 downto 0) & Serin;
END IF;
END PROCESS;
Serout <= reg(n-1);
END shiftreg;NguyenTrongLuat 63
SISO
Serin
Clk
siso
Serout
ONguyenTrongLuat 64
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY piso IS
GENERIC (n: NATURAL := 8);
PORT (Serin, Clk, ShLd : IN STD_LOGIC;
D : IN STD_LOGIC_VECTOR(n-1 downto 0);
Serout : OUT STD_LOGIC);
END piso;
ARCHITECTURE shiftreg OF piso IS
SIGNAL reg : STD_LOGIC_VECTOR(n-1 downto 0);
BEGIN
PROCESS (Clk)
BEGIN
IF rising_edge(Clk) THEN
IF ShLd = ’0’ THEN
reg <= D;
ELSE reg <= reg(n-2 downto 0) & Serin;
END IF;
END PROCESS;
Serout <= reg(n-1);
END shiftreg;
SIP
D
Clk
Serout
piso
n
ShLd
Serin
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33
- Maùy traïng thaùi höõu haïn ñöôïc thieát keá deã daøng baèng phaùt bieåu PROCESS.
- Vieäc chuyeån traïng thaùi ñöôïc moâ taû trong Process vôùi danh saùch caûm nhaän (sensitivity list) laø clock vaø tín hieäu reset baát ñoàng boä.
- Ngoõ ra coù theå ñöôïc moâ taû baèng caùc phaùt bieåu ñoàng thôøi (concurrenrt) naèm ngoaøi process.
- Coù 2 kieåu FSM: MOORE vaø MEALY
NguyenTrongLuat 65
MAÙY TRAÏNG THAÙIFSM
MOORE MOORE MOORE MOORE
FSMFSMFSMFSM
Present StateRegister
Next Statefunction
Outputfunction
Inputs
Present StateNext State
Outputs
clockreset
Next state function: haøm traïng thaùi keá tieáp laø maïch toå hôïp phuï thuoäc vaøo ngoõ vaøo vaø traïng thaùi hieän taïi
Output function: haøm ngoõ ra laø maïch toå hôïp phuï thuoäc vaøo traïng thaùi hieän taïi
Present State Register: thanh ghi traïng thaùi hieän taïi löu giöõ 1 traïng thaùi hieän taïi, seõ chuyeån traïng thaùi khi coù xung clock.
NguyenTrongLuat 66
13-Sep-10
34
Present StateRegister
Next Statefunction
Outputfunction
Inputs
Present StateNext State
Outputs
clock
resetProcess Thanh ghi traïng thaùi:PROCESS (reset, clock)
Process Haøm traïng thaùi keá tieáp:PROCESS (input, present_state)
Process Haøm ngoõ ra:PROCESS (present_state)
Concurrent Statements
FSM kieåu MOORE ñöôïc moâ taû baèng 3 PROCESS
- Process Haøm ngoõ ra coù theå thay theá baèng caùc phaùt bieåu ñoàng thôøi (concurrent statement)
NguyenTrongLuat 67
- Process 2 vaø 3 coù theå keát hôïp thaønh 1 Process.
LIBRARY ieee;
USE iee.std_logic_1164.all;
ENTITY Moore_FSM IS
PORT (clock, rerset, input: IN std_logic;
output: OUT std_logic);
END Moore_FSM;
ARCHITECTURE behavior OF Moore_FSM IS
TYPE state IS (list of states);
SIGNAL pr_state, nx_state: state;
BEGIN
PROCESS(clk, reset)
BEGIN
IF reset = ’1’ THEN
pr_state <= reset state;
ELSIF (clock = ’1’ and clock’event) THEN
pr_state <= nx_state;
END IF;
END PROCESS;
TYPE state IS (list of states): khai baùo state laø döõ lieäu kieåu lieät keâNguyenTrongLuat 68
Process Thanh ghi traïng thaùi:PROCESS (reset, clock)
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35
PROCESS (input, ps_state )
CASE ps_state IS
WHEN state_1 =>
IF input = ’…’ THEN
nx_state <= state_2;
ELSIF nx_state <= state_3;
END IF;
WHEN state_2 =>
IF input = ’…’ THEN
nx_state <= state_1;
ELSIF nx_state <= state_3;
END IF;
. . .
END CASE;
END PROCESS;
NguyenTrongLuat 69
Process Haøm traïng thaùi keá tieáp:PROCESS (input, present_state)
PROCESS(ps_state )
CASE ps_state IS
WHEN state_1 =>
output <= ’...’;
WHEN state_2 =>
output <= ’...’;
...
END CASE;
END PROCESS;
Coù theå duøng phaùt bieåu IF … THEN …
NguyenTrongLuat 70
Process Haøm ngoõ ra:PROCESS (present_state)
Coù theå thay theá process naøy baèng phaùt bieåu ñoàng thôøioutput <= ... ;
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36
TT hieän taïi
TT keá tieáp Ngoõ ra (z)x = 0 x = 1
LIBRARY ieee;USE iee.std_logic_1164.all;ENTITY Moore_FSM ISPORT (
clock, rerset, x: IN std_logic;z: OUT std_logic);
END Moore_FSM;ARCHITECTURE behavior OF Moore_FSM ISTYPE state IS (S0, S1, S2, S3);SIGNAL pr_state, nx_state: state;
BEGINregst: PROCESS(clk, reset)BEGIN
IF reset = ’1’ THEN pr_state <= S0;ELSIF (clock = ’1’ and clock’event) THEN
pr_state <= nx_state;END IF;
END PROCESS;
S0S1S2S3
S0S2S0S2
S1S1S3S1
0001
NguyenTrongLuat 71
nxst: PROCESS (x, ps_state )CASE ps_state ISWHEN S0 =>
IF x = ’0’ THENnx_state <= S0;
ELSIF nx_state <= S1;END IF;
WHEN S1 =>IF x = ’0’ THEN nx_state <= S2;ELSIF nx_state <= S1;
END IF;WHEN S2 =>
IF x = ’0’ THEN nx_state <= S0;ELSIF nx_state <= S3;
END IF;WHEN S3 =>
IF x = ’0’ THEN nx_state <= S2;ELSIF nx_state <= S1;
END IF;END CASE;
END PROCESS;
TT hieän taïi
TT keá tieáp Ngoõ ra (z)x = 0 x = 1
S0S1S2S3
S0S2S0S2
S1S1S3S1
0001
NguyenTrongLuat 72
13-Sep-10
37
TT hieän taïi
TT keá tieáp Ngoõ ra (z)x = 0 x = 1
S0S1S2S3
S0S2S0S2
S1S1S3S1
0001
Output: PROCESS(ps_state )
CASE ps_state IS
WHEN S3 =>
z <= ’1’;
WHEN OTHERS =>
z <= ’0’;
END CASE;
END PROCESS;
END behavior;
Output: PROCESS(ps_state )
IF ps_state = S3 THEN z <= ’1’;
ELSE ’0’;
END IF;
z <= ’1’ WHEN ps_state = S3 ELSE ’0’;
NguyenTrongLuat 73
NguyenTrongLuat 74
Keát hôïp Process 2 vaø 3 thaønh 1 Process
TT hieän taïi
TT keá tieáp Ngoõ ra (z)x = 0 x = 1
S0S1S2S3
S0S2S0S2
S1S1S3S1
0001
nx_out: PROCESS (x, ps_state )CASE ps_state ISWHEN S0 =>
z <= ’0’;IF x = ’0’ THEN
nx_state <= S0;ELSIF nx_state <= S1;
END IF;WHEN S1 =>
z <= ’0’;IF x = ’0’ THEN nx_state <= S2;ELSIF nx_state <= S1; END IF;
WHEN S2 =>z <= ’0’;IF x = ’0’ THEN nx_state <= S0;ELSIF nx_state <= S3; END IF;
WHEN S3 =>z <= ’1’;IF x = ’0’ THEN nx_state <= S2;ELSIF nx_state <= S1; END IF;
END CASE;END PROCESS;
END behavior;
13-Sep-10
38
Present State
Present StateRegister
Next Statefunction
Outputfunction
Inputs
Next State
Outputs
clock
reset Process Thanh ghi traïng thaùi:PROCESS (reset, clock)
Process Haøm traïng thaùi keá tieáp vaø Ngoõ ra:
PROCESS (input, present_state)
FSM kieåu MEALY ñöôïc moâ taû baèng 2 PROCESS
NguyenTrongLuat 75
MEALY MEALY MEALY MEALY
FSMFSMFSMFSM
PROCESS (input, ps_state )
CASE ps_state IS
WHEN state_1 =>
IF input = ’…’ THEN
output <= ’...’;
nx_state <= state_2;
ELSIF
output <= ’...’;
nx_state <= state_3;
END IF;
. . .
END CASE;
END PROCESS;
NguyenTrongLuat 76
Process Haøm traïng thaùi keá tieáp vaø Ngoõ ra:PROCESS (input, present_state)
13-Sep-10
39
nx_out: PROCESS (x, ps_state )CASE ps_state IS
WHEN S0 => IF x = ’0’ THEN
z <= ’0’;nx_state <= S0;
ELSIF z <= ’0’;nx_state <= S1;
END IF;WHEN S1 =>
IF x = ’0’ THEN z <= ’0’;nx_state <= S2;
ELSIF z <= ’0’;nx_state <= S1;
END IF;WHEN S2 =>
IF x = ’0’ THEN z <= ’0’;nx_state <= S2;
ELSIF z <= ’0’;nx_state <= S1;
END IF;END CASE;
END PROCESS;
TT HT
TT keá tieáp Ngoõ ra (Z)
X = 0 1 X = 0 1
S0S1S2
S0S2S2
S1S1S1
000
001
NguyenTrongLuat 77
- Vieäc gaùn traïng thaùi thöôøng laø töï ñoäng.
- Ta coù 2 caùch ñeå gaùn cho moãi traïng thaùi baèng 1 toå hôïp nhò phaân:
TYPE state IS (S0, S1, S2);
SIGNAL pr_state, nx_state: state;
TYPE state IS STD_LOGIC_VECTOR(1 downto 0);
CONSTANT S0: state:= ”00”;
CONSTANT S1: state:= ”01”;
CONSTANT S2: state:= ”11”;
SIGNAL pr_state, nx_state: state;
* Söû duïng thuoäc tính (attribute) enum_encoding:TYPE state IS (S0, S1, S2);
ATTRIBUTE ENUM_ENCODING: STRING;
ATTRIBUTE ENUM_ENCODING OF state: TYPE IS ”00 01 11”;
SIGNAL pr_state, nx_state: state;
Gán trạng thái
* Khai baùo constant
NguyenTrongLuat 78
13-Sep-10
40
Phaùt bieåu WAIT
- WAIT laø phaùt bieåu tuaàn töï (sequential statement). - Neáu Process khoâng coù danh saùch caûm nhaän (sensitivity list) thì phaùt bieåu WAIT laø phaùt bieåu ñaàu tieân cuûa Process
WAIT UNTIL condition_signal;
WAIT ON sensitivity_list;
WAIT FOR time;
Process ñöôïc thöïc thi khi coù söï thay ñoåi giaù trò cuûa 1 hoaêc nhieàu tín hieäu trong danh saùch caûm nhaän
Process ñöôïc thöïc thi khi coù ñieàu kieän cuûa 1 tín hieäu xaåy ra (true)
Chæ duøng trong moâ phoûng (testbench). Taïm döøng thöïc hieän Process trong 1 khoaûng thôøi gian (time).
NguyenTrongLuat 79
NguyenTrongLuat 80
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY Dlatch IS
PORT (D, Clk : IN STD_LOGIC;
Q, Qn : OUT STD_LOGIC);
END Dlatch;
ARCHITECTURE behavior OF Dlatch IS
BEGIN
PROCESS (D, Clk)
BEGIN
IF Clk = ’1’ THEN
Q <= D;
Qn <= NOT Q;
END IF;
END PROCESS;
END behavior;
ARCHITECTURE behavior OF Dlatch IS
BEGIN
PROCESS
BEGIN
WAIT ON Clk, D;
IF Clk = ’1’ THEN
Q <= D;
Qn <= NOT Q;
END IF;
END PROCESS;
END behavior;
D
Clk
Q
Q
Dlatch
13-Sep-10
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NguyenTrongLuat 81
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY Dflipflop IS
PORT (D, Clk : IN STD_LOGIC;
Q, Qn : OUT STD_LOGIC);
END Dflipflop;
ARCHITECTURE behavior OF Dflipflop IS
BEGIN
PROCESS (Clk)
BEGIN
IF Clk’event AND Clk = ’1’ THEN
Q <= D;
Qn <= NOT Q;
END IF;
END PROCESS;
END behavior;
ARCHITECTURE behavior OF Dflipflop IS
BEGIN
PROCESS
BEGIN
WAIT UNTIL Clk’event AND Clk = ’1’;
Q <= D; Qn <= NOT Q;
END PROCESS;
END behavior;
D
clk
Q
Q
Dflipflop