l3cmbintlverilog(1)

8/13/2019 l3cmbintlverilog(1)

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L3: Introduction toL3: Introduction to VerilogVerilog(Combinational Logic)(Combinational Logic)

Courtesy ofRex Min. Used with permission.

Verilog References:

Samir Palnitkar, Verilog HDL, Pearson Education (2nd edition).

Donald Thomas, Philip Moorby, The Verilog Hardware Description Language, Fifth

Edition, Kluwer Academic Publishers.

J. Bhasker, Verilog HDL Synthesis (A Practical Primer), Star Galaxy Publishing

L3: 6.111 Spring 2004 Introductory Digital Systems Laboratory 1


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Synthesis andSynthesis and HDLsHDLs Hardware description language (HDL) is a convenient, device-

independent representation of digital logic

Verilog

input a,b;output sum;

assign sum


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The FPGA: A Conceptual ViewThe FPGA: A Conceptual View An FPGA is like an electronic breadboard that is wired together

by an automated synthesis tool

Built-in components are called macros

sel

interconnect

D Q

LUT

F(a,b,c,d)

G(a,b,c,d)

ab

cd

RAMADR

R/WDATA

counter

+

32

32

32SUM

(for everything else)



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Synthesis and Mapping forSynthesis and Mapping for FPGAsFPGAs Infer macros: choose the FPGA macros that efficiently

implement various parts of the HDL code

counter

...

always @ (posedge clk)begin

count


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VerilogVerilog: The Module: The Module Verilog designs consist of

interconnected modules.

A module can be an element orcollection of lower level design blocks.

A simple module with combinationallogic might look like this: Out = sel a + sel b

1

0

sel

out

outbar

a

b

2-to-1 multiplexer with inverted output

modulemux_2_to_1(a,b,out, Declare and name a module; list itsoutbar,sel); ports. Dont forget that semicolon.

//Thisis2:1multiplexor

inputa,b,sel;

outputout,outbar;

Comment starts with //

Verilog skips from // to end of the lineSpecify each port as input, output,or inoutExpress the modules behavior.

assignout=sel?a:b;Each statement executes in

assignoutbar=~out; parallel; order does not matter.

endmodule Conclude the module code.



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Continuous (Dataflow) AssignmentContinuous (Dataflow) Assignmentmodulemux_2_to_1(a,b,out,

outbar,sel); ainputa,b,sel;

1

0

outoutputout,outbar; b outbarassignout=sel?a:b;

assignoutbar=~out; selendmodule

Continuous assignments use the assignkeyword A simple and natural way to represent combinational logic Conceptually, the right-hand expression is continuously evaluated as a function of

arbitrarily-changing inputsjust like dataflow

The target of a continuous assignment is a net driven by combinational logic Left side of the assignment must be a scalar or vector net or a concatenation of scalar

and vector nets. It cant be a scalar or vector register (discussed later). Right side can beregister or nets

Dataflow operators are fairly low-level: Conditional assignment: (conditional_expression) ? (value-if-true) : (value-if-false); Boolean logic: ~, &, | Arithmetic: +, -, *

Nested conditional operator (4:1 mux) assignout=s1?(s0?i3:i2):(s0?i1:i0);



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MAX+plusIIMAX+plusII: Simulator, Synthesis, Mapping: Simulator, Synthesis, Mapping Must be synthesizable Verilog files Step by step instructions on the course WEB site

Glitch

Create *.v file (module name same as file name)

Select area and set inputs through overwrite or insert menu (under edit)



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Gate Level DescriptionGate Level Descriptionmodulemuxgate(a,b,out,outbar,sel);inputa,b,sel;outputout,outbar;

wireout1,out2,selb;

anda1(out1,a,sel);noti1(selb,sel);

out

sel

a

b

out1

out2selb

outbaranda2(out2,b,selb);oro1(out,out1,out2);assignoutbar=~out;

endmodule

Verilog supports basic logic gates as primitivesand,nand,or,nor,xor,xnor,not,bufcan be extended to multiple inputs: e.g., nandnand3in (out, in1, in2,in3);bufif1and bufif0are tri-state buffers

Net represents connections between hardware elements. Nets aredeclared with the keywordwire.



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Procedural Assignment withProcedural Assignment with alwaysalways

Procedural assignment allows an alternative, often higher-level, behavioraldescription of combinational logic

Two structured procedure statements: initialand always Supports richer, C-like control structures such as if, for,while,casemodulemux_2_to_1(a,b,out,

outbar,sel); Exactly the same as before.inputa,b,sel;outputout,outbar;

Anything assigned in an alwaysregout,outbar; block must also be declared as

type reg(nextslide)

always@(aorborsel)

begin

if(sel)out=a;elseout=b;

outbar=~out;

end

endmodule

Conceptually, the alwaysblockruns once whenever a signal in thesensitivity list changes value

Statements within the alwaysblock are executed sequentially.Order matters!

Surround multiple statements in asingle alwaysblock with begin/end.



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VerilogVerilog RegistersRegisters In digital design, registers represent memory elements (we

will study these in the next few lectures)

Digital registers need a clock to operate and update theirstate on certain phase or edge

Registers in Verilog should not be confused with hardwareregisters

In Verilog, the term register (reg) simply means a variablethat can hold a value

Verilog registers dont need a clock and dont need to bedriven like a net. Values of registers can be changedanytime in a simulation by assuming a new value to theregister



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MixMix--andand--Match AssignmentsMatch Assignments Procedural and continuous assignments can (and often do) co-existwithin a module Procedural assignments update the value of reg. The value will remain

unchanged till another procedural assignment updates the variable.This is the main difference with continuous assignments in which theright hand expression is constantly placed on the left-side

modulemux_2_to_1(a,b,out,

outbar,sel);inputa,b,sel;outputout,outbar;regout;

always@(aorborsel)

beginif(sel)out=a;elseout=b;

end

assignoutbar=~out;

proceduraldescription

continuousdescription

1

0

sel

out

a

b outbar

endmodule



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TheThe casecase StatementStatement caseand ifmay be used interchangeably to implement

conditional execution within alwaysblocks

caseis easier to read than a long string of if...elsestatementsmodulemux_2_to_1(a,b,out,

outbar,sel);inputa,b,sel;outputout,outbar;regout;

modulemux_2_to_1(a,b,out,outbar,sel);

inputa,b,sel;outputout,outbar;regout;

always@(aorborsel) always@(aorborsel)begin beginif(sel)out=a; case(sel)elseout=b; 1b1:out=a;

end 1b0:out=b;endcase

assignoutbar=~out; end

endmodule assignoutbar=~out;

endmodule

Note: Number specification notation:

(4b1010 if a 4-bit binary value, 16h6cda is a 16 bit hex number, and 8d40 is an 8-bit decimal value)L3: 6.111 Spring 2004 Introductory Digital Systems Laboratory 12


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The Power ofThe Power of VerilogVerilog:: nn--bit Signalsbit Signals Multi-bit signals and buses are easy in Verilog. 2-to-1 multiplexer with 8-bit operands:

modulemux_2_to_1(a,b,out,

outbar,sel);input[7:0]a,b;

1

0

8inputsel;output[7:0]out,outbar; a 8reg[7:0]out; out

always@(aorborsel) boutbarbegin 8 8

if(sel)out=a;selelseout=b;

end

assignoutbar=~out;

endmodule

assign{b[7:0],b[15:8]}={a[15:8],a[7:0]};

effects a byte swap

Concatenate signals using the { } operator



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The Power ofThe Power of VerilogVerilog: Integer Arithmetic: Integer Arithmetic Verilogs built-in arithmetic makes a 32-bit adder easy:

moduleadd32(a,b,sum);input[31:0]a,b;

output[31:0]sum;assignsum=a+b;endmodule

A 32-bit adder with carry-in and carry-out:

moduleadd32_carry(a,b,cin,sum,cout);

input[31:0]a,b;inputcin;

output[31:0]sum;outputcout;assign{cout,sum}=a+b+cin;

endmodule



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Dangers ofDangers of VerilogVerilog: Incomplete Specification: Incomplete SpecificationGoal: Proposed Verilog Code:

00

sel

out01

10

a

b

c

2

3-to-1 MUX(11 input is a dont-care)

modulemaybe_mux_3to1(a,b,c,sel,out);

input[1:0]sel;inputa,b,c;outputout;regout;

always@(aorborcorsel)

begincase(sel)2'b00:out=a;2'b01:out=b;2'b10:out=c;

endcaseend

endmodule

Is this a 3-to-1 multiplexer?



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Incomplete Specification Infers LatchesIncomplete Specification Infers Latchesmodulemaybe_mux_3to1(a,b,c, Synthesized Result:

sel,out);input[1:0]sel;inputa,b,c;outputout; aregout;

b

00

sel

01

10

2

D Q

G

sel[1]

sel[0]

outalways@(aorborcorsel)begin ccase(sel)

2'b00:out=a;

2'b01:out=b;2'b10:out=c;endcase

endendmodule

if outis not assignedduring any pass through

the always block, then the

previous value must be

retained!

Latch memory latchesold data when G=0 (wewill discuss latches later)

In practice, we almostnever intend this


A idi I l S ifi i


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Avoiding Incomplete SpecificationAvoiding Incomplete Specification

Precede all conditionalswith a default assignmentfor all signals assignedwithin them

always@(aorborcorsel)beginout=1bx;case(sel)

2'b00:out=a;2'b01:out=b;2'b10:out=c;

endcaseend

endmodule

always@(aorborcorsel)begin or, fully specify allcase(sel) branches of conditionals and

2'b00:out=a;assign all signals from all

2'b01:out=b;2'b10:out=c; branchesdefault:out=1bx;

For each if, include elseendcaseend For each case, include default

endmodule


D fD f V ilV il P i i L iP i it L i


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Dangers ofDangers of VerilogVerilog: Priority Logic: Priority LogicGoal: Proposed Verilog Code:

I3I2I1I0

4-to-2 Binary Encoder

E1E0

1

0

0

1

0

0

I3 I2 I1 I0

0 0 0 1

0 0 1 0

0 1 0 01 0 0 0

all others

E1 E0

0 0

0 1

1 01 1

X X

modulebinary_encoder(i,e);

input[3:0]i;output[1:0]e;rege;

always@(i)begin

if(i[0])e=2b00;elseif(i[1])e=2b01;elseif(i[2])e=2b10;elseif(i[3])e=2b11;elsee=2bxx;

endendmodule

What is the resulting circuit?


P i it L iP i it L i


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Priority LogicPriority LogicIntent: if more than one input is

1, the result is a dont-care.I3 I2 I1 I0 E1 E0

0 0 0 1 0 0

0 0 1 0 0 10 1 0 0 1 0

1 0 0 0 1 1

all others X X

Code: if i[0] is 1, the result is 00regardless of the other inputs.

i[0] takes the highest priority.

if(i[0])e=2b00;elseif(i[1])e=2b01;elseif(i[2])e=2b10;elseif(i[3])e=2b11;elsee=2bxx;end

1

i[0]

0

2b001

i[1]

0

2b011

i[2]

0

2b101

i[3]

0

2b11

2bxxe[1:0]

Inferred

Result:

if-elseand casestatements are interpreted very literally!Beware of unintended priority logic.


A idi (U i t d d) P i it L iA idi (U i t d d) P i it L i


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Avoiding (Unintended) Priority LogicAvoiding (Unintended) Priority Logic Make sure that if-elseand casestatements areparallel

If mutually exclusive conditions are chosen for each branch......then synthesis tool can generate a simpler circuit that evaluates

the branches in parallel

Parallel Code: Minimized Result:

modulebinary_encoder(i,e);input[3:0]i;

output[1:0]e;rege;

always@(i)beginif(i==4b0001)e=2b00;

elseif(i==4b0010)e=2b01;elseif(i==4b0100)e=2b10;elseif(i==4b1000)e=2b11;elsee=2bxx;

I3

I1I0

E0

E1

endendmodule


I t ti M d lInterconnecting Mod les


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Interconnecting ModulesInterconnecting Modules

Modularity is essential to the success of large designs A Verilogmodulemay contain submodules that are wired together High-level primitives enable direct synthesis of behavioral descriptions (functions such

as additions, subtractions, shifts (>), etc.

Example: A 32-bit ALU Function TableA[31:0] B[31:0]

+ - *

0 1 0 1

32d1 32d1

00 01 10

F[0]

F[2:1]

F2 F1 F0

0 0 00 0 10 1 0

F[2:0] 0 1 11 0 X

FunctionA + B

A + 1

A - B

A - 1

A * B

R[31:0]


Module DefinitionsModule Definitions


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Module DefinitionsModule Definitions2-to-1 MUX 3-to-1 MUX

modulemux32two(i0,i1,sel,out);modulemux32three(i0,i1,i2,sel,out);input[31:0]i0,i1,i2;

input[31:0]i0,i1; input[1:0]sel;inputsel; output[31:0]out;output[31:0]out; reg[31:0]out;

assignout=sel?i1:i0; always@(i0ori1ori2orsel)begin

endmodule case(sel)2b00:out=i0;2b01:out=i1;2b10:out=i2;default:out=32bx;

endcaseendendmodule

32-bit Adder 32-bit Subtracter 16-bit Multiplier

modulemul16(i0,i1,prod);moduleadd32(i0,i1,sum); modulesub32(i0,i1,diff); input[15:0]i0,i1;input[31:0]i0,i1; input[31:0]i0,i1; output[31:0]prod;output[31:0]sum; output[31:0]diff;

//thisisamagnitudemultiplierassignsum=i0+i1; assigndiff=i0- i1; //signedarithmeticlater

assignprod=i0*i1;endmodule endmodule

endmodule


TopTop Level ALU DeclarationLevel ALU Declaration


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TopTop--Level ALU DeclarationLevel ALU DeclarationA[31:0] B[31:0]

Given submodules: alumodulemux32two(i0,i1,sel,out);modulemux32three(i0,i1,i2,sel,out);

moduleadd32(i0,i1,sum);

modulesub32(i0,i1,diff);

modulemul16(i0,i1,prod);+ - *

0 1 0 1

32d1 32d1

00 01 10

F[0]

F[2:1]

F[2:0] Declaration of the ALU Module:

modulealu(a,b,f,r);

input[31:0]a,b;

input[2:0]f;

output[31:0]r; R[31:0]wire[31:0]addmux_out,submux_out;

wire[31:0]add_out,sub_out,mul_out;

mux32two adder_mux(b,32'd1,f[0],addmux_out);

mux32two sub_mux(b,32'd1,f[0],submux_out);

add32 our_adder(a,addmux_out,add_out);sub32 our_subtracter(a,submux_out,sub_out);

mul16 our_multiplier(a[15:0],b[15:0],mul_out);

mux32threeoutput_mux(add_out,sub_out,mul_out,f[2:1],r);

endmodule module

names

(unique)

instancenames

corresponding

wires/regs inmodule alu

intermediate output nodes


SimulationSimulation


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SimulationSimulation

addition subtraction multiplier


More on Module InterconnectionMore on Module Interconnection


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More on Module InterconnectionMore on Module Interconnection Explicit port naming allows port mappings in arbitrary

order: better scaling for large, evolving designs

Given Submodule Declaration:

modulemux32three(i0,i1,i2,sel,out);

Module Instantiation with Ordered Ports:

mux32threeoutput_mux(add_out,sub_out,mul_out,f[2:1],r);

Module Instantiation with Named Ports:

mux32threeoutput_mux(.sel(f[2:1]),.out(r),.i0(add_out),

.i1(sub_out),.i2(mul_out));

submodulesport name

correspondingwire/reg in

outer module

Built-in Verilog gate primitives may be instantiated as wellInstantiations may omit instance name and must be ordered:

buf(out1,out2,...,outN, in); and(in1,in2,...inN,out);


Useful Boolean OperatorsUseful Boolean Operators


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Useful Boolean OperatorsUseful Boolean Operators Bitwise operators perform bit-sliced operations on vectors

~(4b0101) = {~0,~1,~0,~1} = 4b10104b0101 & 4b0011 = 4b0001

Logical operators return one-bit (true/false) results !(4b0101) = ~1 = 1b0

Reduction operators act on each bit of a single input vector &(4b0101) = 0 & 1 & 0 & 1 = 1b0

Comparison operators perform a Boolean test on two argumentsBitwise Logical Reduction Comparison

~a NOT

a & b AND

a | b OR

a ^ b XOR

a ~^ b XNOR

!a NOT

a && b AND

a || b OR

&a AND

~& NAND

| OR

~| NOR^ XOR

a < ba > b

a = b

a == ba != b [in]equalityreturns x when x

or z in bits. Elsereturns 0 or 1

a === b casea !== b [in]equality

returns 0 or 1based on bit by bitcomparison

Note distinction between ~a and !a


TestbenchesTestbenches ((ModelSimModelSim)) DemoDemo


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L3: 6.111 Spring 2004 27Introductory Digital Systems Laboratory

(( ))this week in Lab by TAsthis week in Lab by TAs

module full_adder (a, b, cin,sum, cout);

input a, b, cin;

output sum, cout;

reg sum, cout;

always @(a or b or cin)

begin

sum = a ^ b ^ cin;cout = (a & b) | (a & cin) | (b & cin);

end

Endmodule

module full_adder_4bit (a, b, cin, sum,cout);

input[3:0] a, b;

input cin;

output [3:0] sum;

output cout;

wire c1, c2, c3;

// instantiate 1-bit addersfull_adder FA0(a[0],b[0], cin, sum[0], c1);

full_adder FA1(a[1],b[1], c1, sum[1], c2);

full_adder FA2(a[2],b[2], c2, sum[2], c3);

full_adder FA3(a[3],b[3], c3, sum[3], cout);

endmodule

Full Adder (1-bit) Full Adder (4-bit) Testbench

ModelSim Simulation

module test_adder;reg [3:0] a, b;

reg cin;

wire [3:0] sum;

wire cout;

full_adder_4bit dut(a, b, cin,

sum, cout);

initial

begin

a = 4'b0000;

b = 4'b0000;

cin = 1'b0;

#50;

a = 4'b0101;

b = 4'b1010;// sum = 1111, cout = 0

#50;

a = 4'b1111;

b = 4'b0001;

// sum = 0000, cout = 1

#50;

a = 4'b0000;

b = 4'b1111;cin = 1'b1;

// sum = 0000, cout = 1

#50;

a = 4'b0110;

b = 4'b0001;

// sum = 1000, cout = 0

end // initial begin

endmodule // test_adder

Courtesy of Francis A. Honore. Used with permission.

SummarySummary


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SummarySummary Multiple levels of description: behavior, dataflow, logic and

switch (not used in 6.111)

Gate level is typically not used as it requires working outthe interconnects

Continuous assignment using assignallows specifyingdataflow structures

Procedural Assignment using alwaysallows efficientbehavioral description. Must carefully specify thesensitivity list

Incomplete specification of caseor ifstatements canresult in non-combinational logic

Verilog registers (reg) is not to be confused with ahardware memory element

Modular design approach to manage complexityL3: 6.111 Spring 2004 Introductory Digital Systems Laboratory 28

l3cmbintlverilog(1)

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