MZ - ESD L8/28/9/2012

Complex FSM

State Assignment problem State Minimisation ASM charts (Algorithmic state machines)

1

MZ - ESD L8/28/9/2012

State-Assignment Problem: Impact of the assignment of binary codes to states

when designing a finite state machine.

Let us again consider an FSM that recognizes two consecutive 1s (i.e., looks for the pattern 11)

State Diagram:

C z 1 =

Reset

B z 0 = A z 0 = w 0 =

w 1 =

w 1 =

w 0 = w 0 = w 1 =

2

Q

Q

MZ - ESD L8/28/9/2012

Version 1: Ascending Sequence

2 flip flops 3 gates + 7 gate inputs

Present Next state

state w = 0 w = 1 Output

y 2 y 1 Y 2 Y 1 Y 2 Y 1 z

A 00 00 01 0 B 01 00 10 0 C 10 00 10 1

11 -- -

D Q

D Q

Y 2

Y 1 w

Clock

z

y 1

y 2

Resetn

3

--

Q

Q

MZ - ESD L8/28/9/2012

Version 2: Gray Code

2 flip flops 1 gate + 2 gate inputs

D Q

D Q

Y 2

Y 1 w

Clock

z

y 1

y 2

Resetn

Present Next state

state w = 0 w = 1 Output

y 2 y 1 Y 2 Y 1 Y 2 Y 1 z

A 00 00 01 0 B 01 00 11 0 C 11 00 11 1

10 -- -- -

4

MZ - ESD L8/28/9/2012

One-Hot Encoding

Each state variable gets its own flip flop.

If machine is in state Q, flip flop Q is 1, else 0.

At any given time, only one flip flop is 1 therefore the states are one hot encoded.

Can result in less combinational logic at the expense of more flip-flops.

5

MZ - ESD L8/28/9/2012

Why might we want to do this? If we do not have many states, it can significantly simplify the logic

required for the state transitions and decoding the outputs. Having one variable for each state has automatically decoded.

If we consider counters, the previous approach corresponds to a binary counter, and the one-hot approach corresponds to a ring counter, where each of the outputs becomes active in turn.

If we actually want the decoded outputs, a ring counter is actually simpler than a binary counter with additional decoding logic, especially if we only have a small number of states.

6

One-Hot Encoding

MZ - ESD L8/28/9/2012

We can derive the required logic directly from inspection of the state transition diagram. A state becomes active whenever a transition ends in that state, therefore we can write an expression combining all of the transitions entering a state:

It is important to include the from state as well as the transition conditions with each of the terms.

7

One-Hot Encoding

MZ - ESD L8/28/9/2012

The above list of equations is suitable when using a D latch.If using RS (or JK) latches, the conditions are a little different.We need to set the latch on transitions coming into a state, and reset the latch on transitions leaving a state.We do not need to worry about transitions looping back to the current state.

X

One-Hot Encoding

MZ - ESD L8/28/9/2012

While this might seem like more logic, every transition that leaves one state enters another state, so this will reduce the logic needed. Output decoding can also be done by inspection from the state transition diagram:

8

One-Hot Encoding

MZ - ESD L8/28/9/2012

The choice between a coded representation, and a one-hot representation really comes down to complexity and available resources.

With octal latches available, a discrete component one-hot representation may be economical up to about 8 states, depending on the complexity of the transitions.

The main advantage of the one-hot design approach, however, is that the logic of the finite state machine is usually much easier to follow (if the FSM is not too complex!!) and the resulting FSM is very fast.

9

One-Hot Encoding

MZ - ESD L8/28/9/2012

Mpx-based State Machines

Another alternative to implementing finite state machines is through the use of multiplexers.

A multiplexer can be used to implement any arbitrary function by connecting the inputs appropriately.

Recall that a multiplexer selects one of several inputs based on a set of control signals.

Therefore by putting appropriate levels on the inputs, we can directly implement a truth table.

X

MZ - ESD L8/28/9/2012

Mpx-based State Machines

We can take the output column from the truth table and apply directly to the inputs of a multiplexer. The input signals provide the control signals that select the corresponding input.

X

MZ - ESD L8/28/9/2012

Mpx-based State Machines

The input signals do not have to be just 0 and 1 they can also be other signals.

For example for our voting circuit we could use a multiplexer on 2 of the variables (eg A and B) and apply the third variable to the input.

For the input, the output corresponds to C, so we apply C to the corresponding input to the multiplexer.

Similarly for the input.

X

MZ - ESD L8/28/9/2012

Summarizing

In summary, some logic functions may be easier to implement with multiplexers than with individual gates. This may be especially so if we have some awkward functions, and would require quite a few chips to implement the function. So, how do multiplexers help us in designing finite state machines?

Well, we could use the multiplexers in place of all of the combinatorial logic that is required to implement the state machine.

However, it is more usual to use the multiplexers to decode the state variables.

This effectively allows us to simplify the design with coded state variables.

X

MZ - ESD L8/28/9/2012

Simplified design with coded statevariables - 1

This is shown on the right for 2 state variables. With the multiplexers based on the current state, we need to code the next state based on the inputs

The state variables do not appear in the equations because the multiplexer takes care of that. We only select inputs based on the state we are in. So what we need to code is all of the transitions leaving a given state.

We have one multiplexer for each state variable, so we need to design the logic for the next state variable for each of the current states.

X

MZ - ESD L8/28/9/2012

Simplified design with coded statevariables - 2

Looking at the traffic lightexample:

In state 00, in all of the next states Xn=0, and Yn=T.P In state 01 we always transition to state 10, ie Xn=1 and Yn=0 In state 10, in all of the next states, Xn=1, and Yn= \P +T.F Finally in state 11, we always transition to state 00, ie Xn=0, and Yn=0.

X

MZ - ESD L8/28/9/2012

Simplified design with coded statevariables - 3

Putting these into the multiplexers gives the figure opposite: The outputs can be decoded as before, or by using a 2 to 1-of-4 decoder and decoding directly as with the one-hot state machine. The main advantage of the multiplexed design is a lower chip count for the implementation (when using discrete logic). Often the logic is also easier to see than with discrete components, although this is not as clear as the one-hot approach.

X

MZ - ESD L8/28/9/2012

State Minimization

Definition: Two states are equivalent iff same output sequence for the same input sequence starting at either state.

Partitioning Minimization Procedure.

Definition: Let a partition be a set of blocks, each block comprising a subset of states that might be equivalent. A given state is in a single block and is definitely NOT equivalent to any state in any other block.

10

MZ - ESD L8/28/9/2012

Example P1 = (ABCDEFG) consider output at each state P2 = (ABD)(CEFG) consider w=0, 0-successors: (ABD) => (BDB) (CEFG) => (FFEF) consider w=1, 1-successors: (ABD) => (CFG) (CEFG) => (ECDG) P3 = (ABD)(CEG)(F) consider 0-successors: (ABD) => (BDB) consider 1-successors: (ABD) => (CFG) P4 = (AD)(B)(CEG)(F)

Present Next state Outputstate w = 0 w = 1 z

A B C 1 B D F 1 C F E 0 D B G 1 E F C 0 F E D 0 G F G 0

11

MZ - ESD L8/28/9/2012

Resulting State Table

where: A := (AD) B := (B) C := (CEG) F := (F)

Present Nextstate Outputstate w = 0 w = 1 z

A B C 1 B A F 1 C F C 0 F C A 0

12

MZ - ESD L8/28/9/2012

Final words on FSM Optimization

Incompletely specified FSMs Partitioning depends upon outputs assumed for dont cares.

May not find the minimum number of states required. Can use definition of equivalence directly [not in this course].

State assignment may have more impact than state minimization!

In practice Let CAD tools decide. In this course Life is not so easy.

13

MZ - ESD L8/28/9/2012

ASM charts

Algorithmic State Machine Charts

Type of flow chart, useful for designing complex state machines.

Three types of elements used: State Box : Name outside, top left; Moore Output: inside;

only list signals to be asserted. Write z instead of z=1. Or, write action to be taken, e.g.,: count count +1 (which might just be short hand for a datapath input signal inc)

Decision Box : Condition expression inside a diamond; expression consists of one or more inputs to FSM. Exit path chosen accordingly.

Conditional Output Box : Actually, an oval. Inside contains a list of Mealy outputs. Preceded by decision box where necessary.

14

MZ - ESD L8/28/9/2012

Output signalsor actions

(Moore type)

State name

Condition expression

0 (False) 1 (True)

Conditional outputs or actions (Mealy type)

(a) State box (b) Decision box

(c) Conditional output box

Elements used in ASM charts

15

MZ - ESD L8/28/9/2012

Example

Recognize this circuit?

w

w

w 0 1

0

1

0

1

A

B

C

z

Reset

16

MZ - ESD L8/28/9/2012

Test #2

Who am I? What am I?

17

MZ - ESD L8/28/9/2012

Can you write VHDL for this?

How many states?

What kind of FSM?

What does it do?

r 1

r 3 0 1

1

Idle

Reset

r 2

r 1

r 3

r 2

gnt1

gnt2

gnt3

1

1

1

0

0

0

g 1

g 2

g 3

0

0

1

18

MZ - ESD L8/28/9/2012It is an Arbiter!!!!!

Idle

000

1xx

Reset

gnt1 g 1 1 =

x1x

gnt2 g 2 1 =

xx1

gnt3 g 3 1 =

0xx 1xx

01x x0x

001 xx0

19

r1r2r3 =

MZ - ESD L8/28/9/2012Alternative style of state diagram for the arbiter.

r 1 r 2

r 1 r 2 r 3

Idle

Reset

gnt1 g 1 1 =

gnt2 g 2 1 =

gnt3 g 3 1 =

r 1 r 1

r 1

r 2

r 3

r 2

r 3

r 1 r 2 r 3

X

MZ - ESD L8/28/9/2012

LIBRARY ieee;USE ieee.std_logic_1164.all;

ENTITY arbiter IS PORT ( Clock, Resetn : IN STD_LOGIC ; r : IN STD_LOGIC_VECTOR(1 TO 3) ; g : OUT STD_LOGIC_VECTOR(1 TO 3) ) ;END arbiter ;

ARCHITECTURE Behavior OF arbiter IS TYPE State_type IS (Idle, gnt1, gnt2, gnt3) ; SIGNAL y : State_type ;BEGIN PROCESS ( Resetn, Clock ) BEGIN IF Resetn = '0' THEN y

MZ - ESD L8/28/9/2012

Correct VHDL code for the grant signals

. . . PROCESS( y ) BEGIN g(1)

MZ - ESD L8/28/9/2012

Example 1

Data Path

L

L E

L E

0 DataA LA

EA

A Clock

P

DataP

RegisterLP

Sum 0 z

B

b 0

DataB LB

EB

+

2n

n n

Shift-leftregister Shift-right register

n

n

2n 2nPsel 1 0

2n

2n

(a) Manual method

(b) Pseudo-code

Multiplicand11

Product

Multiplier10

01

11

1 1 0 11011

00001011

01 0 0 1 1 1 1

Binary131113

13143

Decimal

P = 0 ; for i = 0 to n 1 do

if b i = 1 thenP = P + A ;

end if; Left-shift A ;

end for;

25

MZ - ESD L8/28/9/2012

Example 1

Data Path

L

L E

L E

0 DataA LA

EA

A Clock

P

DataP

RegisterLP

Sum 0 z

B

b 0

DataB LB

EB

+

2n

n n

Shift-leftregister Shift-right register

n

n

2n 2nPsel 1 0

2n

2n

Control FSM

LP z

b 0

Reset

S3

0

1

0 1

s

0

1

Done

Psel 0 = LP,

s 0

1

S1

S2Psel 1 = EA EB, ,

26

LA, LB

MZ - ESD L8/28/9/2012 27

LIBRARY ieee ;USE ieee.std_logic_1164.all ;USE ieee.std_logic_unsigned.all ;ENTITY multiply IS GENERIC ( N : INTEGER := 8; NN : INTEGER := 16 ) ; PORT ( Clock, s : IN STD_LOGIC ; Resetn : IN STD_LOGIC ; DataA : IN STD_LOGIC_VECTOR(N1 DOWNTO 0) ; DataB : IN STD_LOGIC_VECTOR(N1 DOWNTO 0) ; P : BUFFER STD_LOGIC_VECTOR(NN1 DOWNTO 0) ; Done : OUT STD_LOGIC ) ;END multiply ;

ARCHITECTURE Behavior OF multiply IS TYPE State_type IS ( S1, S2, S3 ) ; SIGNAL y : State_type ; SIGNAL Psel, z, EA, EB, EP, Zero , LA, LB: STD_LOGIC ; SIGNAL B, N_Zeros : STD_LOGIC_VECTOR(N1 DOWNTO 0) ; SIGNAL A, Ain, DataP, Sum : STD_LOGIC_VECTOR(NN1 DOWNTO 0) ;-- Definition of the components used in the datapath -- to be added.................

BEGIN FSM_transitions: PROCESS ( Resetn, Clock ) BEGIN IF Resetn = '0 THEN y

MZ - ESD L8/28/9/2012 28

FSM_outputs: PROCESS ( y, s, B(0) ) BEGIN EP

MZ - ESD L8/28/9/2012 31

FSM_outputs: PROCESS ( y, s, B(0) ) BEGIN EP