laboratory #5 bjt basics and mosfet basics
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© EE, NCKU All rights reserved.
() Electronics Laboratory (1), 2013 p. 5-1 EE, NCKU, Tainan City, Taiwan
Laboratory #5
I. Objectives
2. Learn to measure I-V characteristics of BJTs and MOSFETs.
II. Components and Instruments
(3) Resistor – 100, 1k, 2.2k, 4.7k, 10k, 47k, 100k,1M (Ω)
(4) Variable resistor – 10k, 1M (Ω)
(5) Capacitor – 0.1μ (F)
Sedra/Smith”. Or, chapter 5 to section 6-4 of “Microelectronics Circuit
Analysis and Design 3rd edition, Neaman”.
IV. Preparation
1. Physical structure of BJT
BJT, which is the short form of Bipolar Junction Transistor, is a
three-terminal electronic device, constructed of doped semiconductor
material (Bipolar: P and N or holes and electrons). The three
terminals are emitter (E), base (B) and collector (C). Note the pins
assignment of commercialized products should be assured according
to their datasheets. For instance, the pins assignment component
used in this lab is shown in Fig. 5.1.
The doping of each terminal is different, which is in order to make
the BJT works. Such as, the emitter is heavily doped, while the
© EE, NCKU All rights reserved.
() Electronics Laboratory (1), 2013 p. 5-2 EE, NCKU, Tainan City, Taiwan
collector is lightly doped, allowing a large reverse bias voltage to be
applied before the collector–base junction breaks down.
Fig. 5.1 Physical structure of BJT and pins assignment of 9013
Another switch component, MOSFET, is operated in lots of
similar forms with BJT, such as the current-voltage relationship,
amplifier configurations, etc.
BJT MOSFET
Minority-carrier device Majority-carrier device
2. Characteristics of BJT
The I-V curve of BJT is shown as below, where the y-axis is Ic
(collector current) and the x-axis is Vce (collector-emitter voltage). For
MOSFET, the y-axis will be drain current and the x-axis will be
gate-source voltage. It is helpful to make connections between BJT
and MOS. Another Ib-to-Vbe curve is shown next for further illustration.
NPN
PNP
© EE, NCKU All rights reserved.
() Electronics Laboratory (1), 2013 p. 5-3 EE, NCKU, Tainan City, Taiwan
Fig. 5.2(a) The Ic-Vce Curve of BJT
Fig. 5.2(b) The Ib-Vbe Curve of BJT
For the I-V curve of BJT, it can be divided into four configurations,
which are reverse active, cut-off, saturation, active (forward-active)
regions. Cut-off (switch-off) and saturation (switch-on) regions are
used for switch, active region is used for amplifier, while reverse
active region is rarely used and will not be introduced in this lab. The
status of EBJ and CBJ under different modes is tabulated as below
and the three configurations are discussed next to it.
Table 5.2 The status of EBJ and CBJ under different modes
Mode EBJ CBJ
Cutoff Reverse Reverse
Active Forward Reverse
Saturation Forward Forward
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() Electronics Laboratory (1), 2013 p. 5-4 EE, NCKU, Tainan City, Taiwan
(1) Cut-Off Region
Refer to Fig. 5.2(b), when VBE is smaller than 0.6V or 0.7V,
the BJT is nearly closed. In this region, no matter how large the
VCE is, IB is nearly zero and so as IC. (Remember that BJT is a
current-controlled current source.)
(2) Active Region
To operate BJT in this region, VBE should be larger than 0.7V
(refer to the Fig. 5.2(b)) and VCE should be larger than 0.2V (refer
to the Fig. 5.2(a)). Here in this region, IC and IB are in a nearly
constant ratio, and this ratio is defined as the current gain β
IC/IB. Different BJTs have different values of β, and it is better to
refer to the datasheet before using BJTs.
(3) Saturation Region
When VBE is fixed at or a little higher than 0.7V and VCE is
lower than 0.2V, the BJT will be operated in the saturation region.
From the Fig. 5.2(a), it could be observed that when VCE changes
a little, IC would vary rapidly. Note that there is no linear
relationship between IC and IB.
3. Fundamentals of MOSFET
The metal–oxide–semiconductor field-effect transistor (MOSFET)
is commonly used for amplifying or switching the electronic signals. In
MOSFETs, a voltage applying on the oxide-insulated gate electrode
will induce a conducting channel between source and drain.
Depending on the major carriers, the channel can be n-type or p-type,
and they are called NMOS or PMOS respectively.
(1) Physical structure of MOSFET
As shown in Fig. 5.3, MOSFETs can be classified into two types,
enhancement- and depletion-type. Enhancement MOSFET is the
most widely used FET. So, in this lab we will focus on enhancement
MOSFET and review its physical structure and operation. However,
the depletion-type MOSFET will be briefly discussed as well.
© EE, NCKU All rights reserved.
() Electronics Laboratory (1), 2013 p. 5-5 EE, NCKU, Tainan City, Taiwan
Fig. 5.3 Physical structure of two types of MOSFET
Fig. 5.4 Physical structure of n-channel enhancement-type MOSFET
The transistor is fabricated on a p-type substrate, which is a
single-crystal silicon wafer that provides the base for the whole
device or IC. Two heavily doped n-type regions, n+ source and the n+
drain indicated in Fig. 5.3, are formed in the substrate. A thin layer of
silicon dioxide (SiO2) with thickness tox, which is an excellent
electrical insulator, is grown on the surface of the substrate covering
the area of the source and drain regions. Then, metal is deposited on
the top of the oxide layer to form the gate electrode of the device.
Metal contacts are also made to the source region, the drain
region, and the substrate (body). Thus, there are four terminals for a
MOSFET: the gate terminal (G), the source terminal (S), the drain
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() Electronics Laboratory (1), 2013 p. 5-6 EE, NCKU, Tainan City, Taiwan
terminal (D), and the substrate or body terminal (B).
Observing the substrate, it could be found that it forms p-n
junctions with the source and drain region. These two p-n junctions
can be effectively cut-off by simply connecting the substrate terminal
to the source terminal. In normal operations, these p-n junctions are
kept reverse-biased. On the other hand, once the “channel” between
source and drain terminals is built up by applying external voltage,
carriers can flow through that channel and cause drain current. The
details about how MOSFET operates in different bias conditions will
be discussed in the next section.
The other type of MOSFET, which is called “depletion-type”, has
similar structure as enhancement-type MOSFET. The vital difference
between them is that the depletion MOSFET has physically implanted
channel. Thus, if a voltage VDS is applied between drain and source, a
current ID flows at VGS=0. In other words, depletion-type MOSFET
conducts without applying external gate voltage.
(2) Operation mode
Depending on the bias voltages at the terminals, the operations
of a MOSFET can be classified into three modes. In the following
discussion, a simplified algebraic model that is only accurate for
dated technology has been used. Modern MOSFET requires
computer to simulate its more complex behavior, e.g. short channel
effect.
In this Lab., the enhancement-type NMOS will be used as an
example to illustrate the three modes including cut-off, linear, and
saturation region.
© EE, NCKU All rights reserved.
() Electronics Laboratory (1), 2013 p. 5-7 EE, NCKU, Tainan City, Taiwan
Cut-off region:
With no bias voltage applied to the gate, two back-to-back
diodes exist in series between drain and source. One diode is
formed by the p-n junction between the n+ drain and the
p-substrate, and the other is formed by the n+ source region and
p-substrate. These two back-to-back diodes prevent current
conduction from drain to source when a voltage VDS is applied. In
other words, there is no “channel” between drain and source or
the path between drain and source is highly resistive.
In Figure 5.6, we ground the drain and source terminal, and
apply a positive voltage to the gate. Since the source is grounded,
the gate voltage could be denoted as VGS. The positive voltage
induces an n-channel between two n+ regions and the channel
would provide a path for current to flow. But, there will be no
sufficient number of mobile electrons accumulated in the channel
until VGS > Vt (threshold voltage).
Fig. 5.6 An NMOS with positive voltage applied to the gate VGS<Vt
Linear region:
With the induced channel, we first apply a small positive
voltage VDS (i.e. around 50 mV) between drain and source as
shown in Fig. 5.7. This voltage VDS causes a current ID to flow
through n-channel.
As indicated in Fig. 5.7, the magnitude of ID depends on the
density of electrons in the channel, which in turn depends on the
magnitude of VGS. In fact, the conductance of the channel is
proportional to the excess gate voltage (VGS-Vt), also known as
the effective voltage or the overdrive voltage.
© EE, NCKU All rights reserved.
() Electronics Laboratory (1), 2013 p. 5-8 EE, NCKU, Tainan City, Taiwan
Fig. 5.7 NMOS with VGS>Vt and a small VDS applied
Fig. 5.8 shows a sketch of ID versus VDS for various values of
VGS and it illustrates that the MOSFET is operating as a linear
resistance whose value is controlled by VGS. Ideally, the
resistance is infinite for VGS Vt, and it decreases as VGS > Vt.
Fig. 5.8 The ID-VDS characteristics of the MOSFET in Fig. 5.7
The description above indicates that a channel has to be
induced for the MOSFET to conduct. Increasing VGS above the
threshold voltage Vt enhances the channel, and hence it is
named as “enhancement-type” MOSFET.
Saturation region:
For observing this region, let VGS be held constant at a value
greater than Vt and increase VDS. Refer to Fig. 5.9, it is noted that
VDS appears non-uniformly along the channel. Since every
segment of the channel depth depends on its suffered voltage, it
could be found that the channel is no longer of uniform depth.
Rather, the channel will be tapered as shown in Fig. 5.9, the
deepest depth appears at the source end and the shallowest at
the drain end. As VDS is further increased, the channel is more
© EE, NCKU All rights reserved.
() Electronics Laboratory (1), 2013 p. 5-9 EE, NCKU, Tainan City, Taiwan
tapered and its resistance increases correspondingly. As the
result, the ID-VDS curve is no longer a straight line but bends as
shown in Fig. 5.10.
Fig. 5.9 Induced channel is tapered as VDS is increased,
When VDS is increased to the value of VDS(sat) = VGS-Vt, it
reduces the voltage between gate and channel at the drain end
to Vt, or the channel depth of the drain end decreases to almost
zero, it is said to be “pinched off”. Increasing VDS beyond VGS-Vt,
the current through the channel remains constant or said it have
been entered into the saturation region.
Fig. 5.10 Drain current ID vs. the drain-to-source voltage VDS
© EE, NCKU All rights reserved.
() Electronics Laboratory (1), 2013 p. 5-10 EE, NCKU, Tainan City,
Taiwan
(1) Complete the wiring as Fig. 5.11.
(2) Turn on the power supply after completing the wiring.
(3) Use the digital multi-meter to measure the value of IB, and tune
VR1 until the required IB is obtained.
(4) Use oscilloscope to measure the values of VCE, and tune VR2 to
the required VCE values in the table below.
(5) Use the digital multi-meter to measure the values of IC, and write
down the values of IC at different VCE.
(6) When complete the 1st table, redo (3) to (4) for different IB.
(7) Draw the two sets of data on the same graph.
BI
100
The layout and connections of CD4007 MOSFET array are
shown below. As what it shown, CD4007 consists of 6 transistors, 3
p-channels and 3 n-channels.
1
2
3
4
5
6
7
14
13
12
11
10
9
8
NOTE: Pin14 must be connected to the most positive voltage, and pin 7 to
the most negative. For the sake of safety, maintain the voltage between pin
7 and pin 14 at or below 16V to avoid internal voltage breakdown. Make
sure you turn off the power supply before changing any circuit
connection.
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() Electronics Laboratory (1), 2013 p. 5-11 EE, NCKU, Tainan City,
Taiwan
+12V
14
3
2
1
7
DVM
+12V
14
3
5
4
7
DVM
(a) (b)
Fig. 5.12 (a) Setup for measuring Vtp0 (b) Setup for measuring Vtn0
VDD
14
3
5
4
VGv
RVAR(10k)
Fig. 5.13 Setup for measuring ID vs. VDS with different VGS
(1) Assemble the circuit as shown in Figure 5.12(a) and 5.12(b), and
record down the voltage using DVM (the circled numbers
correspond to the IC pins assignment).
(2) Calculate the threshold voltage of PMOS and NMOS
respectively by using the formula listed in the report.
(3) Next, assemble the circuit as shown in Fig. 5.13. The two bias
voltage sources VDS and VGS could be derived from the variable
resistor connected as shown in Figure 5.13. Note: Check all
connections before turning on the power supply.
(4) Adjust the variable resistors so that MOSFET is biased at
VGS=0.5V and VDS=1V, then record down the current value
shown in DMM. Use the oscilloscope to check the bias voltages
and DMM to measure the current.
(5) Repeat the steps at different bias conditions and record the
current value.
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() Electronics Laboratory (1), 2013 p. 5-12 EE, NCKU, Tainan City,
Taiwan
Problem 1 (PSPICE simulation)
Using PSpice to obtain the I-V characteristics curve of BJT, note that
the schematic is not provided and you should complete drawing the circuit
by CIS Capture and simulating it with DC sweep analysis. Requirement:
(primary sweep) vce is in the range of -300mV to 300mV, (secondary
sweep) ib varies within the range of 0 to 50μA and the step is 10μA.
(1) The circuit schematic
(2) The simulation result
Problem 2 (PSPICE simulation)
Use DC sweep analysis to run the ID vs. VDS curve under different VGS
levels. Use NMOS0P5_BODY model to simulate the MOSFET with
W=1.25μm, L=0.5μm.
(1) The circuit schematic
(2) The simulation result
Note: Library files (sedra_lib.lib and sedra_lib.olb) are available in the
CD-ROM attached to the textbook. You can include the needed
libraries in simulation profile to obtain the required model.
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() Electronics Laboratory (1), 2013 p. 5-13 EE, NCKU, Tainan City,
Taiwan
0.5V
3V
5V
Problem 1
What is the relationship between IE, IB and IC? And, express α by
β? (Calculations are needed, not just giving out the result.) Why do
we need large β?
IC (mA)
IB=40μA
IC (mA)
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() Electronics Laboratory (1), 2013 p. 5-14 EE, NCKU, Tainan City,
Taiwan
In practical applications (ex. speaker), explain why do we need
an amplifier which featuring high input impedance and low output
impedance? Explain the reason. (Hint: loading effect)
loadamplifier
Zin
Zout
Conclusion
() Electronics Laboratory (1), 2013 p. 5-1 EE, NCKU, Tainan City, Taiwan
Laboratory #5
I. Objectives
2. Learn to measure I-V characteristics of BJTs and MOSFETs.
II. Components and Instruments
(3) Resistor – 100, 1k, 2.2k, 4.7k, 10k, 47k, 100k,1M (Ω)
(4) Variable resistor – 10k, 1M (Ω)
(5) Capacitor – 0.1μ (F)
Sedra/Smith”. Or, chapter 5 to section 6-4 of “Microelectronics Circuit
Analysis and Design 3rd edition, Neaman”.
IV. Preparation
1. Physical structure of BJT
BJT, which is the short form of Bipolar Junction Transistor, is a
three-terminal electronic device, constructed of doped semiconductor
material (Bipolar: P and N or holes and electrons). The three
terminals are emitter (E), base (B) and collector (C). Note the pins
assignment of commercialized products should be assured according
to their datasheets. For instance, the pins assignment component
used in this lab is shown in Fig. 5.1.
The doping of each terminal is different, which is in order to make
the BJT works. Such as, the emitter is heavily doped, while the
© EE, NCKU All rights reserved.
() Electronics Laboratory (1), 2013 p. 5-2 EE, NCKU, Tainan City, Taiwan
collector is lightly doped, allowing a large reverse bias voltage to be
applied before the collector–base junction breaks down.
Fig. 5.1 Physical structure of BJT and pins assignment of 9013
Another switch component, MOSFET, is operated in lots of
similar forms with BJT, such as the current-voltage relationship,
amplifier configurations, etc.
BJT MOSFET
Minority-carrier device Majority-carrier device
2. Characteristics of BJT
The I-V curve of BJT is shown as below, where the y-axis is Ic
(collector current) and the x-axis is Vce (collector-emitter voltage). For
MOSFET, the y-axis will be drain current and the x-axis will be
gate-source voltage. It is helpful to make connections between BJT
and MOS. Another Ib-to-Vbe curve is shown next for further illustration.
NPN
PNP
© EE, NCKU All rights reserved.
() Electronics Laboratory (1), 2013 p. 5-3 EE, NCKU, Tainan City, Taiwan
Fig. 5.2(a) The Ic-Vce Curve of BJT
Fig. 5.2(b) The Ib-Vbe Curve of BJT
For the I-V curve of BJT, it can be divided into four configurations,
which are reverse active, cut-off, saturation, active (forward-active)
regions. Cut-off (switch-off) and saturation (switch-on) regions are
used for switch, active region is used for amplifier, while reverse
active region is rarely used and will not be introduced in this lab. The
status of EBJ and CBJ under different modes is tabulated as below
and the three configurations are discussed next to it.
Table 5.2 The status of EBJ and CBJ under different modes
Mode EBJ CBJ
Cutoff Reverse Reverse
Active Forward Reverse
Saturation Forward Forward
© EE, NCKU All rights reserved.
() Electronics Laboratory (1), 2013 p. 5-4 EE, NCKU, Tainan City, Taiwan
(1) Cut-Off Region
Refer to Fig. 5.2(b), when VBE is smaller than 0.6V or 0.7V,
the BJT is nearly closed. In this region, no matter how large the
VCE is, IB is nearly zero and so as IC. (Remember that BJT is a
current-controlled current source.)
(2) Active Region
To operate BJT in this region, VBE should be larger than 0.7V
(refer to the Fig. 5.2(b)) and VCE should be larger than 0.2V (refer
to the Fig. 5.2(a)). Here in this region, IC and IB are in a nearly
constant ratio, and this ratio is defined as the current gain β
IC/IB. Different BJTs have different values of β, and it is better to
refer to the datasheet before using BJTs.
(3) Saturation Region
When VBE is fixed at or a little higher than 0.7V and VCE is
lower than 0.2V, the BJT will be operated in the saturation region.
From the Fig. 5.2(a), it could be observed that when VCE changes
a little, IC would vary rapidly. Note that there is no linear
relationship between IC and IB.
3. Fundamentals of MOSFET
The metal–oxide–semiconductor field-effect transistor (MOSFET)
is commonly used for amplifying or switching the electronic signals. In
MOSFETs, a voltage applying on the oxide-insulated gate electrode
will induce a conducting channel between source and drain.
Depending on the major carriers, the channel can be n-type or p-type,
and they are called NMOS or PMOS respectively.
(1) Physical structure of MOSFET
As shown in Fig. 5.3, MOSFETs can be classified into two types,
enhancement- and depletion-type. Enhancement MOSFET is the
most widely used FET. So, in this lab we will focus on enhancement
MOSFET and review its physical structure and operation. However,
the depletion-type MOSFET will be briefly discussed as well.
© EE, NCKU All rights reserved.
() Electronics Laboratory (1), 2013 p. 5-5 EE, NCKU, Tainan City, Taiwan
Fig. 5.3 Physical structure of two types of MOSFET
Fig. 5.4 Physical structure of n-channel enhancement-type MOSFET
The transistor is fabricated on a p-type substrate, which is a
single-crystal silicon wafer that provides the base for the whole
device or IC. Two heavily doped n-type regions, n+ source and the n+
drain indicated in Fig. 5.3, are formed in the substrate. A thin layer of
silicon dioxide (SiO2) with thickness tox, which is an excellent
electrical insulator, is grown on the surface of the substrate covering
the area of the source and drain regions. Then, metal is deposited on
the top of the oxide layer to form the gate electrode of the device.
Metal contacts are also made to the source region, the drain
region, and the substrate (body). Thus, there are four terminals for a
MOSFET: the gate terminal (G), the source terminal (S), the drain
© EE, NCKU All rights reserved.
() Electronics Laboratory (1), 2013 p. 5-6 EE, NCKU, Tainan City, Taiwan
terminal (D), and the substrate or body terminal (B).
Observing the substrate, it could be found that it forms p-n
junctions with the source and drain region. These two p-n junctions
can be effectively cut-off by simply connecting the substrate terminal
to the source terminal. In normal operations, these p-n junctions are
kept reverse-biased. On the other hand, once the “channel” between
source and drain terminals is built up by applying external voltage,
carriers can flow through that channel and cause drain current. The
details about how MOSFET operates in different bias conditions will
be discussed in the next section.
The other type of MOSFET, which is called “depletion-type”, has
similar structure as enhancement-type MOSFET. The vital difference
between them is that the depletion MOSFET has physically implanted
channel. Thus, if a voltage VDS is applied between drain and source, a
current ID flows at VGS=0. In other words, depletion-type MOSFET
conducts without applying external gate voltage.
(2) Operation mode
Depending on the bias voltages at the terminals, the operations
of a MOSFET can be classified into three modes. In the following
discussion, a simplified algebraic model that is only accurate for
dated technology has been used. Modern MOSFET requires
computer to simulate its more complex behavior, e.g. short channel
effect.
In this Lab., the enhancement-type NMOS will be used as an
example to illustrate the three modes including cut-off, linear, and
saturation region.
© EE, NCKU All rights reserved.
() Electronics Laboratory (1), 2013 p. 5-7 EE, NCKU, Tainan City, Taiwan
Cut-off region:
With no bias voltage applied to the gate, two back-to-back
diodes exist in series between drain and source. One diode is
formed by the p-n junction between the n+ drain and the
p-substrate, and the other is formed by the n+ source region and
p-substrate. These two back-to-back diodes prevent current
conduction from drain to source when a voltage VDS is applied. In
other words, there is no “channel” between drain and source or
the path between drain and source is highly resistive.
In Figure 5.6, we ground the drain and source terminal, and
apply a positive voltage to the gate. Since the source is grounded,
the gate voltage could be denoted as VGS. The positive voltage
induces an n-channel between two n+ regions and the channel
would provide a path for current to flow. But, there will be no
sufficient number of mobile electrons accumulated in the channel
until VGS > Vt (threshold voltage).
Fig. 5.6 An NMOS with positive voltage applied to the gate VGS<Vt
Linear region:
With the induced channel, we first apply a small positive
voltage VDS (i.e. around 50 mV) between drain and source as
shown in Fig. 5.7. This voltage VDS causes a current ID to flow
through n-channel.
As indicated in Fig. 5.7, the magnitude of ID depends on the
density of electrons in the channel, which in turn depends on the
magnitude of VGS. In fact, the conductance of the channel is
proportional to the excess gate voltage (VGS-Vt), also known as
the effective voltage or the overdrive voltage.
© EE, NCKU All rights reserved.
() Electronics Laboratory (1), 2013 p. 5-8 EE, NCKU, Tainan City, Taiwan
Fig. 5.7 NMOS with VGS>Vt and a small VDS applied
Fig. 5.8 shows a sketch of ID versus VDS for various values of
VGS and it illustrates that the MOSFET is operating as a linear
resistance whose value is controlled by VGS. Ideally, the
resistance is infinite for VGS Vt, and it decreases as VGS > Vt.
Fig. 5.8 The ID-VDS characteristics of the MOSFET in Fig. 5.7
The description above indicates that a channel has to be
induced for the MOSFET to conduct. Increasing VGS above the
threshold voltage Vt enhances the channel, and hence it is
named as “enhancement-type” MOSFET.
Saturation region:
For observing this region, let VGS be held constant at a value
greater than Vt and increase VDS. Refer to Fig. 5.9, it is noted that
VDS appears non-uniformly along the channel. Since every
segment of the channel depth depends on its suffered voltage, it
could be found that the channel is no longer of uniform depth.
Rather, the channel will be tapered as shown in Fig. 5.9, the
deepest depth appears at the source end and the shallowest at
the drain end. As VDS is further increased, the channel is more
© EE, NCKU All rights reserved.
() Electronics Laboratory (1), 2013 p. 5-9 EE, NCKU, Tainan City, Taiwan
tapered and its resistance increases correspondingly. As the
result, the ID-VDS curve is no longer a straight line but bends as
shown in Fig. 5.10.
Fig. 5.9 Induced channel is tapered as VDS is increased,
When VDS is increased to the value of VDS(sat) = VGS-Vt, it
reduces the voltage between gate and channel at the drain end
to Vt, or the channel depth of the drain end decreases to almost
zero, it is said to be “pinched off”. Increasing VDS beyond VGS-Vt,
the current through the channel remains constant or said it have
been entered into the saturation region.
Fig. 5.10 Drain current ID vs. the drain-to-source voltage VDS
© EE, NCKU All rights reserved.
() Electronics Laboratory (1), 2013 p. 5-10 EE, NCKU, Tainan City,
Taiwan
(1) Complete the wiring as Fig. 5.11.
(2) Turn on the power supply after completing the wiring.
(3) Use the digital multi-meter to measure the value of IB, and tune
VR1 until the required IB is obtained.
(4) Use oscilloscope to measure the values of VCE, and tune VR2 to
the required VCE values in the table below.
(5) Use the digital multi-meter to measure the values of IC, and write
down the values of IC at different VCE.
(6) When complete the 1st table, redo (3) to (4) for different IB.
(7) Draw the two sets of data on the same graph.
BI
100
The layout and connections of CD4007 MOSFET array are
shown below. As what it shown, CD4007 consists of 6 transistors, 3
p-channels and 3 n-channels.
1
2
3
4
5
6
7
14
13
12
11
10
9
8
NOTE: Pin14 must be connected to the most positive voltage, and pin 7 to
the most negative. For the sake of safety, maintain the voltage between pin
7 and pin 14 at or below 16V to avoid internal voltage breakdown. Make
sure you turn off the power supply before changing any circuit
connection.
© EE, NCKU All rights reserved.
() Electronics Laboratory (1), 2013 p. 5-11 EE, NCKU, Tainan City,
Taiwan
+12V
14
3
2
1
7
DVM
+12V
14
3
5
4
7
DVM
(a) (b)
Fig. 5.12 (a) Setup for measuring Vtp0 (b) Setup for measuring Vtn0
VDD
14
3
5
4
VGv
RVAR(10k)
Fig. 5.13 Setup for measuring ID vs. VDS with different VGS
(1) Assemble the circuit as shown in Figure 5.12(a) and 5.12(b), and
record down the voltage using DVM (the circled numbers
correspond to the IC pins assignment).
(2) Calculate the threshold voltage of PMOS and NMOS
respectively by using the formula listed in the report.
(3) Next, assemble the circuit as shown in Fig. 5.13. The two bias
voltage sources VDS and VGS could be derived from the variable
resistor connected as shown in Figure 5.13. Note: Check all
connections before turning on the power supply.
(4) Adjust the variable resistors so that MOSFET is biased at
VGS=0.5V and VDS=1V, then record down the current value
shown in DMM. Use the oscilloscope to check the bias voltages
and DMM to measure the current.
(5) Repeat the steps at different bias conditions and record the
current value.
© EE, NCKU All rights reserved.
() Electronics Laboratory (1), 2013 p. 5-12 EE, NCKU, Tainan City,
Taiwan
Problem 1 (PSPICE simulation)
Using PSpice to obtain the I-V characteristics curve of BJT, note that
the schematic is not provided and you should complete drawing the circuit
by CIS Capture and simulating it with DC sweep analysis. Requirement:
(primary sweep) vce is in the range of -300mV to 300mV, (secondary
sweep) ib varies within the range of 0 to 50μA and the step is 10μA.
(1) The circuit schematic
(2) The simulation result
Problem 2 (PSPICE simulation)
Use DC sweep analysis to run the ID vs. VDS curve under different VGS
levels. Use NMOS0P5_BODY model to simulate the MOSFET with
W=1.25μm, L=0.5μm.
(1) The circuit schematic
(2) The simulation result
Note: Library files (sedra_lib.lib and sedra_lib.olb) are available in the
CD-ROM attached to the textbook. You can include the needed
libraries in simulation profile to obtain the required model.
© EE, NCKU All rights reserved.
() Electronics Laboratory (1), 2013 p. 5-13 EE, NCKU, Tainan City,
Taiwan
0.5V
3V
5V
Problem 1
What is the relationship between IE, IB and IC? And, express α by
β? (Calculations are needed, not just giving out the result.) Why do
we need large β?
IC (mA)
IB=40μA
IC (mA)
© EE, NCKU All rights reserved.
() Electronics Laboratory (1), 2013 p. 5-14 EE, NCKU, Tainan City,
Taiwan
In practical applications (ex. speaker), explain why do we need
an amplifier which featuring high input impedance and low output
impedance? Explain the reason. (Hint: loading effect)
loadamplifier
Zin
Zout
Conclusion