lecture 5 microfabrication – wafer-level processes...

마이크로시스템기술개론 MEMS_Lect05_1

• Wafer-Level Processes

- Metallic Thin Film

- Thin-Film Deposition

Physical Vapor Deposition

Resistive Evaporation

Electron-Beam Evaporation

Sputter Deposition

Chemical Vapor Deposition

LPCVD

PECVD

Lecture 5

Microfabrication – Wafer-Level Processes (III)


- Usage

Conductors

Resistors

Mechanical elements

Transducer elements

- Deposition techniques

(1) Resistive evaporation

(2) Electron-beam evaporation

(3) Sputter deposition

(4) Magnetron sputter deposition

(5) CVD

(6) Laser-assisted CVD

(7) Electrodeposition

Metallic Thin Film


-잘녹지않는 metal “boat”를사용.- 10-3 ~ 10-2 Torr까지의 vapor pressure를 만드는 온도까지 상승시킬 수있는금속은가능.

-승화하기도하므로용융점이중요한것은아님.- Tungsten boat가 1400 ºC까지 쓸 수 있으므로 Au, Al, Mg 등은 적절하고,

Cr은경계에있다.- Vapor condensation process. 금속 원자는 표면에 도착하면 붙어 버린다.이것은 step coverage나 stress를좋게하는움직임을없게한다.

- 기판 온도는 stress에 영향을 주어 가열하지 않은 기판은 일반적으로

tensile이다.- 저 융점 금속(Al, Au)는 stress가 낮으나, 융점이 높은 금속일수록 stress가커진다.

- Sputter한 막보다 접착력이 나쁘고 대개 0.5 ~ 5 nm/s 정도의 증착율을보인다.

Resistive Evaporation


- Electron beam (8~10 keV, generally 100~200 mA)이 target을 scan해서vapor를만든다.

- Electron beam power, 초점, target 냉각 등에 의해 조절되고 온도는 2800ºC까지올라간다.

- Resistive evaporation으로가능한 금속, Ti, Pt, Pd,녹기어려운 W, Mo, Ta도가능하다.

- W는실리콘과선열팽창계수가비슷해유용하다.

- CVD나 sputtering (5~200 nm/s)보다 빠른 증착이 가능하고 , resistiveevaporation보다는기판온도가낮다.

- Metal과 Dielectric도가능하나같은기계를쓰지는않는다.


(continued)


- 가열하지 않는 기판에서는 일반적으로 tensile이고 고 융점 금속일수록

stress가올라간다.

- Al이나 Mg같은 “soft material”로부터발생하는 x-ray는 100~200 eV이다.

Target 아래에 있는 Cu (열전도를 위한 것)에 beam이 맞아서 K-α x-ray가발생하지않는다면이정도는인체에해를주지않는다.

- 그런데 K-α x-ray는 30 kV 가속 전압이 필요하고, 대부분의 electron-beamevaporator는 10 kV이하이다.

- Ion gun은 film을 compressive로 만든다. Gun으로부터의 에너지와 ion flux를조절하면 그 양을 조절할 수 있고 고 융점이나 high tensile stress film에대해서는 ion gun을보조로사용하면 stress를적게할수있다.

- 표면을 때린 ion이 extra energy를 금속 원자에 주어서 좀 더 조밀하게

(compact)정렬시켜 compressive가된다.



- 불활성 기체의 이온 (예를 들면, Ar+ )이 DC나 RF 구동에 의해 가속되어서target을때리고그 momentum에의해 target물질이튀어나온다.

- 충분히 높은 에너지의 플라즈마가 발생한다면 거의 대부분의 물질을 sputter할수있다 (단, dielectric은 RF sputter가필요하다).

- Methods to obtain plasma.(1) DC glow discharge -장치가간단하고 soft material만이가능하며

low energy plasma만을발생.(2) Planar RF -전극판두개가평행위치, target에 RF를가함.

Dielectric도가능.(3) Planar magnetron -자기장이반원의전자궤도를만들고,가스분자와의

상호작용을증가시켜더많은이온을만든다.(4) Cylindrical magnetron or S-gun - 전자를 위해서 자기적으로 “race-track”과

같은폐회로를만들고기판으로부터는멀리

떨어뜨리고 target근처에 high-energy plasma를만든다.

Sputter Deposition

(continued)


- Sputtering은 evaporation 보다 원자에 에너지를 많이 주어서 surfacemobility가 크고 resputtering이 되기도 한다. 따라서, step coverage가 좋고stress control이좋다.역으로 lift-off가어렵다.

- Sputtering으로 alloy나 dielectric compound를 올릴 수 있다 (TiNi, PZT,NdTbFeB등).

- Sputter로형성된막은 tensile이고심하면 yield strength를넘기도한다.Cr, Ti, Ni, Mo, Ta등은낮은기압에서는 compressive가된다.Stress가바뀌는압력은무거운원자의금속일수록

증가한다.

Illustration of relationshipamong pressure, atomic massof the metal, and stress insputtered films.

Sputter Deposition


- Step coverageEvaporation : source로부터방향성을갖는다.그래서 step coverage가나쁘다.

Lift-off에는유리.Sputtering :방향성은있으나 source가널리분포해있고,분자는 mean free path

(typically 1cm at 10 mTorr)내에서방향성을유지한다.Planar RF나 planar magnetron sputtering :기판이플라즈마에담겨있으므로

벽면과표면이거의같다.S-gun sputtering :기판이플라즈마로부터떨어져있으므로벽면은표면보다얇다.

Illustration highlighting the differences in step coverage between evaporation (left),planar sputtering (center), and S-gun sputtering (right).

Comparison of Evaporation and Sputtering


- Shadow effect는 문제를 일으키기는 하나 마이크로머시닝에서는 유용하기도한다.

- Step coverage를좋게하기위해서웨이퍼를돌리면서증착하기도한다.- Shadowing effect는 minimum lithographic resolution 보다 작은 선폭을 만드는데이용되기도한다.

Illustration of the use of shadowing to produce features finer than the lithographicresolution. At left, a sacrificial layer (typically photoresist) is used to deposit metal at aknown angle. At right, after removal of the sacrificial layer, a finer structure remains thanthe original line width. This approach is similar to standard “lift-off” deposition (discussedbelow), but in that case, an overhanging “lip” of photoresist is used to aid removal of theunwanted metal.

Shadowing


mirror plate

address electrode vertical spring

a’

a

Va

S

Va

S

(a) undeflected state

(b) deflected state

A schematic illustration of micromirror with vertical spring.

- J. W. Shin : Sensors and Actuators, Vol.A66, 144-149,1998

Vertical Spring for Micromirror


(a) electrode definition

(b) sacrificial layer definition

(c) spring evaporation with some incident angle (shadow evaporation)

(d) fill up holes

(e) mirror evaporation

(f) sacrificial layer removal

silicon

oxide

aluminum

thick PR

Fabrication process sequence of micromirror array with vertical spring.

Fabrication Process


(a) SEM photograph of fabricatedmicromirror array (side-view)

(b) magnified view of micromirrorarray in (a)

Micro Mirror Array

vertical spring

Fabricated vertical spring array.


Chemical Vapor Deposition• A class of deposition methods in which precursor materials are introduced

into a heated furnace.• A chemical reaction occurs on the surface of the wafer, resulting in

deposition.• Silicon films are formed from the decomposition of silane (SiH4), with

hydrogen as a gaseous byproducts.• Silicon nitride is formed by the reaction of dichlorosilane (SiH2Cl2) and

ammonia (NH3), with hydrogen and HCl vapor as gaseous byproducts.• Silicon dioxide is formed by the reaction of silane or silane derivative with a

suitable oxidizing species.• CVD depositions are typically performed under low-pressure conditions

(less than 1 mTorr) and usually involve an inert diluent gas, such asnitrogen, in addition to the reacting species.


LPCVD and Metallization• Low pressure CVD, most commercially important.• With the exception of silicon, CVD processed typically involve

temperatures in the range of 500o to 850oC.• These temperatures are too high to perform on wafers that have been

metallized with either aluminum or gold, which form eutectics with silicon at577oC and 380oC, respectively.

• It is necessary to perform all CVD processes before any depositions withthese metals.

• Tungsten is able to withstand CVD temperatures.


Epitaxy• If CVD deposition occurs on a single-crystal substrate, it is possible for the

underlying crystal to serve as a template for the deposited material todevelop as an extension of the single crystal.

• Epitaxy is used for silicon and also for various III-V compounds, such asGaAs.

• Taking the case of silicon as an example, there is a relation betweensubstrate temperature, deposition rate, and crystal growth.

• If at given temperature, the deposition rate is slow enough to provide ampletime for atoms to migrate along the surface and find equilibrium lattice sites,then epitaxy is possible.

• At higher deposition rates, the deposition occurs as polysilicon.

(continued)


Epitaxy• In Figure, it is seen that the maximum deposition rates, the deposition

rates for epitaxy drop dramatically with temperature.• One interesting feature of silicon epitaxy is that if a portion of the single-

crystal wafer is exposed, while the rest is covered with silicon dioxide,epitaxial growth can occur over the single-crystal regions while polysiliconis being deposited over the oxide.

The relation between deposition rate,temperature, and the morphology ofthe deposited CVD silicon film.


PECVD• Plasma-Enhanced CVD• Deposition rates can be enhanced if the deposition occurs in a glow-

discharge plasma.• PECVD is used to deposit dielectric films at lower temperature (below

400oC) that could be achieved without the plasma assist.• This is extremely important in constructing insulation layers for use with

metallization.


Film and Process• Films deposited by LPCVD are either amorphous, in the case of the

inorganic dielectrics, or polycrystalline, in the case of polysilicon or metals• The material properties can depend in detail on the exact process,

including such issues as temperature, gas flow rates, pressures, and thechemistry or morphology of the layer on which the film is deposited.

• The mass density of a deposited film, for example, depends on how manyvoids are present (regions where atoms could fit, but, because of therelatively low temperature of deposition, do not get filled up).

• Thermally grown silicon dioxide has fewer voids than LPCVD silicondioxide, which, in turns, has fewer voids than lower-temperature PECVDsilicon dioxide.

• In addition, the CVD oxides have some residual hydrogen.• Post-deposition anneals are used to densify the films


-원하는금속원자가실리콘원자와치환하는반응으로금속막을얻는다.

- Tungsten은 low-pressure CVD로선택적인증착이가능하다.

- SiO2를 mask로 사용하고 WF6 gas를 silicon이나 polysilicon에 쏘여 주면된다.

- Busta : 텅스텐으로 filament, loop, pyramid, field emitter structure 등을제작했다.

- Mac Donald :텅스텐으로 honeycomb, harmonic motor등을제작했다.

- Manginell : platinum을 선택적으로 증착, 산소 내의 수소를 알아내는

가스센서로사용.

46 3232 SiFWSiWF +→+

Selective Metal CVD


SEM top view of a pair of filaments. Al bondwires connect the square bond pads to aconventional dual in-line package (DIP). Only thelower filament which was electrically heated inthe CVD cell contains a 0.2 µm layer of Pt.

The micro-CVD apparatus: A teflon “CVD cell” housesthe packaged filament and a small amount of the Ptprecursor. The cell is equipped with electrical access toprovide power to those filament selected for deposition.Nitrogen lines insure an inert ambient in the cell. Tovaporize the precursor, the CVD cell is inserted in to anoven at 140 ºC.

- R. P. Manginell, Solid-State Sensor and Actuator Workshop, pp.23-27, 1996.- Pt precursor (platinum acetylacetonate)를 140 ºC의 CVD에 넣고 filament를넣는다.

- Pt는 450 ºC를넘어야 filament에형성된다.-단자에전류를흘려 filament를가열.-전류를 dc로흘리거나 20 Hz의 pulse를 duty cycle을바꿔가면서가열.

Selective CVD of platinum


Near-profile SEMs of the ends of two filamentssubjected to different deposition conditions.The high surface-area film on the top filamentwas deposited in continuous mode for 10minutes. The lower film underwent a 9 % duty-cycle (5 msec on, 50 msec off) deposition for atotal elapsed time of 7 min., and is relativelysmooth in comparison to the upper film.

- 10분간전류를계속흘린경우표면이상당히거칠어짐.

- 이것은 catalyst precursor의 mass-transport가제한되기때문이다.

- Duty-cycle이클수록거칠어짐.- 9 % duty-cycle의경우 film이고움.

Results


- 접착력이 좋지 못한 non-reactive metal 아래에 Ti, Hf (Hafnium, 융점 2230

ºC), Cr등의 reactive metal을 adhesion layer로 10~30 nm정도형성한다.

-금,백금과다른 low-reactivity metals등에는절대적으로필수적이다.

-보통 Ti/Au/Ti의 3층막을사용. Ti 30nm/Au 500 nm/Ti 30 nm.

-전기적으로연결한다면위의티타늄은제거해야한다.

- Adhesion metal은증착할금속과합금을만들수도있으므로 Pt또는 Pd와

같은확산방지층을삽입해야한다.

-금은티타늄을통해서 GaAs나 Silicon기판으로확산할수있다.

Adhesion Layers for Metals

lecture 5 microfabrication – wafer-level processes...

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