logic to gates -...

IWKS 2300/5350

Fall 2017

John K. Bennett

Logic to Gates

Boolean Algebra

Some elementary Boolean functions:

Not(x)

And(x,y)

Or(x,y)

Nand(x,y) (functionally complete!)

x y z

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 0

1 0 0 1

1 0 1 0

1 1 0 1

1 1 1 0

zyxzyxf )(),,(

Boolean functions:

A Boolean function can be expressed using a logic expression, a truth table or a schematic.

Important observation:Every Boolean function can be expressed using And, Or & Not, so, if your function can implement these 3, it is “functionally complete.”

x y Nand(x,y)

0 0 1

0 1 1

1 0 1

1 1 0

x y And(x,y)

0 0 0

0 1 0

1 0 0

1 1 1

x y Or(x,y)

0 0 0

0 1 1

1 0 1

1 1 1

x Not(x)

0 1

1 0

All Boolean Functions of Two Variables

How many

for n

variables?

Boolean Algebra

Given: Nand(a,b), false

We can build:

Not(a) = Nand(a,a)

true = Not(false)

And(a,b) = Not(Nand(a,b))

Or(a,b) = Not(And(Not(a),Not(b)))

Xor(a,b) = Or(And(a,Not(b)),And(Not(a),b)))

Etc. (i.e., any Boolean function) We can prove this!

George Boole, 1815-1864

(“A Calculus of Logic”)

Gate Logic

Gate logic – a gate architecture designed to implement a Boolean function

Elementary gates:

Composite gates:

Important distinction: Interface (what) VS implementation (how).

0 0 0

0 1 01 0 0

1 1 1

a b out

a b

out

power supply

AND gate

power supply

a

b

out

0 0 0

0 1 1

1 0 1

1 1 1

a b out

OR gate

Circuit Implementations

From a theoretical perspective, physical realizations of logic gates are irrelevant.

From an engineering perspective, physical realizations of logic gates are essential to performance.

Diode Transistor Implementation of NAND

outa

bAnd

a b out

0 0 0

0 1 0

1 0 0

1 1 1

Example: Building and AND Gate from Just NAND Gates

outNot

a

b

outNand

ain out

x

b

Implementation: And(a,b) = Not(Nand(a,b))

Building an AND Gate

Equation: And(a,b) = Not(Nand(a,b))

outNOT

a

b

outNAND

ain out

x

b

Building an AND Gate with LogicCircuit

Lab 3: Elementary Logic Gates

Given: Nand(a,b)

Build:

1. XOR

2. Half Adder

3. Full Adder

4. 2:1 Multiplexor

5. 1:2 Demultiplexor

a b Nand(a,b)

0 0 1

0 1 1

1 0 1

1 1 0

XOR

And

And

Not

Or out

a

b

Not

Xor(a,b) = Or(And(a,Not(b)),And(Not(a),b)))

An (Inefficient) Implementation

Xora

bout

0 0 00 1 1

1 0 11 1 0

a b out

Interface

Claude Shannon, 1916-2001

(“Symbolic Analysis of Relay and

Switching Circuits” )

f = (~a ● b) + (a ● ~b)

We can build an XOR using only 4 NAND gates…

Xora

bout

0 0 00 1 1

1 0 11 1 0

a b out

Interface

How?


Xora

bout

0 0 00 1 1

1 0 11 1 0

a b out

Interface

How?

By being clever…


Xora

bout

0 0 00 1 1

1 0 11 1 0

a b out

Interface

How can we prove this works?

1) Write out the equations for Q

and simplify.

t

r

s


t

r

s

Q = ~(s ● t) = ~ (~(A ● r) & ~(B ● r))

= (~~(A ● r) + ~~(B ● r)) = ((A ● r) + (B ● r))

= ((( A ● ~(A ● B)) + ((B ● ~(A ● B)))

= (((A ● ~A) + (A ● ~B)) + ((B ● ~B) + (B ● ~A)))

= (A ● ~B) + (~A ● B)

= A XOR B


Xora

bout

0 0 00 1 1

1 0 11 1 0

a b out

InterfaceHow can we prove this works?

1) Write out the equations for Q

and simplify.

2) Build it…

Half adder (designed to add 2 bits)

Implementation: based on two gates that you’ve seen before.

half

adder

a sum

b carry

a b sum carry

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

How To Build A Half Adder

Truth table for Half Adder

A B A XOR B (A + B) Cout

0 0 0 0 0

0 1 1 1 0

1 0 1 1 0

1 1 0 0 1

Half Adder

∑Cout

BA

??

∑

How To Build A Half Adder

Truth table for XOR and Half Adder

A B A XOR B (A + B) Cout A AND B

0 0 0 0 0 0

0 1 1 1 0 0

1 0 1 1 0 0

1 1 0 0 1 1

Half Adder

∑Cout

BA

∑

= A XOR B

Cout = A AND B

∑

Full adder (designed to add with carry in)

Implementation: based on half-adder gates.

a b c sum carry

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

full adder

asum

b

carryc

Implementation of Full Adder

Truth table for Full Adder

Cin A B Cout

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

∑

Full Adder

∑Cout

BA Cin

How To Build A Full Adder


Cin A B Cout1 Cout2 Cout

0 0 0 0 0 0 0 0

0 0 1 1 0 0 1 0

0 1 0 1 0 0 1 0

0 1 1 0 1 0 0 1

1 0 0 0 0 0 1 0

1 0 1 1 0 1 0 1

1 1 0 1 0 1 0 1

1 1 1 0 1 0 1 1

∑∑1

Half Adder

∑2Cout2

B2A2

Half Adder

∑1Cout1

B1A1

A B Cin

∑

Cout

??

How To Build A Full Adder


Cin A B Cout1 Cout2 Cout

0 0 0 0 0 0 0 0

0 0 1 1 0 0 1 0

0 1 0 1 0 0 1 0

0 1 1 0 1 0 0 1

1 0 0 0 0 0 1 0

1 0 1 1 0 1 0 1

1 1 0 1 0 1 0 1

1 1 1 0 1 0 1 1

∑∑1

Half Adder

∑2Cout2

B2A2

Half Adder

∑1Cout1

B1A1

A B Cin

∑Cout

Chained Carry Adder

Chained carry makes addition time approximately equal to number of

bits times the propagation delay of a Full Adder

Full Adder

∑Cout

BA Cin

Full Adder

∑Cout

BA Cin

Full Adder

∑Cout

BA Cin

Full adder prop. delay = 3 gpd (carry output)

So a 16 bit adder would take 48 gpd to complete add

Carry Look Ahead Basics

If we understand how carry works we can compute carry in advance.

This is called “Carry Look-Ahead.”

For any bit position, if A = 1 and B = 1; Cout = 1, i.e., a carry will be

generated to the next bit position, regardless of value of Cin. This is

called “Carry Generate”

For any bit position, if one input is 1 and the other input is 0; Cout

will equal Cin (i.e., the value of Cin will be propagated to the next bit

position. This is called “Carry Propagate”

For any bit position, if A = 0 and B = 0; Cout will equal 0, regardless

of value of Cin. This is called “Carry Stop.”

Full Adder

∑Cout

BA Cin

Full Adder

∑Cout

BA Cin

Full Adder

∑Cout

BA Cin

Carry Generate, Propagate and Stop


Cin A B Cout

fgps 0 0 0 x CSi

fgps 0 1 1 x CPi

fgps 1 0 1 x CPi

fgps 1 1 0 x CGi

∑

Full Adder

∑Cout

BA Cin

X

fgps

No need for carry chain

Carry Look Ahead Basics

The equations to compute Cin at Bit Position i are as follows:

Cini = Cgi-1

+ Cpi-1 ● Cgi-2

+ Cpi-1 ● Cpi-2 ● Cgi-3

…

+ Cpi-1 ● Cpi-2 … Cp1 ● Cg0

Practical Considerations

Cini = Cgi-1

+ Cpi-1 ● Cgi-2

+ Cpi-1 ● Cpi-2 ● Cgi-3

…

+ Cpi-1 ● Cpi-2 … Cp1 ● Cg0

Very wide (more than 8 input) gates are impractical, so we

would likely use a logn depth tree of gates to implement the

wide ANDs and ORs. This is still faster than chained carry,

even for 16 bits (and is much faster for 32 or 64 bit adders).

Practical Implementation Note

Use Cin0 to add one (for example, when inverting

the sign of a two’s complement number).

Cin0 then becomes a control signal that can be

turned on by the control part of the microprocessor.

Full Adder

∑Cout

BA Cin

23

03 02 01 00

0

0

13 12 11 10

1

1

22 21 20

2

2

33 32 31 30

3

3

What About Multiplication?

Carry Save Addition

The idea is to perform several additions in sequence, keeping the carries

and the sum separate. This means that all of the columns can be added

in parallel without relying on the result of the previous column, creating a

two output "adder" with a time delay that is independent of the size of its

inputs. The sum and carry can then be recombined using a normal carry-

aware addition (ripple or CLA) to form the correct result.

CSA Uses Full Adders (we can be clever about how we do this)

Wallace Tree Addition

CSA Adder Tree Depth = 7; 7 adders used

Plus add with carry

Depth = 4; 7 adders

Plus add with carry

A 4-bit Example (carry propagating to the right)

Example: An 8-bit Carry Save Array Multiplier

A parallel multiplier for unsigned operands. It is composed of 2-input AND

gates for producing the partial products, a series of carry save adders for

adding them and a ripple-carry adder for producing the final product.

Generating Partial Products

FA with 3 inputs, 2 outputs

Multiplexor

Proposed Implementation: based on Not, And, Or gates (since

we can build all of these from NAND.

a

b

sel

outMux

a b sel out

0 0 0 0

0 0 1 0

0 1 0 0

0 1 1 1

1 0 0 1

1 0 1 0

1 1 0 1

1 1 1 1

sel out

0 a

1 b

Multiplexor

a

b

sel

outMux

a b sel out

0 0 0 0

0 0 1 0

0 1 0 0

0 1 1 1

1 0 0 1

1 0 1 0

1 1 0 1

1 1 1 1

sel out

0 a

1 b

Multiplexor

Proposed Implementation: based on Not, And, Or gates (since

we can build all of these from NAND.

a

b

sel

outMux

a b sel out

0 0 0 0

0 0 1 0

0 1 0 0

0 1 1 1

1 0 0 1

1 0 1 0

1 1 0 1

1 1 1 1

sel out

0 a

1 b

Multiplexors can be used a “function generators.” For example,

how might a 4:1 mux be used to generate all possible

combinations of two Boolean variables?

All Boolean Functions of Two Variables

What About a DeMux? Here is a 1:8 Demux…

What would a 1:2

Demux look like?

1:2 Demultiplexor

s0 in a0 a1

0 0 0 0

0 1 1 0

1 0 0 0

1 1 0 1

a0 = (~s0 in)

a1 = (s0 in)

4 Bit Arithmetic Logic Unit (ALU) (not quite as easy as I first imagined )

X Y

ZC

ALUF

4-bit ALU with two 4-but two inputs, X and Y, one 4-bit

function select input F, one 4-bit output Z, and one carry

output C: The ALU should compute the following functions:1. 0

2. 1

3. X

4. Y

5. ~X

6. ~Y

7. X & Y

8. X | Y

9. X XOR Y

10. ~(X & Y)

11. ~(X | Y)

12. ~(X XOR Y)

13. X + Y

14. X – Y

15. -X

16. -Y

These complicate things a lot.

I’ve made them optional

4 Bit Arithmetic Logic Unit (ALU)

X Y

ZC

ALUF




2. 1

3. X

4. Y

5. ~X

6. ~Y

7. X & Y

8. X | Y

9. X XOR Y

10. ~(X & Y)

11. ~(X | Y)

12. ~(X XOR Y)

13. X + Y

14. X – Y

15. -X

16. -Y

?

?


X Y

ZC

ALUF




2. 1

3. X

4. Y

5. ~X

6. ~Y

7. X & Y

8. X | Y

9. X XOR Y

10. ~(X & Y)

11. ~(X | Y)

12. ~(X XOR Y)

13. X + Y

14. X – Y

15. -X

16. -Y

?


X Y

ZC

ALUF




2. 1

3. X

4. Y

5. ~X

6. ~Y

7. X & Y

8. X | Y

9. X XOR Y

10. ~(X & Y)

11. ~(X | Y)

12. ~(X XOR Y)

13. X + Y

14. X – Y

15. -X

16. -Y

X+Y

X-Y

-X

-Y


How can we make our life easy by mapping F well?

The ALU should compute the following functions:1. 0

2. 1

3. X

4. Y

5. ~X

6. ~Y

7. X & Y

8. X | Y

9. X XOR Y

10. ~(X & Y)

11. ~(X | Y)

12. ~(X XOR Y)

13. X + Y

14. X – Y

15. -X

16. -Y

Functions 1-12 are logical functions:

use 4:1 multiplexors

Functions 13-16 are arithmetic functions:

use full adders

} optional


How can we make our life easy by mapping F well?


2. 1

3. X

4. Y

5. ~X

6. ~Y

7. X & Y

8. X | Y

9. X XOR Y

10. ~(X & Y)

11. ~(X | Y)

12. ~(X XOR Y)

13. X + Y

14. X – Y

15. -X

16. -Y

Functions 1-12 are logical functions:

use 4:1 multiplexors

Functions 13-16 are arithmetic functions:

use full adders (and some other logic for 14-16)

4 x 4:1 Mux

4 x Full Adder++(2’s comp, neg, etc.)

4 x 2:1 Mux

X

Y

X

Y

Z

C

0

F = one of the green boxes

sel

F (mapped as desired)

More about the “2’s comp, neg, etc.” …


2. 1

3. X

4. Y

5. ~X

6. ~Y

7. X & Y

8. X | Y

9. X XOR Y

10. ~(X & Y)

11. ~(X | Y)

12. ~(X XOR Y)

13. X + Y

14. X – Y

15. -X

16. -Y

X

Y Inv.

Inv. +1

+1 2:1

∑

F = 14

∑1

C1

-X

-Y

4:1∑1

∑1

-X

-Y

to 4x2:1

X + Y

X – Y

-X

-Y

to 4x2:1

This is all you

need for F=13

The ALU in the CPU (a sneak preview of the IWKS 3300 Hack computer)

AL

U

Mu

x

D

out

A/M

a

D register

A registerA

M

c1,c2, … ,c6

RAM

(selected

register)

Let’s stop here…

Computer Architecture: Von Neumann Machine (circa 1940)

Keyboard

Arithmetic Logic

Unit (ALU)

CPU

Registers

Control

Memory

(data

+

instructions)

Input

device

Output

device

Gordon Moore, Andy Grove (and others)

... made it small and fast.John Von Neumann (and others) ... made it possible

Harvard Mark 1 (circa 1940)

Howard Aiken

Keyboard

Arithmetic Logic

Unit (ALU)

CPU

Registers

Control

Memory

(data

+

instructions)

Input

device

Output

device

Processing logic: fetch-execute cycle

Executing the current instruction involves one or more of

the following tasks:

Have the ALU compute some function out = f (register values)

Write the ALU output to selected registers

As a side-effect of this computation,

determine what instruction to fetch and execute next.

Historical End-note: Leibnitz (1646-1716)

“The binary system may be used in place of the decimal system;

express all numbers by unity and by nothing”

1679: built a mechanical calculator (+, -, *, /)

CHALLENGE: “All who are occupied with the reading or

writing of scientific literature have assuredly very often

felt the want of a common scientific language, and

regretted the great loss of time and trouble caused by

the multiplicity of languages employed in scientific

literature:

SOLUTION: “Characteristica Universalis”: a universal,

formal, and decidable language of reasoning

The dream’s end: Turing and Gödel in 1930’s (there are

undecidable problems).

Leibniz’s medallion

for the Duke of Brunswick

logic to gates -...

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