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Functional DescriptionGeneral

The 82C54 is a programmable interval timer/counterdesigned for use with microcomputer systems . It is a generalpurpose, mufti-timing element that can be treated as anarray of 1/0 ports in the system software .

The 82C54 solves one of the most common problems in anymicrocomputer system, the generation of accurate timedelays under software control. . Instead of settinguDtimingloops in software, the programmer confirurracthe 82C54 )omatch his requirements and programsone of thecountersTor the desired delay. After the desired delay, the 82C54 willinterrupt the UU'U. Software overhead is minimal and vari-able length delays can easily be accommodated.

Some of the other computer/timer functions common to micro-c o putters which can be implemented with the 82C54 are:

•

Real time dodo

•

Event counter

•

Digital one-shot

•

Programmable rate generator

•

Square wave generator•

Binary rate multiplier

•

Complex waveform generator

•

Complex motor controller

Data Bus Buffer

This three-state, bi-directional, 8-bit buffer is used to inter-face the 82C54 to the system bus (see Figure 1) . -

4-3

01- Do

WK

Ae

Al

FIGURE 1. DATA BUS BUFFER AND READIWRITE LOGICFUNCTIONS

Read/Write Logic

The Read/Wnte Logic accepts inputs from the system bus andgenerates control signals for the other functional blocks of the82054. Al and AO select one of the three counters or the Con-trol Word Register to be read frorn/written into. A low on theRD input tells the 82C54 that the CPU is reading one of thecounters. A low' on the WR input tells the 82C54 that the CPUis writing either a Control Word or an initial counL Both A5 andWR are qualified by LT; TO and WR are ignored unless the82C54 has been selected by holding ZS low.

SYMBOLDIP PINNUMBER TYPE DEFINITION

CLK 2 18 I CLOCK 2: Clock input of Counter 2 .

A0, Al 19-20 I ADDRESS: Select inputs for one of the three counters or Control Word Register for readlwriteoperations. Normally connected to the system address bus.

Al AO SELECTS

0 0 Counter 00 1 Counter 1

1 0 Counter 2

1 1 Control Word Register

21 I CHIP SELECT : A low on this Input enables the 82C54 to respond to RU and WR signetsL i$ andWR are ignored otherwise .

A6 22 I READ: This Input Is low during CPU read operations .

i ! 23 I WRITE This input is low during CPU write operations.

VCC 24 VCC: The +5V power supply pin. A 0 .1µF capacitor between pins VCC and GND is recommendedfor decou pling .

Control Word RegisterThe Control Word Register (Fgure 2) is selected by theRead/Write 8 the CPU then does awrite operation to the 82054, the data is . Moved in the Con-trol Word Register and is interpreted as a Control Word usedto define the Counter operation .The Control Word Register can only be written to; statusinformation is available with the Read-Back Command .

FIGURE 2. CONTROL WORD REGISTER AND COUNTER

The Control Word Register is shown in the figure; it is notpart of the Counter itself, but its contents determine how theCounter operates .

The status register, shown in the figure, when latched, con-tains the current contents of the Control Word Register andstatus of the output and null count flag . (See detailed expla-nation of the Read-Back command .)

TtLO.actg al counter is labeled CE (for Counting Element). It isa 16-bit presettable synchronous down counter.

82054

4-4

CONTROLWORD

REGISTER

I

GAN

L

OUT

FIGURE 3. COUNTER KRENNAL BLOCK DIAGRAM .

OLM and OIL are two 8-bit latches. OL stands for Xktot1WGV, the -Most significant byte" and¶east sk.Lnin~vnt byte", respectively. Both are normally referredto as one unit and called lust OL These latches normally I*low" the CE, but if a suitable Counter Latch Command is sent tothe 82054, the latches latch' the present count until read bythe CPU and then return to -falowfng" the CE. One latch at atime is enabled by the counters Control Logic to drive the inter-nal bus. This is how the 16-bit Counter conwrxmicates over the8-bit internal bus. Note that the CE itself cannot be read; when-ever you read the count, it is the OL that is being read

FUNCTIONS

Sin there are two 8-bti registers called CRMands

Counter 0, Counter 1, Counter 2

arenom* eefened to as arm will andcalled just CR. When a nowcount is written to the Calmer, the

Thesethreefunctionalblocks are identical_ in operation, so count is stored.u the CR and I~er t anstened totheCE The

only a single Counter will be described . The internal block

Logic allows one register at a time to be loaded fromdiagram of a signal counter is shown in Figure 3 . The Fe--intemal bus. Both bytes are Uansferred to the E sircounters are fully independent Each Counter may operate neously. CRM and CRL are cleared when the Counter is pro-in a differen! Mode . grammed for one byte counts (either most significant byte only

or least significant byte only) the other byte will be zero . Notethat the CE cannot be written into ; whenever a count is written,it is written into the CR.

I

The Control Logic is also shown in the diagram. CLK n,GATE n, and OUT n are all connected to the outside worldthrough the Control Logic .

82C54 System InterfaceThe 82C54 is treated by the system software as an array ofperipheral I/O ports ; three are counters and the fourth is acontrol register for MODE programming.

V

Basically, the select inputs AO, Al connect to the AO, Aladdress bus signals of the CPU . The Z S can be deriveddirectly from the address bus using a linear select method orit can be connected to the output of a decoder .

after power-up, the state of the 82C54 is undefined . TheMode, count value, and output of all Counters are undefined .

How each Counter opealss is determined when it is pro-grammed. Each Counter must be programmed before it canbe used. Unused counters need not be programmed .

Programming the 82C54

Counters are programmed by writing a Control Word andthen an initial count.

All Control Words are written into the Control Word Register,which is selected when Al, AO =11 . The Control Word spec-ifies which Counter is being programmed .

By contrast, initial counts are written into the Counters, notthe Control Word Register. The Al, AD inputs are used toselect the Counter to be written into. The format of the initialcount is determined by the Control Word used .

7

pct

I

A1

A1 AO

AO

ADDRESS BUS (16)

CONTROL BUS

00-07$2054

WK

COUNTER COUNTER COUNTER0

1

2

OUTGATECLK OIIrGQECLK OUTGATECLK

1 T T

I T T

i T T

FIGURE 4. 82C54 SYSTEM INTERFACE

O ns_j

The, programming procedure for the 82C54 is very flexible .Only two conventions need to be remembered:

1,.For Each Counter. theCnntmlWnrrlmi'vt ba wittan

before the initial count is written .

2. Theinitial count must follow the count forrrnat speafled in the&ntrol Word (least signtttcant byte orgy, most signincan byte

, or least significant byte and then most significant byte) .

Since the Control Word Register and the three Counters haveseparate addresses (selected by the Al, AO inputs), and eachControl Word specifies the Counter it applies to (SCO, SC1 bits),no special instruction sequence is required . Any programmingsequence that follows the conventions above is acceptable

Control Word Format

Al, A0=11 ;U3=0; RD =1 ; WR=O

I

MIImI

i 1

D6 I 05

SC0 RW1

D4

RWO

D3

M2 -

02

M'

D1

MO

DO

BCC

82C54

4-5

RW - Read/Write

U - Mode

BCD - Binary Coded Decimal 0'Binary Counter 16-bit

Binary Coded Decimal (BCD) Counter (4 DecadesNOTE : Don't Care bits (X) should be 0 to insure compatibility with

future products.

Possible Programming Sequence

Possible Programming SequenceF

A1 AOControl Word - Counter 0 1 1

Control Word - Counter 1 1 1

Control Word - Counter 2 1 1

LSB of Count - Counter 2 1 0

A1Control Word - Counter0 1 1

LSB of Count - Counter0 0 0

MSB of Count - Counter0 0 0Control Wont - Counter 1 1 1

LSB of Count - Counter 1 0 1

MSB of Count - Counter 1 0 1

Control Word - Counter 2 1 1

LSB of Count - Counter 2 1 0

MSB of Count - Counter 2 1 0

M2 M1 MO

0 0 0 Mode 0

0 0 1 Mode 1

1 0 Mode 2

X 1 1 Mode 3

1 0 0 Mode 4

1 0 Mode 5

RWI RWO

0 0 Counter Latch Command (See Read Operations)0 1 Raad/Write least significant byte only.

41 0 Raad/Write most significant byte only.

A

1 1 Read Write least significant byte first, then mostsignificant byte .

sc1 sco

0 0 Select Counter 0

0 1 Select Counter 1

1 0 Select Counter 2

1 1 Read-Back Command (See Read Operations)

ardware Retriggerable One-Shot

_=will be initially high . OUT will go low on the CLK pulsefollowing a trigger to begin the one-shat pulse, gnd wig remainlow until the Counter reaches zero. OUT will then go high andremain high until the ClK-p-tiIN-Mi ter the next trigger.

After writing the Control Word and initial count, the Counter isarmed. A trigger results in loading the Counter and settingOUT low on the next CLK pulse, thus starting the one-shotpulse N CLK cycles in duration. The one-shot is retriggerable,hence OUT will remain low for N CLK pulses after any trigger .The one-shot pulse can be repeated without rewriting thesame count into the counter. GATE has no effect on OUT.

If a new count is written to the Counter during a one-shotpulse, the current one-shot is not affected unless theCounter is retriggerable . In that case, the Counter is loadedwith the new count and the one-shot pulse continues untilthe new count expires .

CW=12 LSB=3

CLK

GATE

OUT

WR

CLK

GATE

•

INININININI3121110'FFI3I2I

CW=12 LSB=3

AA-L-11 !

CLK

GATE

U OUT

INININININI3I2I1I

CW s 12 LSB = 2

OUT

IN IN IN

ft- -

1 02

4-9

Mode 2: Rate GeneratorThis Mode functions like a divide-by-N counter. It Is typicallyused to generate a Real Time Clock Interrupt OUT will ini-tialy be high. When the initial count has decremented to 1,OUT goes low for one CLK pulse . OUT then goes highagain, the Counter reloads the initial count and the processis repeated. Mode 2 is periodic the same sequence isrepeated irrdefinitely. For an nrhd count of M, ttre sequencerepeats every N CLK cycles.

GATE = 1 enables counting; GATE = 0 dieaWoc ceuntirag . IfGATE goes low during an output Vie, OUT is set 14ghimmediately. A trigger reloads the Cot~ uft the ir0alcount on the next CLK pulse; OUT goes low N C LX poisesafter the trigger. Thus the GATE input can be used b syro-chronize the Counter.

After writing a Control Word and initial count, the Courrler WAbe loaded on the next CLK pulse. OUT goes low N CLKpulses after the initial count is written. This aftws theCounter to be synchronized by software also.

Writing a new count while counting does not affect the ctmntcounting sequence . If a trigger is received after writing a newcount but before the end of the current period, the Counter wdbe loaded with the new count on the rod CLK pulse and count-ing wig continue from the end of the current counting cycle.

CWs14 LSBs3

CLK

GATE

OUT

WK

CLK

GATE

OUT

IN IN ININI3

NCR

CLK

GATE

OUT

IN IN IN IN I4

IN ININI N I3I21113I2I1131

CWs14 LSB=3

CW=14 LSB=4

LSB=5

1 212131211I3I

1 312111514131FIGURE 11 . MODE 2

ROM-8K BYTES

RAM-256 BYTES4

EEPROM-512 BYTES

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