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Master-Thesis

Development of a receiver system for the

RTO

Fabio Di [email protected]

Date: 31.03.2010

Advisors: Prof. Dr. Loffler-Mang

Prof. Dr. Bodenschatz ([email protected])

Master’s program: Mechatronic and Sensor Technology

Department of Engineering Science

Declaration Of Authorship

I, Fabio Di Lorenzo, declare that the presented work was prepared independently and

without using anything other than the named sources.

Gottingen, March 31, 2010

Signed: .....................................................

Acknowledgement

At first I would like to thank my parents and my sister for their encouragement and

support. I thank Prof. Martin Loffler-Mang from the University of Applied Sciences

in Saarbrucken and Prof. Eberhard Bodenschatz from the Max Planck Institute for

Dynamics and Self-Organization in Gottingen for giving me the chance to work at

the MPIDS and for their advise. Moreover I thank the members of the LFPN for a

great time on and off the job.

CONTENTS

Contents

1 Introduction 1

2 RTO-Interface 5

2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.2 RocketIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.2.1 Readout sequence . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.2.2 8b/10b encoding . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2.3 Camera protocol (confidential) . . . . . . . . . . . . . . . . . . 9

2.3 Optical transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.4 Capability of the RTO . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.5 Requirements on the receiver system . . . . . . . . . . . . . . . . . . 12

3 FPGA-Board 13

3.1 Framework Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.1.1 Deframer and Stacker . . . . . . . . . . . . . . . . . . . . . . . 16

3.1.2 VFIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.1.3 Destacker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.1.4 Alerts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.1.5 Packetizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.1.6 PCIe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.1.7 Modification of the Framework Logic . . . . . . . . . . . . . . 17

4 Configuration of the RocketIO 18

4.1 Transfer rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.2 Comma detection and alignment . . . . . . . . . . . . . . . . . . . . . 19

4.3 Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5 Implementing the RocketIO 21

5.1 RocketIO Wrapper Tile . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.2 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.3 Sender . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.4 RocketIO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.5 RocketIO clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.6 RocketIO Channel Interface . . . . . . . . . . . . . . . . . . . . . . . 28

5.7 User constraints file . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6 Transceiver-Board 30

Fabio Di Lorenzo Master Thesis i

CONTENTS

7 Results 32

8 Outlook 33

8.1 FPGA logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

8.2 Host program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

8.3 Digital inputs and outputs . . . . . . . . . . . . . . . . . . . . . . . . 35

8.4 Cameras . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

List of Tables 36

List of Figures 37

References 38

Appendix

A Protocol for 10 bit (confidential)

B Protocol for 12 bit (confidential)

C Protocol for 16 bit (confidential)

D rocketio wrapper tile.vhd (confidential)

E data receiver.vhd (confidential)

F data sender.vhd (confidential)

G rio intf.vhd (confidential)

H rio clocks.vhd (confidential)

I rio chan intf.vhd (confidential)

J Schematic of the Transceiver-Board

K Mechanical drawing of the slot bracket

Fabio Di Lorenzo Master Thesis ii

1 Introduction

1 Introduction

In the Laboratory for Fluid Dynamics, Pattern Formation and Nanobiocomplexity

(LFPN) of the Max-Planck-Institute for Dynamics and Self-Organization, Lagrangian

Particle Tracking1 (LPT) is used to investigate fluid turbulence. LPT is a measure-

ment technology that detects the trajectories of particles moving through a measure-

ment volume. From these trajectories the velocity and acceleration information can

be retrieved.

In experiments analyzed with 3 dimensional LPT, three to four high speed cameras

take images of the measurement volume from different angles. As an example fig. 1.1

shows the Lagrangian Exploration Module (LEM). The LEM is an apparatus with the

shape of an icosahedron, where 12 propellers generate a homogeneous and isotropic

turbulence [1].

Figure 1.1: LPT on the Lagrangian Exploration Module [1]

To make the fluid motion visible, the fluid is seeded with particles that follow the flow.

The particles in the measurement volume are illuminated by a laser, and the cameras

record high speed movies of the particle motion. Since the cameras are synchronized,

corresponding images from all cameras show the measurement volume from different

angles at the same time (fig. 1.2). After recording, the images of each camera are

downloaded to a computer for post processing.

1also known as Particle Tracking Velocimetry (PTV)

Fabio Di Lorenzo Master Thesis 1

1 Introduction

Camera 1 Camera 2

Camera 3 Camera 4

Measurement Volume

Figure 1.2: Measurement volumeImages of the measurement volume are taken fromdifferent angles. The grayscale of the imagesshown in the figure was inverted for ease of illus-tration, i.e. in reality the images show white spotson black ground.

The following description of the post processing procedure is based on reference [2].

The first step is to find all particles in every image and to determine their coordinates

within the image planes of the cameras. In LPT the seeding density is small to reduce

the probability of overlapping particles2. Due to the small seeding density, images

taken for LPT consist of a few bright pixels and large dark areas. By comparing

every pixel to a threshold value, the image is segmented into groups of bright pixels,

that represent individual particles, while dark pixels are discarded.

A particle finding algorithm then determines the position of the particle in the image

plane of the camera. With the particle positions from corresponding images of the dif-

ferent cameras, the particle position in 3D can be determined with a stereo-matching

process. The 3D particle positions from all time steps are then used to track the

particles in time, with the particle trajectories as a result. Different algorithms for

particle finding and particle tracking are discussed in [2], but for this work that part

of the post processing is of less importance.

2One speaks of overlapping particles, when two ore more particles are in a line from the viewpointof a camera, and appear as one particle in the image.


1 Introduction

We now want to focus on the measurement procedure. In a turbulent flow very fast

processes occur, i.e. to observe them cameras that are capable of high frame rates are

needed. Hence, the cameras used for LPT in the LFPN are from Vision Research’s

Phantom V -Series. As an example, with a resolution of 480x480 pixels the Phantom

V10 can take images at a frame rate of 6 kHz. This corresponds to a data rate of

approximately 1.4GB/s. As explained before, the images have to be downloaded to a

computer for post processing. This is done by use of the Gigabit-Ethernet interface of

the cameras. As transfer rate of the Gigabit-Ethernet 28MB/s was measured. Due

to this difference downloading the images to a computer in real-time is not possible

with Gigabit-Ethernet. Therefore, the images are stored in the internal RAM of

the cameras and are downloaded afterwards. That leads to the problem, that for

the use of four cameras, one second of acquisition involves 4·1.4GB/s28MB/s

· 1 s = 200 s of

downloading time. During this time no data can be acquired.

Figure 1.3 shows a plot of the number of particles (in arbitrary units) against time

in minutes. Each data point represents a measurement of 1 second. The time in

between two data points is the downloading time. The fact that the number of

particles decreases with time shows that valuable information for the statistics gets

lost during the time between the measurements. The decrease of the number of

particles in the measurement volume is due to the density mismatch of particles and

fluid. The blue curve shows that even tracer particles, which are considered to be

neutrally buoyant with a density of only 6% bigger than the density of water, sink

below the measurement volume. The red curve shows that the decrease is faster for

heavy particles (glass particles, 4 times heavier than water).

0 50 100 1500

5

10

15

Time in [min]

Nda

ta in

[a.

u.]

Tracer particlesGlass particles

Figure 1.3: Decrease of particle density in the measurement volume


1 Introduction

To solve this problem Chan et al [3] showed that a real-time image compression can be

performed. The basis for this is the fact, that the seeding density in LPT experiments

is low and only the bright pixels are needed for the described post processing process.

They developed an FPGA-Board that receives the high speed images of the camera,

performs the thresholding and sends only the bright pixels with coordinates to a

computer. Due to this sparsification of the images, the data rate was reduced below

the writing speed of the hard drive and the relevant data of the high speed movies

could be saved in real time. Compression rates3 of 100-1000 were achieved at a frame

rate of 500Hz [3].

The aim of this work is to develop a similar system for the much faster Phantom

cameras. These provide, besides the Gigabit-Ethernet interface, an optical output,

the so called Real-Time Output (RTO). On this RTO, raw sensor data are sent out

at a higher transfer rate (1.5552GB/s including overhead for Phantom V7 e.g.) than

would be possible with Gigabit-Ethernet. The RTO will be described in section 2.

An FPGA-Board, the X5-TX, was purchased to receive the RTO signals and to write

the data on the hard drive of a computer. This FPGA-Board and the logic provided

with it is explained in section 3. The necessary interface to receive the RTO signals is

called RocketIO transceiver and was not implemented in the provided logic. Hence,

configuration and implementation of the RocketIOs in the FPGA logic was the main

task of this work and is described in the sections 4 and 5. Since the RTO sends optical

signals and the X5-TX provides eSATA connectors to access the RocketIOs, a circuit

board for conversion of optical to electrical signals was developed. This circuit board

was called Transceiver-Board and is topic of section 6. The results are presented in

section 7 and an outlook is given in section 8.

3The compression rate depends on the seeding density


2 RTO-Interface

2 RTO-Interface

This section describes the Real-Time-Output of the Phantom V7.2. Understanding

how the signal is generated and which information it carries will lead to important

requirements for the receiving system. Differences to other camera models like the

Phantom V10 will be pointed out. These differences determine which properties of

the receiver system have to be flexible, so it can be designed to be compatible with

a variety of camera models.

2.1 Overview

The cameras have an built in Field Programmable Gate Array (FPGA). Specifically,

it is the model Virtex II Pro from Xilinx. The FPGA reads the data from the CMOS

chip and sends them to an optical transmitter using its RocketIO ports (fig. 2.1).

The optical transmitter converts the differential electrical signals from the RocketIO

ports to optical signals and outputs these through an MTP/MPO receptacle, shown

in fig. 2.2.

Se

nso

r

Ro

cke

tIO

opticalTransmitter

Virtex IIpro

Camera

Figure 2.1: Camera block diagram

Figure 2.2: Real Time Output


2.2 RocketIO

Different camera models use a different number of RocketIO channels and have dif-

ferent transfer rates. In tab. 2.1 the values for various cameras are shown.

camera no. of transfer ratemodel channels per channel

V7.2 8 1.5552 Gb/sV10 6 2.125 Gb/sV12 8 2.125 Gb/sV640 8 2.125 Gb/s

Table 2.1: Transfer rates and channel numbers [4]

2.2 RocketIO

The Xilinx FPGAs provide versatile multi-gigabit transceivers, called RocketIO trans-

ceivers. The RocketIOs are used to send the camera data and can be calibrated

to satisfy different standards like Gigabit-Ethernet, PCI-Express or Infiniband, for

example. Vision Research uses a customized protocol that will be described in sec-

tion 2.2.3.

2.2.1 Readout sequence

For transmission, every image (frame) is split up to all available RocketIO channels.

Every channel sends rows of pixels from left to right, starting with the rows in the

middle of the image. As shown in fig. 2.3 and fig. 2.4, one half of the channels send

the upper half of the image, while the other half of the channels send the lower half.

CH1

CH1

CH2

CH2

CH3

CH3

CH4

CH4

CH5

CH5

CH6

CH6

CH7

CH7

CH8

CH8

Figure 2.3: Readout sequencefor 8 channels [4]

CH1

CH1

CH2

CH2

CH3

CH3

CH4

CH4

CH5

CH5

CH6

CH6

Figure 2.4: Readout sequencefor 6 channels [4]


2.2 RocketIO

2.2.2 8b/10b encoding

Before data are sent, the RocketIO transceiver performs 8b/10b encoding on every

data byte, i.e. that every 8 bit character is assigned to a 10 bit symbol according to

a look-up-table [6]. The serial bit stream sent out of the RTO is a sequence of these

10 bit symbols.

One reason to perform 8b/10b encoding is that some of the 8 bit characters do not

provide enough bit transitions for the receiver to recover a clock out of the data

stream. In tab. 2.2 some of these unfavorable characters are listed. The table shows

that these characters are assigned to symbols that provide more transitions and never

more than five 1s or 0s in a row.

Another reason for 8b/10b encoding is to keep the data stream DC-balanced. A signal

is considered as DC-balanced if the difference between the number of transmitted 1s

and the number of transmitted 0s (the disparity) is at most two. Therefore in the

look-up-table every 8 bit character in fact corresponds to two 10 bit symbols, one

with six 1s (RD-) and one with six 0s (RD+) (tab. 2.2). The RocketIO transceiver

increases or decreases the disparity by choosing either an RD+ or an RD- symbol to

send.

The full 8b/10b look-up-table is listed in [6].

Data Byte 8b Character 10b Symbol 10b SymbolName HGF EDCBA RD- RD+

D3.0 000 00011 110001 1011 110001 0100D0.1 001 00000 100111 1001 011000 1001D31.3 011 11111 101011 0011 010100 1100D28.7 111 11100 001110 1110 001110 0001

Table 2.2: Extract of the 8b/10b look-up-table [6]


2.2 RocketIO

Even with every 8 bit data character being assigned to two 10 bit symbols, there

are still half of the possible 10 bit combinations left. Most of them are unused, but

some are assigned to 8 bit control characters, the so called K-Characters. The K-

Characters used by the FPGA in the Phantom cameras are listed in tab. 2.3. This

document will refer to the K-Characters by their meaning for the protocol.

The full table of valid K-Characters is listed in [6].

Control Byte Hex 8b Character 10b Symbol 10b SymbolMeaning

Name Value HGF EDCBA RD- RD+

K28.4 9C 100 11100 001111 0010 110000 1101 SOF1

K27.7 FB 111 11011 110110 1000 001001 0111 SOP2

K29.7 FD 111 11101 101110 1000 010001 0111 EOP3

K28.5 BC 101 11100 001111 1010 110000 0101 CommaK28.0 1C 000 11100 001111 0100 110000 1011 IdleK28.2 5C 010 11100 001111 0101 110000 1010 Non-IdleK28.3 7C 011 11100 001111 0011 110000 1100 Non-Idle

Table 2.3: Extract of K-Characters [6]

1SOF = Start Of Frame2SOP = Start Of Packet3EOP = End Of Packet


2.2 RocketIO

2.2.3 Camera protocol (confidential)

Due to a non-disclosure agreement with Vision Research, the information in this

section is confidential.

Figure 2.5: Transmission of packets

Figure 2.6: Data packet [5]

Table 2.4: Transfer protocol for 8 bit pixels [5]


2.3 Optical transmitter

2.3 Optical transmitter

After 8b/10b encoding, the 10 bit sequences of all RocketIO channels are sent to

the optical transmitter as differential electrical signals. The optical transmitter is a

ZL60101 TX (fig. 2.7) from Zarlink Semiconductor. It provides 12 channels to convert

electrical signals to optical signals of 850nm wavelength [7]. It can be connected to a

fiber cable with an MTP/MPO connector (fig. 2.8). These cables have 12 fiber cores.

As shown in tab. 2.1 only 6 or 8 channels are used, depending on the camera type.

Therefore the channels in the middle of ZL60101 TX are not used [5].

Figure 2.7: Optical transmitter ZL60101 TX [7]

Figure 2.8: Fiber cable with MTP/MPO connector


2.4 Capability of the RTO

2.4 Capability of the RTO

Unfortunately, the RTO is not fast enough for transmission of images at the highest

possible frame rate and full resolution. If the amount of data caused by the requested

frame rate and image size is to large, the RTO will automatically output the images

at a submultiple of the desired frame rate [5]. This section presents an equation to

calculate the maximum possible frame rate for a given image size.

Eq. 1 can be formed from the protocol described in tab. 2.4. It shows that the

amount of data to be transferred caused by one frame, multiplied by the frame rate

equals the transfer rate. Due to 8b/10b encoding the transfer rate has to be reduced

by 20% to fulfill the equation.

(FSP + n ·DP + IFG) fmax = TF · 0.8 (1)

• FSP : frame start packet including SOP and EOP (42B)

• n : number of data packets

• DP : data packet including SOP, EOP, Comma and IPG (140B)

• IFG : inter frame gap, minimum size is used to calculate the maximum

framerate (1600B)

• fmax : maximum frame rate for a given image size

• TF : transfer rate

The number of data packets is a function of the image size, the depth of the pixels

and the number of channels of the camera, taking into account that one data packet

carries 128B of information (eq. 2).

n =xy · d

ch · 128B(2)

• n : number of data packets

• xy : resolution

• d : pixel depth

• ch : number of channels


2.5 Requirements on the receiver system

With eq. 2 in eq. 1, the maximum frame rate for a given image size can be calculated

(eq. 3).

fmax =TF · 0.8(

FSP + xy·dch·128B ·DP + IFG

)fmax =

TF · 0.8(xy·dch

140128

+ 1642B) (3)

An example calculation (eq. 4) shows the maximum frame rate that can be outputted

by the RTO of a Phantom V7.2 (8 channels, 8 bit depth, 1.5552Gb/s) for a resolution

of 256x256 pixels.

fmax =1.5552Gb/s · 0.8(2562 B

8140128

+ 1642B)

fmax = 14.67 kHz (4)

For comparison, if images are written only to the internal RAM of the camera, one

can record with up to 36.7 kHz at that resolution [8]. However, the RTO outputs, in

this case, at a total data rate of 2562B · 14.67 kHz = 961.4MB/s. This is about a

factor of 100 faster than transferring through Gigabit-Ethernet, which was measured

to transfer at approximately 10MB/s for the same camera.

2.5 Requirements on the receiver system

The requirements on the receiver system arising from the previous sections are:

• it has to receive the optical signals of up to 2.125Gb/s per channel and convert

them to electrical signals for processing with an FPGA

• the FPGA has to be able to perform 8b/10b decoding

• it has to be flexible in the number of channels and transfer rate in order to be

compatible with all types of cameras

• it needs a fast interface to a computer for storing image data


3 FPGA-Board

3 FPGA-Board

To match the requirements on the receiver system while keeping the task of hardware

development small, we decided to use an off-the-shelf FPGA module that provides

the necessary interfaces and software. After reviewing commercially available FPGA

modules on the market, we chose the module X5-TX Rev. B (fig. 3.1) from Innovative

Integration:

Advantages: + Integrated FPGA is a Virtex 5 SX95T from Xilinx and provides

RocketIOs

+ The pins of 8 RocketIO channels are routed to eSATA

connectors (fig. 3.1)

+ FPGA logic is provided by the manufacturer and is fully

customizable

+ An adapter card provides a fast interface (PCIe) to a host

computer (fig. 3.1)

+ Host computer programs for communication with and controlling

of the FPGA board are provided by the manufacturer and are

fully customizable

+ It provides an adjustable PLL-Clock. This is important to

source the RocketIOs with different frequencies to match the

different transfer rates of the cameras.

Disadvantages: - It does not provide the necessary optical interface. That means a

circuit board has to be developed which provides an optical

receiver and routes the converted signals to eSATA connectors,

see section 6.

- RocketIOs are not implemented in the FPGA logic, see section 4

and section 5.


3 FPGA-Board

The X5-TX is a D/A converter card. It is designed to read digital data from the

hard drive of the host computer, convert these to analog signals and provide them

on SMA outputs. Figure 3.1 shows the X5-TX plugged onto the adapter card that

provides the connectors. The goal is to change the FPGA logic so that it reads data

from the camera on the RocketIO inputs and writes these to the hard drive.

Figure 3.1: X5-TX with adapter card

As a starting point, the FPGA logic delivered by the board manufacturer, the so called

Framework Logic, was used. The following section describes briefly the structure of

the Framework Logic and shows what has to be modified for the X5-TX to become

a receiver card for the RTO.


3.1 Framework Logic

3.1 Framework Logic

The Framework Logic described here is not the official version usually delivered with

the X5-TX. It is a version modified by the customer service of Innovative Integration.

Basically all functions related to D/A conversion were removed. The rest is important

for board to host communication. To keep it simple this document will refer to this

version as Framework Logic.

Figure 3.2 shows a block diagram of the components of the Framework Logic that are

relevant for board to host communication. One can see that in this state the FPGA

just receives data from the host computer through the PCIe interface and sends them

right back. This loopback structure is the starting point for further modifications.

Host

Com

pute

r

X5-TX

PCIe

Deframer Stacker

Packetizer Destacker

Alerts

VFIFO

Figure 3.2: Framework Logic block diagram

The individual components shown in the block diagram will be explained in more

detail in the following sections. The informations about these components are taken

from [9].


3.1 Framework Logic

3.1.1 Deframer and Stacker

The components Deframer and Stacker receive data packets from the PCIe interface

and are used to interpret the header information and rout the data to their destination

device.

3.1.2 VFIFO

The X5-TX is equipped with four 64M x 16 SRAM devices. Together they form the

component VFIFO (virtual first in first out). A FIFO is used as a buffer if data is

passed from one clock domain to an other. It simply stores data from the Stacker

until the Destacker is ready to receive them.

3.1.3 Destacker

The component Destacker receives 128 bit words from the VFIFO and passes these

on to the Packetizer as two 64 bit words.

3.1.4 Alerts

In the component Alerts, critical system parameters like the buffer state or tempera-

ture are monitored. If an alert occurs a packet is sent to the host computer through

Packetizer and PCIe interface for interpretation by the host software.

3.1.5 Packetizer

The component Packetizer prepares data packets to be sent through the PCIe in-

terface. It attaches a header to each packet that will be interpreted by the host

software.

3.1.6 PCIe

The Virtex-5 SX95T has 16 RocketIO transceivers in total. Eight of them are used

by the Framework Logic for the 8 lane PCIe interface to the host computer. The

component PCIe encapsulates the logic needed for fast data transfer between host

and FPGA board. It sends data from the Packetizer to the computer and data from

the computer to the Deframer. The component additionally provides a so called

command channel for status and control of the FPGA.


3.1 Framework Logic

3.1.7 Modification of the Framework Logic

The goal is to receive signals from the RocketIO transmitters of the camera with the

FPGA and write them to a file on the host computer through the PCIe interface.

As shown in fig. 3.2, the Framework Logic already provides components to stream

data from the FPGA to the host. However, in order to receive camera data the

RocketIOs have to be implemented into the logic. Then the data can be routed from

the RocketIOs to the VFIFO and make its way through Destacker, Packetizer and

PCIe interface. Since in the planned application no data streaming from the host to

the FPGA is intended, Deframer and Stacker will not be needed (fig. 3.3).

Host

Com

pute

r

X5-TX

PCIe

Packetizer Destacker

Alerts

VFIFO

RocketIO

Camera

RocketIO

Figure 3.3: Framework Logic block diagram with RocketIO

The red block called RocketIO in (fig. 3.3) shows what was added to the Framework

Logic to enable the X5-TX to receive the camera signals. In the sections 4 and 5

this red block will be described in more detail. The circuit board that had to be

developed to convert the optical signals to electrical signals is the topic of section 6.


4 Configuration of the RocketIO

4 Configuration of the RocketIO

To implement RocketIO transceivers a component from the Xilinx library, a so called

Xilinx primitive, is used. In the Virtex 5, the primitive encapsulating RocketIOs

is called GTP Dual. A GTP Dual operates two RocketIO transceivers, hence two

transmitters and two receivers. This section deals with the configuration of the GTP

Dual. It is configured by assigning values to configuration ports and attributes of the

component. For test purposes the RocketIO transmitters are also configured.

Table 4.1 and table 4.2 list the most important configuration ports and attributes, the

rest is either self explanatory or assigned to its default value. A full list is provided

in [6].

Attribute Value Used for

PLL DIVSEL FB 2PLL DIVSEL REF 1PLL TXDIVSEL COMM OUT 1 Transfer ratePLL TXDIVSEL OUT x 1PLL RXDIVSEL OUT x 1ALIGN COMMA WORD x 1

Comma detectionand alignment

COMMA DOUBLE x FALSEMCOMMA 10B VALUE x 1010000011PCOMMA 10B VALUE x 0101111100

Table 4.1: Attributes of the GTP Dual [6]

Port Value Used for

INTDATAWIDTH 1Transfer rateRXDATAWIDTHx 1

TXDATAWIDTHx 1RXDEC8B10BUSEx 1

Comma detectionand alignment

TXENC8B10BUSEx 1RXCOMMADETUSEx 1RXENMCOMMAALIGNx 1RXENPCOMMAALIGNx 1TXPOLARITY0 0

PolarityTXPOLARITY1 1RXPOLARITY0 0RXPOLARITY1 1

Table 4.2: Configuration ports of the GTP Dual [6]


4.1 Transfer rate

The following sections contain brief descriptions of the configurations made with the

listed configuration ports and attributes. A configuration port or an attribute with

an ‘x’ at the end of its name indicates that this parameter appears twice, one for each

channel of the GTP Dual.

4.1 Transfer rate

As shown in tab. 2.4, the incoming data are handled as 16 bit words [5]. Therefore

INTDATAWIDTHx, RXDATAWIDTHx and TXDATAWIDTHx have to be set to 1

[6]. To match the transfer rate of the camera the frequency of the clock provided at

the main clock input CLKIN of the GTP Dual is very important. This frequency

is set to 1/20 of the transfer rate (tab. 2.1), since 20 bits of the incoming 10 bit

symbols have to be gathered to produce one 16 bit word after 8b/10b decoding. As

a result CLKIN will be fed with 77.76MHz for a transfer rate of 1.5552Gb/s or

with 106.25MHz for 2.125Gb/s, see section 5.5. In addition to providing one of the

mentioned frequencies (depending on the camera model) several parameters have to

be set according to eq. 5 taken from [6].

PLL DIV SEL FB

PLL DIV SEL REF=

transfer rate

CLKIN · 10=

1.5552GHz

77.76MHz · 10= 2 (5)

As shown in eq. 5 the ratio between PLL DIVSEL FB and PLL DIVSEL REF has

to be 2. Therefore PLL DIVSEL FB was set to 2 and PLL DIVSEL REF was set to

1. With this configuration it is possible to switch between the two transfer rates just

by changing the frequency at CLKIN.

The GTP Dual provides the possibility to have different transfer rates on its two chan-

nels. Since this is not needed the dividers for this purpose - PLL RXDIVSEL OUT x,

PLL TXDIVSEL COMM OUT, PLL TXDIVSEL OUT x - are all set to 1.

4.2 Comma detection and alignment

While receiving a bit stream from the camera, the receiver initially does not know

where a 10 bit symbol starts and where it ends. Therefore the camera sends a Comma

before every packet (tab. 2.4). A Comma detection and alignment circuit in the GTP

Dual searches for this K-Character in the bit stream and aligns to its boundaries [6].

This section explains how to configure the Comma detection and alignment circuit.

8b/10b decoding has to be enabled by setting RXDEC8B10BUSEx and TXENC8B-

10BUSEx to 1. The Comma detection and alignment circuit is enabled by as-

signing 1 to RXCOMMADETUSEx, RXENMCOMMAALIGNx and RXENPCOM-


4.3 Polarity

MAALIGNx. To clarify which K-Character is used as Comma the attribute PCOM-

MA 10B VALUE x is set to 0101 111100, and MCOMMA 10B VALUE x is set to

1010 000011. These values correspond to the 10 bit symbols for Comma listed in

tab. 2.3. As mentioned in section 2.2.2 every 8 bit character corresponds to two

10 bit symbols for disparity control. Therefore the GTP Dual distinguishes be-

tween PCOMMA and MCOMMA. The protocol used by the camera sends either

MCOMMA or PCOMMA. Therefore COMMA DOUBLE x has to be set to FALSE.

Setting ALIGN COMMA WORD x to 1, tells the receiver that there is no preferred

position in the internal data path, which means that if a Comma is found and the

receiver aligns to it, the Comma can be written to the upper or to the lower byte of

the 16 bit word.

4.3 Polarity

On the X5-TX the pins of both receivers of a GTP Dual are routed to one eSATA

connector on the adapter board. The same is done for the pins of the transmitters

(fig. 3.1). In both cases the polarity of channel one is switched to avoid vias [10].

For compensation RXPOLARITY1 and TXPOLARITY1 have to be set to 1, while

RXPOLARITY0 and TXPOLARITY0 remain 0.


5 Implementing the RocketIO

5 Implementing the RocketIO

The following sections describe how the RocketIOs were implemented into the Frame-

work Logic. For this purpose several components were programmed in VHDL (very

high speed integrated circuit hardware description language), just like the Framework

Logic. The following description of the components starts with the components on

the lowest hierarchy level and moves on to the higher ones.

5.1 RocketIO Wrapper Tile

The rocketIO wrapper tile encapsulates the Xilinx primitive GTP Dual described in

section 4. This component only provides the most important inputs and outputs of

the GTP Dual to other components at the same hierarchy level (fig. 5.1). The rocke-

tIO wrapper tile itself is encapsulated in the component RocketIO interface (rio intf).

The most important inputs and outputs are listed in tab. 5.1. Appendix D shows the

VHDL code of the rocketIO wrapper tile.

Port name Direction Function

RXDATAx OUTReceived 16 bit words (tab. 2.4) after8b/10b decoding

RXCHARISKx OUT

After 8b/10b decoding data characterscannot be distinguished from K-Characters,this 2 bit value indicates if the upper or thelower byte of the received 16 bit word is aK-Character

TXOUTCLK OUT

A clock generated by the GTP Dualaccording to the frequency of CLKIN andthe settings for the transfer rate, seesection 4.1. The frequency of TXOUTCLKis transfer rate/10 and used to generateUSRCLK and USRCLK2, see section 5.5

TXDATAx IN 16 bit word to be sent over the RocketIO

TXCHARISKx IN2 bit value that indicates if the upper or thelower byte of TXDATAx is a K-Character

USRCLK INClock needed for the internal logic of theGTP Dual. The frequency is transferrate/10

USRCLK2 INClock needed for the interface betweenGTP Dual and the Framework Logic. Thefrequency is transfer rate/20

CLKIN IN Reference clock for the transfer rate settings

Table 5.1: Inputs and outputs of rocketIO wrapper tile [6]


5.1 RocketIO Wrapper Tile

Figure 5.1: RocketIO interface


5.2 Receiver

5.2 Receiver

The component data receiver handles the data stream of one RocketIO receiver chan-

nel and is therefore instantiated twice in rio intf (fig. 5.1). It interprets the K-

Characters of the incoming data stream and raises the output DATA RDY TRIG

to 1 if an SOP is found and resets it to 0 if an EOP is found (tab. 2.4). Hence,

DATA RDY TRIG indicates the following component if the data is part of a packet

or not, so that the Idle and Non-Idle sequences of the IPG and IFG can be skipped.

Moreover the data receiver calculates the CRC of the incoming data and compares it

to the CRC at the end of each packet. In the current design a wrong checksum has

no consequence, but later this can be used to detect transmission errors.

The most important inputs and outputs are listed in tab. 5.2. Appendix E shows the

VHDL code of the data receiver.


DATAIN INInput for 16 bit words received from theRXDATAx of the rocketIO wrapper tile

CHAR IS K INInput for the 2 bit value received from theRXCHARISKx of the rocketIO wrapper tile

DATAOUT OUTData from DATAIN are routed toDATAOUT without being changed

DATA RDY TRIG OUTA signal that indicates whether the 16 bitword in DATAOUT is part of a packet ornot

Table 5.2: Inputs and outputs of data receiver


5.3 Sender

5.3 Sender

The component data sender was implemented for test purposes. It sends the same

data stream to both transmitter channels of the rocketIO wrapper tile and is encap-

sulated in rio intf (fig. 5.1). This data stream consists of a repeated data packet of

the form shown in fig. 2.6. In the current design the 128 data characters of the data

packet are all 0xFF, and therefore the data stream corresponds to a white image.

This data stream can be received by connecting an eSATA connector of the Rocke-

tIO transmitters to an eSATA connector of the RocketIO receivers (fig. 3.1). For the

development of the data receiver it was important to have this source of known data.

The outputs of data sender are listed in tab. 5.3. Appendix F shows the VHDL code

of the data sender.


CHAR IS Kx OUTOutput of a 2 bit value for TXCHARISKxof the rocketIO wrapper tile

DATAOUTx OUTData output for TXDATAx of therocketIO wrapper tile

Table 5.3: Outputs of data sender


5.4 RocketIO Interface


The component rio intf was programmed for structural purposes. The components ex-

plained in the previous sections - rocketio wrapper tile, data receiver and data sender

- are all encapsulated and connected with each other inside the rio intf (fig. 5.1). By

providing access only to important inputs and outputs of these components, the

rio intf becomes the interface for one GTP Dual, i.e. two RocketIO transceivers. In

order to receive data from 8 RocketIO transceivers rio intf has to be instantiated four

times in the RocketIO Channel Interface (fig. 5.2).

The most important inputs and outputs of rio intf are listed in tab. 5.4. Appendix

G shows the VHDL code of the rio intf.


DATAOUTx OUTProvides access to DATAOUT of thedata receiver

DATA RDY TRIGx OUTProvides access to DATA RDY TRIG of thedata receiver

TXOUTCLK OUTProvides access to TXOUTCLK of therocketio wrapper tile

USRCLK INProvides access to USRCLK of therocketio wrapper tile

USRCLK2 INProvides access to USRCLK2 of therocketio wrapper tile

CLKIN INProvides access to CLKIN of therocketio wrapper tile

Table 5.4: Inputs and outputs of rio intf



Figure 5.2: RocketIO channel interface


5.5 RocketIO clocks

5.5 RocketIO clocks

The component rio clocks provides USRCLK and USRCLK2 to the rio intf by deriv-

ing these clocks from TXOUTCLK. Figure 5.2 shows that TXOUTCLK is routed from

one rio intf to rio clocks, while USRCLK and USRCLK2 are routed from rio clocks

to all four instantiated rio intf.

As explained in tab. 5.1 TXOUTCLK and USRCLK have the frequency of 1/10 of

the transfer rate, while USRCLK2 has the frequency of 1/20 of the transfer rate.

A digital clock manager in rio clocks ensures USRCLK and USRCLK2 have these

frequencies and are edge aligned to each other. This way of clocking is suggested in

[6].

The most important inputs and outputs of rio clocks are listed in tab. 5.5. Appendix

H shows the VHDL code of the rio clocks.


TXOUTCLK INTXOUTCLK from therocketio wrapper tile. The frequency istransfer rate / 10

USRCLK OUTUSRCLK for the rocketio wrapper tile. Thefrequency is transfer rate / 10. It is edgealigned to USRCLK2

USRCLK2 OUTUSRCLK2 for the rocketio wrapper tile.The frequency is transfer rate / 20. It isedge aligned to USRCLK

Table 5.5: Inputs and outputs of rio clocks


5.6 RocketIO Channel Interface

5.6 RocketIO Channel Interface

The component rio chan intf is implemented on the top level in the Framework Logic

and corresponds to the red block in fig. 3.3. It encapsulates the components rio clocks

and four rio intf (fig. 5.2) and is therefore the interface between the eight RocketIO

transceivers and the Framework Logic.

The most important inputs and outputs of rio chan intf are listed in tab. 5.6. Ap-

pendix I shows the VHDL code of the rio chan intf.


PLL INProgrammable PLL clock routed through toCLKIN of the rocketio wrapper tile. Thefrequency has to be transfer rate / 20

DATAOUT OUT128 bit wide signal merged from the eight16 bit wide outputs of the data receiver. Itis sent to the data input of the VFIFO

DATA RDY OUTSignal sent to the write enable input of theVFIFO. It indicates to the VFIFO whennew data is available

Table 5.6: Inputs and outputs of rio chan intf


5.7 User constraints file

5.7 User constraints file

The final step to implement the RocketIOs is to connect the programmed logic to the

hardware, i.e. every instantiated GTP Dual has to be assigned to the hardware core

it represents [6]. This is done by inserting the following entries in the so called user

constraints file (cam intf.ucf).

INST rio_channel_interface/rio_chan01/rocketio_rx/gtp_dual_i

LOC=GTP_DUAL_X0Y0;


LOC=GTP_DUAL_X0Y5;


LOC=GTP_DUAL_X0Y6;


LOC=GTP_DUAL_X0Y7;

The first part of the entry starting with INST is followed by a hierarchy-path that

identifies one specific GTP Dual instantiated in the logic. Every component is in-

stantiated with a unique instantiation name. To keep it simple the instantiation

names were neglected before. The hierarchy-paths consist of the instantiation names

of the previously described components and point to the individual GTP Duals. For

clarification, written with component names the hierarchy-path is:

rio_chan_intf/rio_intf/rocketio_wrapper_tile/gtp_dual

The reader might compare to fig. 5.2 and fig. 5.1.

The second part of the entry starting with LOC assigns the component specified by the

hierarchy-path to its physical unit. As mentioned before, the FPGA integrated in the

X5-TX provides eight GTP Duals, called GTP DUAL X0Y0 to GTP DUAL X0Y7

[6]. Four of them are in use for the PCIe [10]. The rest is enabled to receive the RTO

signals by the entries in the user constraints file mentioned above.


6 Transceiver-Board

6 Transceiver-Board

The Transceiver-Board (fig. 6.1) was developed to convert the optical signals from

the camera to differential electrical signals for the RocketIOs. This job is done by the

optical receiver ZL60102 RX from Zarlink Semiconductors which is the counterpart

of the optical transmitter used in the cameras, see section 2.3.

Figure 6.1: Transceiver-Board

As explained before the camera uses the eight outer channels of the optical transmit-

ter. Hence, the electrical outputs of the eight outer channels of the optical receiver

are routed to four eSATA connectors. Thus the Transceiver-Board can be connected

to the X5-TX by common eSATA cables. Since the X5-TX is plugged in a PCIe slot

of the host computer, the Transceiver-Board is equipped with a slot bracket and is

also mounted in the computer. For power supply a receptacle was chosen that fits the

power supply connectors available in the computer. The optical receiver is accessible

through the slot bracket from outside the computer (fig. 6.2).

The Transceiver-Board is equipped with an MDR68 connector that routes its signals

through to an MDR36 connector, accessible through the slot bracket. The MDR68

connector is meant to be connected to the MDR68 connector of the X5-TX. This was

done to make the 16 digital inputs and outputs of the X5-TX accessible from outside

the computer. At present the digital inputs and outputs are not used.


6 Transceiver-Board

Figure 6.2: X5-TX and Transceiver-Board in the host computer

The schematic of the Transceiver-Board is shown in Appendix J and the mechanical

drawing of the slot bracket is shown in Appendix K.


7 Results

7 Results

The X5-TX with the modified Logic in combination with the Transceiver-Board form

a receiver system for the RTO of the Phantom cameras. Data of all channels excluding

the inter frame gaps is written to a binary file. Then MATLAB is used to assemble

the data to an image.

A test image of 64 x 64 pixels from a chessboard was taken with the Phantom V7.2.

Figure 7.1 shows this image. As mentioned before the RTO is sending raw images.

Hence, every pixel has to be corrected by subtracting an offset and then multiplying

a gain. The offsets and gains are different for every pixel and are provided in the

.stg-files of each camera [4]. In the .stg-file, the pointer to the offsets is at address1

0x34 and the pointer to the gains is at address 0x40. Both pointers are little-endian 4

byte numbers and represent the addresses where the first offset and the first gain are

listed. The values are listed from left to right, starting with bottom row. MATLAB

is used to perform the correction. Figure 7.2 shows the corrected image.

Figure 7.1: Raw image Figure 7.2: Corrected image

1The address of a byte is the number of the byte in the .stg-file, starting to count on zero.


8 Outlook

8 Outlook

8.1 FPGA logic

The developed receiver system is now capable to receive the data output by the

RTO. However, due to the limitation in the writing speed of common hard drives

(≈ 70 − 80MB/s), images of high resolution recorded at high frame rates cannot

be stored in real-time. Therefore future improvements will aim on performing a

sparsification on the data stream.

As mentioned before, the images taken for Lagrangian Particle Tracking consist of

large dark areas and very few bright pixels where particles are represented. Only

the bright pixels are of interest for post processing and there is no need to save dark

ones, too. Hence, the sparsification algorithm will be implemented in the X5-TX

logic and compare received pixels to a threshold. Only if the pixel is brighter than

the threshold it will be saved with its coordinate. The following example shows that

the data rate will be reduced below the writing speed limit of hard drives.

If images with a resolution of 256x256 are recorded at the highest possible frame rate

for the RTO of 14.67 kHz (section 2.4) the data rate is:

data rate = 2562B · 14.67 kHz

data rate = 961.41MB/s

This number represents pure image data after all K-Characters and overhead has

been filtered out. It is too high to be written on hard drives.

The sparsification algorithm would write only the bright pixels with one coordinate to

file. One coordinate is sufficient, since the information from which channel the pixel

came is available and does not require memory. The size of this coordinate depends

on the resolution and is 2562/8 = 8192=13 bit for this example, if an 8 channel camera

is used. Assuming 500 particles per frame and each represented by five 8 bit-pixel the

data rate would be:

data rate = 500 · 5 · (8 bit + 13 bit) · 14.67 kHz

data rate = 96.4MB/s

This shows, using sparsification can reduce the data rate (and the amount of data

produced by an experiment) drastically, 90% in this example. Even if the data rate

is still too high for a common hard drive, a simple RAID0 system can easily handle

data rates in that range. Hence, this improvement will make it possible to stream


8.2 Host program

only the needed data of high speed movies directly to the hard drive and increase the

duration of the experiment. A movie recorded into the 4GB RAM of the Phantom

V7.2 will last only:

experiment duration =4GB

961.41MB/s

experiment duration = 4.16 s

While a movie recorded to the hard drive with a size of 4GB after sparsification will

last:

experiment duration =4GB

96.4MB/s

experiment duration = 41.5 s

Moreover the size of the hard drive can be increased easily and with low costs. A hard

drive of 1TB, full with sparsified data would contain 2.9 hours of a continuous ex-

periment. This will make it possible to acquire data efficiently as long as the particle

density in the measurement volume is high enough (fig. 1.3). Moreover slow processes

can be observed, together with the fast ones, with a high temporal resolution.

8.2 Host program

The host program used at this stage of the project is the Wave Example delivered by

Innovative Integration. Just like the X5-TX it was developed for D/A conversion of

data from a file. It is only used to start and stop the process of writing camera data

to file.

As mentioned before it is fully customizable. Hence, it will be adapted to the applica-

tion. The user could give information about the experiment like frame rate, resolution

and camera model to the program and therefore to the X5-TX. Then the FPGA can

configure itself to the number of channels in use, for example. Moreover the host

program could inform the user if the chosen frame rate is within the capability of the

RTO according to eq. 3.


8.3 Digital inputs and outputs

8.3 Digital inputs and outputs

When the receiver system with sparsification is used in LPT experiments, four of

these systems will be used - one for each camera. Then synchronization is necessary.

As explained in section 6 the 16 digital inputs and outputs of the X5-TX are available

on an MDR36 connector of the Transceiver-Board and are unused up to now. One

of these inputs of every receiver system could be connected to an external device and

be used as the trigger signal for all systems to start and stop recording simultaneous.

This external device could be a simple button or another computer. If a computer is

used, more digital outputs can be used and information of all four receiver systems

can be monitored.

8.4 Cameras

At present the RTO outputs image data without saving them in the dedicated RAM

of the camera. Due to this fact and the limited transfer rate of the RTO the maximum

frame rates which can be achieved when the RTO is in use, are much lower than the

maximum frame rates of the camera itself, as explained in section 2.4. That means,

high speed movies taken at the limit of the cameras capability have to be stored

in the RAM and can only be downloaded by Ethernet. The camera manufacturer

confirmed to deliver firmware updates in the future that will allow the RTO to send

images from the RAM. Then the user can chose to use the RTO with:

Live images: The frame rate is limited by the transfer rate of the RTO,

but therefore experiment duration is only limited to the size

of the hard drive.

Images from RAM: The possible frame rates are much higher, but the experiment

duration is limited to the size of the RAM of the camera.

However, the downloading of the recorded images is much

faster than through ethernet.

In a cooperation with the camera manufacturer the sparsification could even be im-

plemented in the camera. Then the RTO could output sparsified data.


LIST OF TABLES

List of Tables

2.1 Transfer rates and channel numbers [4] . . . . . . . . . . . . . . . . . 6

2.2 Extract of the 8b/10b look-up-table [6] . . . . . . . . . . . . . . . . . 7

2.3 Extract of K-Characters [6] . . . . . . . . . . . . . . . . . . . . . . . 8

2.4 Transfer protocol for 8 bit pixels [5] . . . . . . . . . . . . . . . . . . . 9

4.1 Attributes of the GTP Dual [6] . . . . . . . . . . . . . . . . . . . . . 18

4.2 Configuration ports of the GTP Dual [6] . . . . . . . . . . . . . . . . 18

5.1 Inputs and outputs of rocketIO wrapper tile [6] . . . . . . . . . . . . 21

5.2 Inputs and outputs of data receiver . . . . . . . . . . . . . . . . . . . 23

5.3 Outputs of data sender . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.4 Inputs and outputs of rio intf . . . . . . . . . . . . . . . . . . . . . . 25

5.5 Inputs and outputs of rio clocks . . . . . . . . . . . . . . . . . . . . . 27

5.6 Inputs and outputs of rio chan intf . . . . . . . . . . . . . . . . . . . 28


LIST OF FIGURES

List of Figures

1.1 LPT on the Lagrangian Exploration Module [1] . . . . . . . . . . . . 1

1.2 Measurement volume . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.3 Decrease of particle density in the measurement volume . . . . . . . . 3

2.1 Camera block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.2 Real Time Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.3 Readout sequence for 8 channels [4] . . . . . . . . . . . . . . . . . . . 6

2.4 Readout sequence for 6 channels [4] . . . . . . . . . . . . . . . . . . . 6

2.5 Transmission of packets . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.6 Data packet [5] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.7 Optical transmitter ZL60101 TX [7] . . . . . . . . . . . . . . . . . . . 10

2.8 Fiber cable with MTP/MPO connector . . . . . . . . . . . . . . . . . 10

3.1 X5-TX with adapter card . . . . . . . . . . . . . . . . . . . . . . . . 14

3.2 Framework Logic block diagram . . . . . . . . . . . . . . . . . . . . . 15

3.3 Framework Logic block diagram with RocketIO . . . . . . . . . . . . 17

5.1 RocketIO interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.2 RocketIO channel interface . . . . . . . . . . . . . . . . . . . . . . . . 26

6.1 Transceiver-Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.2 X5-TX and Transceiver-Board in the host computer . . . . . . . . . . 31

7.1 Raw image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.2 Corrected image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32


REFERENCES

References

[1] The Lagrangian Exploration Module

Generation of homogeneous and isotropic turbulence with little mean flow for

Lagrangian experiments

Diploma Thesis

Robert Zimmermann

November 04, 2008

[2] A quantitative study of three-dimensional Lagrangian particle tracking algorithms

N.T. Ouellette, H. Xu, E. Bodenschatz

Experiments in Fluids, 40(2):301-313, 2006

[3] Real-time image compression for high-speed particle tracking

K.Y. Chan, D. Stich, G.A. Voth

Review of scientific instruments 78, 023704, 2007

[4] Confidential information from Vision Research

[5] Phantom Real-Time Image Output Interface

Vision Research

R. Corlan

Rev 1.0 July 01, 2005

www.visionresearch.com

[6] Virtex-5 FPGA RocketIO GTP Transceiver User Guide

Xilinx

UG196 (v2.0) June 10, 2009

www.xilinx.com

[7] ZL60101 TX / ZL60102 RX Data Sheet

12 x 2.7 Gbps Parallel Fiber Optic Link

Transmitter and Receiver

Data Sheet

Zarlink

Issue 1.1 January, 2003

www.zarlink.com


REFERENCES

[8] Phantom V7.3 Data Sheet

Vision Research

November 11, 2007

www.visionresearch.com

[9] X5 FrameWork Logic User Guide

Innovative Integration

Rev 1.0 December 19, 2007

www.innovative-dsp.com

[10] X5-TX User’s Manual

Innovative Integration

Rev 1.1 April 22, 2009

www.innovative-dsp.com


Appendix J

Schematic of the Transceiver-Board

11

22

33

44

DD

CC

BB

AA

Title

Num

ber

Revision

Size A4

Date:

16.07.2009

Sheet of

File:

E:\Projekte\..\Transceiver.p

rjDrawn By:

MPa

Bun

sens

tr.Göttin

gen

Tel.: +49

-551

Tran

sceiver

V1.0

a

13

TOP

DOUT8

-B2

DOUT8a

B3

DOUT9a

B5

DOUT9

-B6

DOUT7

-C3

DOUT7a

C4

DOUT1

0aC6

DOUT1

0-C7

DOUT6

-D4

DOUT6a

D5

DOUT1

1aD7

DOUT1

1-D8

DOUT5

-E2

DOUT5a

E3

DOUT2

-E5

DOUT2a

E6

DOUT4

-F3

DOUT4a

F4

DOUT1

-F6

DOUT1a

F7

DOUT3

-G4

DOUT3a

G5

DOUT0

-G7

DOUT0a

G8

RX_S

DH7

RX_E

NJ9

SQ_E

NK10

U1A

ZL60102

GND

1

TXa

2TX

-3

GND

4

RX-

5RXa

6

GND

7X2

MOLE

X 67491-0020

GND

1

TXa

2TX

-3

GND

4

RX-

5RXa

6

GND

7X3

MOLE

X 67491-0020

GND

1

TXa

2TX

-3

GND

4

RX-

5RXa

6

GND

7X4

MOLE

X 67491-0020

GND

1

TXa

2TX

-3

GND

4

RX-

5RXa

6

GND

7X5

MOLE

X 67491-0020

C1

100nF

C2

100nF

C3

100nF

C4

100nF

C5

100nF

C6

100nF

C7

100nF

C8

100nF

C9

100nF

C10

100nF

C11

100nF

C12

100nF

C13

100nF

C14

100nF

C15

100nF

C16

100nF

R3

100R

R4

100R

R5

100R

R6

100R

GND

GND

GND

GND

12

34

56

78

JP7B

Jumper 8

Pin

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68

J2 MDR68 10268-55H

3VC

GND

Va

12

34

56

78

JP6B

Jumper 8

Pin

GND Va

12

34

JP5B

Jumper 4

Pin

12

34

JP3B

Jumper 4

Pin

12

34

JP4B

Jumper 4

Pin

R8

480R

R7

480R

KA

D1

LED Rot

KA

D2

LED Grün

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

DIO

18-IN

T

DIO

18-IN

T

DIO

19-IN

T

DIO

19-IN

T

DIO

38-IN

T

DIO

38-IN

T

DIO

39-IN

T

DIO

39-IN

T

DIO

40-IN

T

DIO

40-IN

T

Power und ext. C

onnector

01_P

ower.SCH

DOUT0

_NDOUT0

_P

DOUT1

_NDOUT1

_P

DOUT2

_NDOUT2

_P

DOUT3

_NDOUT3

_P

DOUT8

_NDOUT8

_P

DOUT9

_NDOUT9

_P

DOUT1

0_N

DOUT1

0_P

DOUT1

1_N

DOUT1

1_P

Differential P

airs

02_D

iffPairR

ules.SCH

DIO

_0_1_P

DIO

_0_1_N

DIO

_2_3_N

DIO

_2_3_P

DIO

_4_5_P

DIO

_4_5_N

DIO

_6_7_N

DIO

_6_7_P

DIO

_8_9_P

DIO

_8_9_N

DIO

_10_11_N

DIO

_10_11_P

DIO

_12_13_P

DIO

_12_13_N

DIO

_14_15_N

DIO

_14_15_P

DIO

_16_17_P

DIO

_16_17_N

DIO

_20_21_N

DIO

_20_21_P

DIO

_22_23_P

DIO

_22_23_N

DIO

_24_25_N

DIO

_24_25_P

DIO

_26_27_P

DIO

_26_27_N

DIO

_28_29_N

DIO

_28_29_P

DIO

_30_31_P

DIO

_30_31_N

DIO

_32_33_N

DIO

_32_33_P

DIO

_34_35_P

DIO

_34_35_N

DIO

_36_37_N

DIO

_36_37_P

DIO

42DIO

43

DIO

_CLK

_NDIO

_CLK

_P

DIO

41

DIO

19-EXT

DIO

18-EXT

DIO

38-EXT

DIO

39-EXT

DIO

40-EXT

DOUT8

x_N

DOUT8

x_P

DOUT9

x_N

DOUT9

x_P

DOUT1

0x_N

DOUT1

0x_P

DOUT1

1x_N

DOUT1

1x_P

DOUT0

x_N

DOUT0

x_P

DOUT1

x_N

DOUT1

x_P

DOUT2

x_N

DOUT2

x_P

DOUT3

x_N

DOUT3

x_P

PIC101

PIC102

COC1

PIC201

PIC202

COC2 PI

C301

PIC302

COC3

PIC401

PIC402

COC4

PIC501

PIC502

COC5

PIC601

PIC602

COC6

PIC701

PIC702

COC7

PIC801

PIC802

COC8

PIC901

PIC902

COC9

PIC1001

PIC1002

COC10

PIC1101

PIC1102

COC11

PIC1201

PIC1202

COC12

PIC1301

PIC1302

COC13

PIC1401

PIC1402

COC14

PIC1501

PIC1502

COC15

PIC1601

PIC1602

COC16

PID10A

PID10KCOD

1

PID20A

PID20KCOD

2

PIJ201

PIJ202

PIJ203

PIJ204

PIJ205

PIJ206

PIJ207

PIJ208

PIJ209

PIJ2010

PIJ2011

PIJ2012

PIJ2013

PIJ2014

PIJ2015

PIJ2016

PIJ2017

PIJ2018

PIJ2019

PIJ2020

PIJ2021

PIJ2022

PIJ2023

PIJ2024

PIJ2025

PIJ2026

PIJ2027

PIJ2028

PIJ2029

PIJ2030

PIJ2031

PIJ2032

PIJ2033

PIJ2034

PIJ2035

PIJ2036

PIJ2037

PIJ2038

PIJ2039

PIJ2040

PIJ2041

PIJ2042

PIJ2043

PIJ2044

PIJ2045

PIJ2046

PIJ2047

PIJ2048

PIJ2049

PIJ2050

PIJ2051

PIJ2052

PIJ2053

PIJ2054

PIJ2055

PIJ2056

PIJ2057

PIJ2058

PIJ2059

PIJ2060

PIJ2061

PIJ2062

PIJ2063

PIJ2064

PIJ2065

PIJ2066

PIJ2067

PIJ2068

COJ2

PIJP301

PIJP302

PIJP303

PIJP304

COJP3B

PIJP401

PIJP402

PIJP403

PIJP404

COJP4B

PIJP501

PIJP502

PIJP503

PIJP504CO

JP5B

PIJP601

PIJP602

PIJP603

PIJP604

PIJP605

PIJP606

PIJP607

PIJP608CO

JP6B

PIJP701

PIJP702

PIJP703

PIJP704

PIJP705

PIJP706

PIJP707

PIJP708

COJP7B

PIR301

PIR302COR3

PIR401

PIR402COR4

PIR501

PIR502COR

5

PIR601

PIR602COR

6

PIR701

PIR702COR

7

PIR801

PIR802COR

8

PIU10B2

PIU10B3

PIU10B5

PIU10B6

PIU10C3

PIU10C4

PIU10C6

PIU10C7

PIU10D4

PIU10D5

PIU10D7

PIU10D8

PIU10E2

PIU10E3

PIU10E5

PIU10E6

PIU10F3

PIU10F4

PIU10F6

PIU10F7

PIU10G4

PIU10G5

PIU10G7

PIU10G8

PIU10H7

PIU10J9

PIU10K10

COU1A

PIX201

PIX202

PIX203

PIX204

PIX205

PIX206

PIX207

COX2

PIX301

PIX302

PIX303

PIX304

PIX305

PIX306

PIX307

COX3

PIX401

PIX402

PIX403

PIX404

PIX405

PIX406

PIX407

COX4

PIX501

PIX502

PIX503

PIX504

PIX505

PIX506

PIX507COX

5

PIJP604

NLDIO180EXT

PIJ2014

PIJP606

NLDIO180INT

PIJP704

NLDIO190EXT

PIJ2048

PIJP706

NLDIO190INT

PIJP504

NLDIO380EXT

PIJ2029

PIJP502

NLDIO380INT

PIJP302

NLDIO390EXT

PIJ2063

PIJP304

NLDIO390INT

PIJP402

NLDIO400EXT

PIJ2031

PIJP404

NLDIO400INT

PIJ2065

NLDIO41

PIJ2032

NLDIO42

PIJ2066

NLDIO43

PIJ2035

NLDIO00010N

PIJ201

NLDIO00010P

PIJ2036

NLDIO02030N

PIJ202

NLDIO02030P

PIJ2038

NLDIO04050N

PIJ204

NLDIO04050P

PIJ2039

NLDIO06070N

PIJ205

NLDIO06070P

PIJ2041

NLDIO08090N

PIJ207

NLDIO08090P

PIJ2042

NLDIO0100110N

PIJ208

NLDIO0100110P

PIJ2044

NLDIO0120130N

PIJ2010

NLDIO0120130P

PIJ2045

NLDIO0140150N

PIJ2011

NLDIO0140150P

PIJ2047

NLDIO0160170N

PIJ2013

NLDIO0160170P

PIJ2050

NLDIO0200210N

PIJ2016

NLDIO0200210P

PIJ2051

NLDIO0220230N

PIJ2017

NLDIO0220230P

PIJ2053

NLDIO0240250N

PIJ2019

NLDIO0240250P

PIJ2054

NLDIO0260270N

PIJ2020

NLDIO0260270P

PIJ2056

NLDIO0280290N

PIJ2022

NLDIO0280290P

PIJ2057

NLDIO0300310N

PIJ2023

NLDIO0300310P

PIJ2059

NLDIO0320330N

PIJ2025

NLDIO0320330P

PIJ2060

NLDIO0340350N

PIJ2026

NLDIO0340350P

PIJ2062

NLDIO0360370N

PIJ2028

NLDIO0360370P

PIJ2068

NLDIO0CLK0N

PIJ2034

NLDIO0CLK0P

PIC202

PIU10G7

NLDOUT00N

PIC102

PIU10G8

NLDOUT00P

PIC201

PIX205

NLDOUT0x0N

PIC101

PIX206

NLDOUT0x0P

PIC302

PIU10F6

NLDOUT10N

PIC402

PIU10F7

NLDOUT10P

PIC301

PIX203

NLDOUT1x0N

PIC401

PIX202

NLDOUT1x0P

PIC502

PIU10E5

NLDOUT20N

PIC602

PIU10E6

NLDOUT20P

PIC501

PIX305NLDOUT2x0N

PIC601

PIX306NLDOUT2x0P

PIC702

PIU10G4

NLDOUT30N

PIC802

PIU10G5

NLDOUT30P

PIC701

PIX303NLDOUT3x0N

PIC801

PIX302NLDOUT3x0P

PIC902

PIU10B2

NLDOUT80N

PIC1002

PIU10B3

NLDOUT80P

PIC901

PIX405

NLDOUT8x0N

PIC1001

PIX406

NLDOUT8x0P

PIC1102

PIU10B6

NLDOUT90N

PIC1202

PIU10B5

NLDOUT90P

PIC1101

PIX403

NLDOUT9x0N

PIC1201

PIX402

NLDOUT9x0P

PIC1302

PIU10C7

NLDOUT100N

PIC1402

PIU10C6

NLDOUT100P

PIC1301

PIX505

NLDOUT10x0N

PIC1401

PIX506

NLDOUT10x0P

PIC1502

PIU10D8NLDOUT110N

PIC1602

PIU10D7NLDOUT110P

PIC1501

PIX503

NLDOUT11x0N

PIC1601

PIX502

NLDOUT11x0P

PID10K

PID20K

PIJ203

PIJ206

PIJ209

PIJ2012

PIJ2015

PIJ2018

PIJ2021

PIJ2024

PIJ2027

PIJ2030

PIJ2033

PIJ2037

PIJ2040

PIJ2043

PIJ2046

PIJ2049

PIJ2052

PIJ2055

PIJ2058

PIJ2061

PIJ2064

PIJ2067

PIJP602

PIJP702

PIX201

PIX204

PIX207

PIX301

PIX304

PIX307

PIX401

PIX404

PIX407

PIX501

PIX504

PIX507

PID10A

PIR701

PID20A

PIR801

PIJP301

PIJP303

PIR702

PIJP401

PIJP403

PIR802

PIJP501

PIJP503

PIU10H7

PIJP601

PIJP603

PIJP605

PIJP607

PIU10J9

PIJP701

PIJP703

PIJP705

PIJP707

PIU10K10

PIR301

PIU10F4

PIR302

PIU10F3

PIR401

PIU10E3

PIR402

PIU10E2

PIR501

PIU10D4

PIR502

PIU10D5

PIR601

PIU10C3

PIR602

PIU10C4

PIJP608

PIJP708

11

22

33

44

DD

CC

BB

AA

Title

Num

ber

Revision

Size A4

Date:

16.07.2009

Sheet of

File:

E:\Projekte\..\01_Pow

er.SCH

Drawn By:

MPa

Bun

sens

tr.Göttin

gen

Tel.: +49

-551

Tran

sceiver

V1.0

a

23

Power und ext. C

onnector

VEE

A2

VEE

A3

VEE

A5

VEE

A6

VEE

B1

VEE

B4

VEE

B7

VEE

B8

VEE

B9

VEE

C1

VEE

C2

VEE

C5

VEE

C8

VEE

C9

VEE

D1

VEE

D2

VEE

D3

VEE

D6

VEE

D9

VEE

E1

VEE

E4

VEE

E7

VEE

E8

VEE

E9

VEE

F1VEE

F2VEE

F5VEE

F8VEE

F9VEE

G1

VEE

G2

VEE

G3

VEE

G6

VEE

G9

VCC

H3

VCC

H4

VCC

H5

VCC

H6

VCC

J3VCC

J4VCC

J5VCC

J6

U1B

ZL60102

GND

GND

Va

C101

100nF

C102

100nF

C103

100nF

C104

100nF

C105

100nF

C106

100nF

Va

GND

1 2 3 4

X1A

Molex 15-24-4441

GND

R1

100R

R2

1k

C21

100nF

C22

100nF

GND

GND

GND

GND

Va

GND 1

Vout

2Vin

3

U2B

LD1117S3

3

a5V

GND

C17

100nF

GND

GND

a3V3

a3V3

1 2aC19

10uF/16V

1 2aC20

10uF/16V

L1 1uH

L2 6.8nH

1 2aC18

10uF/16V

123456789101112131415161718

192021222324252627282930313233343536

J3 MDR68 10236-55H

3VC

GND

DIO

_CLK

_NDIO

_CLK

_P

GND

GND

GND

GND

GND

DIO

18-EXT

DIO

19-EXT

DIO

_0_1_P

DIO

_0_1_N

DIO

_2_3_N

DIO

_2_3_P

DIO

_4_5_P

DIO

_4_5_N

DIO

_6_7_N

DIO

_6_7_P

DIO

_8_9_P

DIO

_8_9_N

DIO

_10_11_N

DIO

_10_11_P

DIO

_12_13_P

DIO

_12_13_N

GND

GND

GND

GND

GND

DIO

38-EXT

DIO

39-EXT

DIO

40-EXT

DIO

41

GND

DIO

42DIO

43

PIC1701PIC1702COC17

PIC1801 PIC1802

COC18

PIC1901 PIC1902COC19

PIC2001 PIC2002COC20

PIC2101PIC2102COC21

PIC2201PIC2202COC22

PIC10101PIC10102COC101






PIJ301

PIJ302

PIJ303

PIJ304

PIJ305

PIJ306

PIJ307

PIJ308

PIJ309

PIJ3010

PIJ3011

PIJ3012

PIJ3013

PIJ3014

PIJ3015

PIJ3016

PIJ3017

PIJ3018

PIJ3019

PIJ3020

PIJ3021

PIJ3022

PIJ3023

PIJ3024

PIJ3025

PIJ3026

PIJ3027

PIJ3028

PIJ3029

PIJ3030

PIJ3031

PIJ3032

PIJ3033

PIJ3034

PIJ3035

PIJ3036

COJ3

PIL101

PIL102

COL1

PIL201

PIL202

COL2

PIR101

PIR102COR1

PIR201

PIR202COR

2

PIU10A2

PIU10A3

PIU10A5

PIU10A6

PIU10B1

PIU10B4

PIU10B7

PIU10B8

PIU10B9

PIU10C1

PIU10C2

PIU10C5

PIU10C8

PIU10C9

PIU10D1

PIU10D2

PIU10D3

PIU10D6

PIU10D9

PIU10E1

PIU10E4

PIU10E7

PIU10E8

PIU10E9

PIU10F1

PIU10F2

PIU10F5

PIU10F8

PIU10F9

PIU10G1

PIU10G2

PIU10G3

PIU10G6

PIU10G9

PIU10H3

PIU10H4

PIU10H5

PIU10H6

PIU10J3

PIU10J4

PIU10J5

PIU10J6

COU1B

PIU201PIU202

PIU203CO

U2B

PIX101

PIX102

PIX103

PIX104

COX1A

PIC1801

PIC1901

PIL101

PIR101

PIU202

PIC1702

PIU203

PIX104

NL05V

PIJ308

NLDIO180EXT

PIJ3026

NLDIO190EXT

PIJ306

NLDIO380EXT

PIJ3024

NLDIO390EXT

PIJ305

NLDIO400EXT

PIJ3023

NLDIO41

PIJ303

NLDIO42

PIJ3021

NLDIO43

PIJ3036

NLDIO00010N

PIJ3018

NLDIO00010P

PIJ3035

NLDIO02030N

PIJ3017

NLDIO02030P

PIJ3033

NLDIO04050N

PIJ3015

NLDIO04050P

PIJ3032

NLDIO06070N

PIJ3014

NLDIO06070P

PIJ3030

NLDIO08090N

PIJ3012

NLDIO08090P

PIJ3029

NLDIO0100110N

PIJ3011

NLDIO0100110P

PIJ3027

NLDIO0120130N

PIJ309

NLDIO0120130P

PIJ3019

NLDIO0CLK0N

PIJ301

NLDIO0CLK0P

PIC1701PIC1802

PIC1902PIC2002

PIC2101PIC2201

PIC10101PIC10201

PIC10301PIC10401

PIC10501PIC10601

PIJ302

PIJ304

PIJ307

PIJ3010

PIJ3013

PIJ3016

PIJ3020

PIJ3022

PIJ3025

PIJ3028

PIJ3031

PIJ3034

PIU10A2

PIU10A3

PIU10A5

PIU10A6

PIU10B1

PIU10B4

PIU10B7

PIU10B8

PIU10B9

PIU10C1

PIU10C2

PIU10C5

PIU10C8

PIU10C9

PIU10D1

PIU10D2

PIU10D3

PIU10D6

PIU10D9

PIU10E1

PIU10E4

PIU10E7

PIU10E8

PIU10E9

PIU10F1

PIU10F2

PIU10F5

PIU10F8

PIU10F9

PIU10G1

PIU10G2

PIU10G3

PIU10G6

PIU10G9

PIU201

PIX102

PIX103

PIC2001PIC2102

PIL102

PIL201

PIR102

PIR201

PIX101

PIC2202

PIC10102PIC10202

PIC10302PIC10402

PIC10502PIC10602

PIL202

PIR202

PIU10H3

PIU10H4

PIU10H5

PIU10H6

PIU10J3

PIU10J4

PIU10J5

PIU10J6

11

22

33

44

DD

CC

BB

AA

Title

Num

ber

Revision

Size A4

Date:

16.07.2009

Sheet of

File:

E:\Projekte\..\02_D

iffPairR

ules.SCH

Drawn By:

MPa

Bun

sens

tr.Göttin

gen

Tel.: +49

-551

Tran

sceiver

V1.0

a

33

Differntial P

air R

ules

iNet Class

DIFF_DOUT

iNet Class

DIFF_DOUT

iNet Class

DIFF_DOUT

iNet Class

DIFF_DOUT

DOUT0

_N

DOUT0

_P

DOUT1

_N

DOUT1

_P

DOUT2

_N

DOUT2

_P

DOUT3

_N

DOUT3

_P

DOUT8

_N

DOUT8

_P

DOUT9

_N

DOUT9

_P

DOUT1

0_N

DOUT1

0_P

DOUT1

1_N

DOUT1

1_P

iNet Class

DIFF_DOUT

iNet Class

DIFF_DOUT

iNet Class

DIFF_DOUT

iNet Class

DIFF_DOUT

iNet Class

DIFF_DOUT

iNet Class

DIFF_DOUT

iNet Class

DIFF_DOUT

iNet Class

DIFF_DOUT

iNet Class

DIFF_DOUT

iNet Class

DIFF_DOUT

iNet Class

DIFF_DOUT

iNet Class

DIFF_DOUT

iNet Class

DIFF_DIO

iNet Class

DIFF_DIO

iNet Class

DIFF_DIO

iNet Class

DIFF_DIO

iNet Class

DIFF_DIO

iNet Class

DIFF_DIO

iNet Class

DIFF_DIO

DIO

_0_1_P

DIO

_0_1_N

DIO

_2_3_N

DIO

_2_3_P

DIO

_4_5_P

DIO

_4_5_N

DIO

_6_7_N

DIO

_6_7_P

DIO

_8_9_P

DIO

_8_9_N

DIO

_10_11_N

DIO

_10_11_P

DIO

_12_13_P

DIO

_12_13_N

DIO

_CLK

_NDIO

_CLK

_PiNet Class

DIFF_DIO

iNet Class

DIFF_DIO

iNet Class

DIFF_DIO

iNet Class

DIFF_DIO

iNet Class

DIFF_DIO

iNet Class

DIFF_DIO

iNet Class

DIFF_DIO

iNet Class

DIFF_DIO

iNet Class

DIFF_DIO

DOUT0

_N

DOUT0

_P

DOUT1

_N

DOUT1

_P

DOUT2

_N

DOUT2

_P

DOUT3

_N

DOUT3

_P

DOUT8

_N

DOUT8

_P

DOUT9

_N

DOUT9

_P

DOUT1

0_N

DOUT1

0_P

DOUT1

1_N

DOUT1

1_P

iNet Class

DIFF_DOUTX

iNet Class

DIFF_DOUTX

iNet Class

DIFF_DOUTX

iNet Class

DIFF_DOUTX

iNet Class

DIFF_DOUTX

iNet Class

DIFF_DOUTX

iNet Class

DIFF_DOUTX

iNet Class

DIFF_DOUTX

iNet Class

DIFF_DOUTX

iNet Class

DIFF_DOUTX

iNet Class

DIFF_DOUTX

iNet Class

DIFF_DOUTX

iNet Class

DIFF_DOUTX

iNet Class

DIFF_DOUTX

iNet Class

DIFF_DOUTX

iNet Class

DIFF_DOUTX

NLDIO00010N

NLDIO00010P

NLDIO02030N

NLDIO02030P

NLDIO04050N

NLDIO04050P

NLDIO06070N

NLDIO06070P

NLDIO08090N

NLDIO08090P

NLDIO0100110N

NLDIO0100110P

NLDIO0120130N

NLDIO0120130P

NLDIO0CLK0N

NLDIO0CLK0P

NLDOUT00N

NLDOUT00P

NLDOUT10N

NLDOUT10P

NLDOUT20N

NLDOUT20P

NLDOUT30N

NLDOUT30P

NLDOUT80N

NLDOUT80P

NLDOUT90N

NLDOUT90P

NLDOUT100N

NLDOUT100P

NLDOUT110N

NLDOUT110P

PAC101

PAC102COC1 PAC2

01PAC2

02COC2 PAC

301PAC

302 COC3 PAC

401PAC

402COC4PAC

501PAC

502 COC5PAC6

01PAC6

02COC6 PAC7

01PAC7

02 COC7 PAC8

01PAC8

02COC8PAC

901PAC

902 COC9PAC10

01PAC10

02COC10 PAC1101

PAC1102 COC11 PAC1201

PAC1202

COC12 PAC1301

PAC1302

COC13PAC1401

PAC1402 COC14

PAC1501

PAC1502 COC15

PAC1601

PAC1602COC16

PAC1801

PAC1802COC

18

PAC2102

PAC2101

COC21PAC22

02

PAC2201COC22

PAD10A

PAD10K

COD1

PAD20A

PAD20K

COD2

PAJ200

PAJ2068

PAJ2067

PAJ2066

PAJ2065

PAJ2064

PAJ2063

PAJ2062

PAJ2061

PAJ2060

PAJ2059

PAJ2058

PAJ2057

PAJ2056

PAJ2055

PAJ2054

PAJ2053

PAJ2052

PAJ2051

PAJ2050

PAJ2049

PAJ2048

PAJ2047

PAJ2046

PAJ2045

PAJ2044

PAJ2043

PAJ2042

PAJ2041

PAJ2040

PAJ2039

PAJ2038

PAJ2037

PAJ2036

PAJ2035

PAJ2034

PAJ2033

PAJ2032

PAJ2031

PAJ2030

PAJ2029

PAJ2028

PAJ2027

PAJ2026

PAJ2025

PAJ2024

PAJ2023

PAJ2022

PAJ2021

PAJ2020

PAJ2019

PAJ2018

PAJ2017

PAJ2016

PAJ2015

PAJ2014

PAJ2013

PAJ2012

PAJ2011

PAJ2010

PAJ209

PAJ208

PAJ207

PAJ206

PAJ205

PAJ204

PAJ203

PAJ202

PAJ201

COJ2

PAJ300

PAJ3018

PAJ3017

PAJ3016

PAJ3015

PAJ3014

PAJ3013

PAJ3012

PAJ3011

PAJ3010

PAJ309

PAJ308

PAJ307

PAJ306

PAJ305

PAJ304

PAJ303

PAJ302

PAJ301

PAJ3019

PAJ3020

PAJ3021

PAJ3022

PAJ3023

PAJ3024

PAJ3025

PAJ3026

PAJ3027

PAJ3028

PAJ3029

PAJ3030

PAJ3031

PAJ3032

PAJ3033

PAJ3034

PAJ3036

PAJ3035

COJ3

PAJP304

PAJP303

PAJP302

PAJP301COJP3

PAJP404

PAJP403

PAJP402

PAJP401CO

JP4

PAJP501

PAJP502

PAJP503

PAJP504COJP5

PAJP605

PAJP608

PAJP607

PAJP606

PAJP604

PAJP603

PAJP602

PAJP601

COJP6

PAJP705

PAJP708

PAJP707

PAJP706

PAJP704

PAJP703

PAJP702

PAJP701

COJP7

PAL201

PAL202 COL2

PAR202

PAR201COR2

PAU100

PAU10A1PAU10

A2PAU10

A3PAU10

A4PAU10

A5PAU10A6

PAU10A7

PAU10A8

PAU10A9

PAU10A10

PAU10B1PAU10

B2PAU10

B3PAU10

B4PAU10

B5PAU10B6

PAU10B7

PAU10B8

PAU10B9

PAU10B10

PAU10C1PAU10

C2PAU10

C3PAU10

C4PAU10

C5PAU10C6

PAU10C7

PAU10C8

PAU10C9

PAU10C10

PAU10D1PAU10

D2PAU10

D3PAU10

D4PAU10

D5PAU10D6

PAU10D7

PAU10D8

PAU10D9

PAU10D10

PAU10E1PAU10

E2PAU10

E3PAU10

E4PAU10

E5PAU10E6

PAU10E7

PAU10E8

PAU10E9

PAU10E10

PAU10F1PAU10

F2PAU10

F3PAU10

F4PAU10

F5PAU10F6

PAU10F7

PAU10F8

PAU10F9

PAU10F10

PAU10G1

PAU10G

2PAU

10G3

PAU10G

4PAU

10G5

PAU10G6

PAU10G

7PAU

10G8

PAU10G

9PAU1

0G10

PAU10H1PAU10

H2PAU10

H3PAU10

H4PAU10

H5PAU10H6

PAU10H7

PAU10H8

PAU10H9

PAU10H10

PAU10J1PAU10

J2PAU10

J3PAU10

J4PAU10

J5PAU10J6

PAU10J7

PAU10J8

PAU10J9

PAU10J10

PAU10K1PAU10

K2PAU10

K3PAU10

K4PAU10

K5PAU10K6

PAU10K7

PAU10K8

PAU10K9

PAU10K10

COU1

PAX104

PAX103

PAX102

PAX101

PAX100

COX1

PAX200

PAX201

PAX202

PAX203

PAX204

PAX205

PAX206

PAX207

COX2PAX3

00

PAX301

PAX302

PAX303

PAX304

PAX305

PAX306

PAX307

COX3PAX4

00

PAX401

PAX402

PAX403

PAX404

PAX405

PAX406

PAX407

COX4

PAX500

PAX501

PAX502

PAX503

PAX504

PAX505

PAX506

PAX507

COX5

PAC1801

PAX104

PAJ308

PAJP604

PAJ2014

PAJP606

PAJ3026

PAJP704

PAJ2048

PAJP706

PAJ306

PAJP504

PAJ2029

PAJP502

PAJ3024

PAJP302

PAJ2063

PAJP304

PAJ305

PAJP402

PAJ2031

PAJP404

PAJ2065

PAJ3023

PAJ2032

PAJ303

PAJ2066

PAJ3021

PAJ2035

PAJ3036

PAJ201

PAJ3018

PAJ2036

PAJ3035

PAJ202

PAJ3017

PAJ2038

PAJ3033

PAJ204

PAJ3015

PAJ2039

PAJ3032

PAJ205

PAJ3014

PAJ2041

PAJ3030

PAJ207

PAJ3012

PAJ2042

PAJ3029

PAJ208

PAJ3011

PAJ2044

PAJ3027

PAJ2010

PAJ309

PAJ2045

PAJ2011

PAJ2047

PAJ2013

PAJ2050

PAJ2016PAJ20

51

PAJ2017

PAJ2053

PAJ2019PAJ2

054

PAJ2020

PAJ2056

PAJ2022PAJ20

57

PAJ2023

PAJ2059

PAJ2025PAJ20

60

PAJ2026

PAJ2062

PAJ2028

PAJ2068

PAJ3019

PAJ2034

PAJ301

PAC202

PAU10G

7

PAC102

PAU10G

8

PAC201

PAX205

PAC101

PAX206

PAC302

PAU10F6

PAC402

PAU10F7

PAC301

PAX203

PAC401

PAX202

PAC502

PAU10E5

PAC602

PAU10E6

PAC501

PAX305

PAC601

PAX306

PAC702

PAU10G

4

PAC802

PAU10G

5

PAC701

PAX303

PAC801

PAX302

PAC902

PAU10B2

PAC1002

PAU10B3

PAC901

PAX405

PAC1001

PAX406

PAC1102

PAU10B6

PAC1202

PAU10B5

PAC1101

PAX403

PAC1201

PAX402

PAC1302

PAU10C7

PAC1402

PAU10C6PAC13

01PAX505

PAC1401

PAX506

PAC1502

PAU10D8

PAC1602

PAU10D7

PAC1501

PAX503

PAC1601

PAX502

PAC1802

PAC2101PAC2201

PAD10K

PAD20K

PAJ203

PAJ206

PAJ209

PAJ2012

PAJ2015

PAJ2018

PAJ2021

PAJ2024

PAJ2027

PAJ2030

PAJ2033

PAJ2037

PAJ2040

PAJ2043

PAJ2046

PAJ2049

PAJ2052

PAJ2055

PAJ2058

PAJ2061

PAJ2064

PAJ2067

PAJ302

PAJ304

PAJ307

PAJ3010

PAJ3013

PAJ3016

PAJ3020

PAJ3022

PAJ3025

PAJ3028

PAJ3031

PAJ3034

PAJP602

PAJP702

PAU10A2

PAU10A3

PAU10A5

PAU10A6PAU10B1

PAU10B4

PAU10B7

PAU10B8

PAU10B9

PAU10C1PAU10

C2PAU10

C5PAU10

C8PAU10

C9

PAU10D1PAU10

D2PAU10

D3PAU10D6

PAU10D9

PAU10E1PAU10

E4PAU10

E7PAU10

E8PAU10

E9

PAU10F1PAU10

F2PAU10

F5PAU10

F8PAU10

F9PAU10

G1PAU

10G2

PAU10G

3PAU10

G6PAU

10G9

PAX102

PAX103

PAX201

PAX204

PAX207

PAX301

PAX304

PAX307

PAX401

PAX404

PAX407

PAX501

PAX504

PAX507

PAC2102

PAL201

PAR201

PAD10A

PAD20A

PAJP301

PAJP303

PAJP401

PAJP403

PAJP501

PAJP503

PAU10H7

PAJP601

PAJP603

PAJP605

PAJP607

PAU10J9

PAJP701

PAJP703

PAJP705

PAJP707

PAU10K10

PAU10F4

PAU10F3

PAU10E3

PAU10E2

PAU10D4

PAU10D5

PAU10C3

PAU10C4

PAC2202

PAJP608

PAJP708

PAL202

PAR202

PAU10H3

PAU10H4

PAU10H5

PAU10H6

PAU10J3

PAU10J4

PAU10J5

PAU10J6

PAC1702

PAC1701

COC17

PAC1901

PAC1902

COC19

PAC2001

PAC2002

COC20

PAC10102

PAC10101 COC101

PAC10202

PAC10201 COC102

PAC10302

PAC10301 COC103

PAC10402

PAC10401

COC104

PAC10502

PAC10501

COC105

PAC10602

PAC10601

COC106

PAL102

PAL101

COL1

PAR102

PAR101

COR1

PAR302PAR301 COR3PAR402

PAR401 COR4

PAR502

PAR501COR5

PAR602

PAR601COR6

PAR702

PAR701COR7

PAR802

PAR801COR8

PAU203

PAU202

PAU201

PAU204COU2 PAC19

01PAL101

PAR101

PAU202

PAC1702

PAU203

PAC1701

PAC1902

PAC2002

PAC10101

PAC10201

PAC10301

PAC10401

PAC10501

PAC10601

PAU201

PAC2001

PAL102

PAR102

PAR701

PAR801

PAR702

PAR802

PAR301 PAR302PAR401

PAR402

PAR501

PAR502

PAR601

PAR602

PAC10102

PAC10202

PAC10302

PAC10402

PAC10502

PAC10602

Appendix K

Mechanical drawing of the slot bracket

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master-thesis development of a receiver system for the rto€¦ · master-thesis development of a...

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