memory testing
DESCRIPTION
testing of memoryTRANSCRIPT
Testing Semiconductor Testing Semiconductor MemoriesMemories
Lab for Reliable Computing
Dept. Electrical Engineering
National Tsing Hua University
Cheng-Wen Wu 吳誠文
mbist1.10 Cheng-Wen Wu, NTHU 2
OutlineOutline Introduction RAM functional fault models and test
algorithms RAM fault-coverage analysis Cocktail-March for testing word-
oriented memories
Testing multi-port RAMs
Testing CAMs
Testing flash memories
mbist1.10 Cheng-Wen Wu, NTHU 3
IntroductionIntroduction Memory testing is a more and more important issue
RAMs are key components for electronic systems Memories represent about 30% of the semiconductor market Embedded memories are dominating the chip yield
Memory testing is more and more difficult Growing density, capacity, and speed Emerging new architectures and technologies Embedded memories: access, diagnostics & repair, heterogeneity,
custom design, power & noise, scheduling, compression, etc.
Cost drives the need for more efficient test methodologies IFA, fault modeling and simulation, test algorithm development
and evaluation, diagnostics, DFT, BIST, BIRA, BISR, etc. Test automation is required
Failure analysis, fault simulation, ATG, and diagnostics BIST/BIRA/BISR generation
mbist1.10 Cheng-Wen Wu, NTHU 4
Typical RAM Production FlowTypical RAM Production Flow
WaferWafer Full Probe Test
Marking
Final Test ShippingQA Sample TestVisual Inspection
Burn-In (BI)Post-BI Test
Laser Repair Packaging
Pre-BI Test
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Scope of RAM TestingScope of RAM Testing Parametric Test: DC & AC Reliability Screening
Long-cycle testing Burn-in: static & dynamic BI
Functional Test Device characterization
Failure analysis Fault modeling
Simple but effective (accurate & realistic?) Test algorithm generation
Small number of test patterns (data backgrounds) High fault coverage Short test time
mbist1.10 Cheng-Wen Wu, NTHU 6
RAM ModelsRAM Models Behavior Level
Verilog/VHDL
Function Level Verilog/VHDL/Block diagram Normally not synthesizable
Circuit Level Spice/Schematic
Layout Level GDS-II/Geometry
☞ Who should provide the model?
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Memory Function Model ExampleMemory Function Model Example
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RAM Fault Models (Static)RAM Fault Models (Static) Address-Decoder Fault (AF)
No cell accessed by certain address Multiple cells accessed by certain address Certain cell not accessed by any address Certain cell accessed by multiple addresses
Stuck-At Fault (SAF) Cell (line) SA0 or SA1
Transition Fault (TF) Cell fails to transit from 0 to 1 or 1 to 0
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RAM Fault Models (Static)RAM Fault Models (Static) Bridging Fault (BF)
Short between cells AND type or OR type
Stuck-Open Fault (SOF) Cell not accessible due to broken line
Neighborhood Pattern Sensitive Fault (NPSF) Active (Dynamic) NPSF Passive NPSF Static NPSF
NW BC E
S
mbist1.10 Cheng-Wen Wu, NTHU 10
RAM Fault Models (Static)RAM Fault Models (Static) Coupling Fault (CF)
State Coupling Fault (CFst) Coupled (victim) cell is forced to 0 or 1 if coupling
(aggressor) cell is in given state
Inversion Coupling Fault (CFin) Transition in coupling cell complements (inverts)
coupled cell
Idempotent Coupling Fault (CFid) Coupled cell is forced to 0 or 1 if coupling cell
transits from 0 to 1 or 1 to 0
mbist1.10 Cheng-Wen Wu, NTHU 11
RAM Fault Models (Dynamic)RAM Fault Models (Dynamic) Recovery Fault (RF)
Sense Amplifier Recovery Fault (SARF) Sense amp saturation after reading/writing long run
of 0 or 1 Write Recovery Fault (WRF)
Write followed by reading/writing at different location resulting in reading/writing at same location
Write-after-write recovery fault Read-after-write recovery fault
Results in functional faults---detected at high speed (e.g., GALROW/GALCOL)
Disturb Fault (DF) Victim cell forced to 0 or 1 if we read or write
aggressor cell (may be the same cell)
mbist1.10 Cheng-Wen Wu, NTHU 12
RAM Fault Models (Dynamic)RAM Fault Models (Dynamic) Data Retention Fault (DRF)
DRAM Refresh Fault
Refresh-Line Stuck-At Fault Leakage Fault
Sleeping Sickness---loose data in less than specified hold time (typically tens of ms)
SRAM Leakage Fault
Static Data Losses---defective pull-up Checkerboard pattern triggers max leakage BIST good for sync with refresh mechanism
mbist1.10 Cheng-Wen Wu, NTHU 13
Test Time Complexity Test Time Complexity (100MHz)(100MHz)
Size N 10N NlogN N1.5 N2
1M 0.01s 0.1s 0.2s 11s 3h
16M 0.16s 1.6s 3.9s 11m 33d
64M 0.66s 6.6s 17s 1.5h 1.43y
256M 2.62s 26s 1.23m 12h 23y
1G 10.5s 1.8m 5.3m 4d 366y
4G 42s 7m 22.4m 32d 57c
16G 2.8m 28m 1.6h 255d 915c
mbist1.10 Cheng-Wen Wu, NTHU 14
RAM Test AlgorithmRAM Test Algorithm A test algorithm (or simply test) is a finite
sequence of test elements A test element contains a number of memory
operations (access commands) Data pattern (background) specified for the Read
operation Address (sequence) specified for the Read and
Write operations
A march test algorithm is a finite sequence of march elements A march element is specified by an address order
and a number of Read/Write operations
mbist1.10 Cheng-Wen Wu, NTHU 15
Classical Test AlgorithmsClassical Test Algorithms Zero-One Algorithm [Breuer & Friedman 1976]
Also known as MSCAN
For SAF
Solid background (pattern)
Complexity is 4N
)}1();1();0();0({ rwrw
mbist1.10 Cheng-Wen Wu, NTHU 16
Classical Test AlgorithmsClassical Test Algorithms
Checkerboard Algorithm Zero-one algorithm with checkerboard pattern
Complexity is 4N
For SAF and DRF
1 0 10 1 01 0 1
mbist1.10 Cheng-Wen Wu, NTHU 17
Classical Test AlgorithmsClassical Test Algorithms
Galloping Pattern (GALPAT) Complexity is 4N**2---only for characterization All AFs,TFs, CFs, and SAFs are located
1. Write background 0;
2. For BC = 0 to N-1
{ Complement BC;
For OC = 0 to N-1, OC != BC;
{ Read BC; Read OC; }
Complement BC; }
3. Write background 1;
4. Repeat Step 2;
BC
mbist1.10 Cheng-Wen Wu, NTHU 18
Classical Test AlgorithmsClassical Test Algorithms Sliding (Galloping) Row/Column/Diagonal
Based on GALPAT, but instead of a bit, a complete row, column, or diagonal is shifted
Complexity is 4N**1.5
1
1
1
1
1
mbist1.10 Cheng-Wen Wu, NTHU 19
Classical Test AlgorithmsClassical Test Algorithms Butterfly Algorithm
Complexity is 5NlogN
1. Write background 0;
2. For BC = 0 to N-1
{ Complement BC; dist = 1;
While dist <= mdist /* mdist < 0.5 col/row length */
{ Read cell @ dist north from BC;
Read cell @ dist east from BC;
Read cell @ dist south from BC;
Read cell @ dist west from BC;
Read BC; dist *= 2; }
Complement BC; }
3. Write background 1; repeat Step 2;
6
1
9 4 5,10 2 7
3
8
mbist1.10 Cheng-Wen Wu, NTHU 20
Classical Test AlgorithmsClassical Test Algorithms Moving Inversion (MOVI) Algorithm [De Jonge &
Smeulders 1976]
For functional and AC parametric test Functional (13N): for AF, SAF, TF, and most CF
Parametric (12NlogN): for Read access time 2 successive Reads @ 2 different addresses with
different data for all 2-address sequences differing in 1 bit
Repeat T2~T5 for each address bit GALPAT---all 2-address sequences
)}0,0,1();1,1,0();0,0,1();1,1,0();0({ rwrrwrrwrrwrw
mbist1.10 Cheng-Wen Wu, NTHU 21
Classical Test AlgorithmsClassical Test Algorithms Surround Disturb Algorithm
Examine how the cells in a row are affected when complementary data are written into adjacent cells of neighboring rows
1. For each cell[p,q] /* row p and column q */ { Write 0 in cell[p,q-1]; Write 0 in cell[p,q]; Write 0 in cell[p,q+1]; Write 1 in cell[p-1,q]; Read 0 from cell[p,q+1]; Write 1 in cell[p+1,q]; Read 0 from cell[p,q-1]; Read 0 from cell[p,q]; }2. Repeat Step 1 with complementary data;
1
0 0 0
1
mbist1.10 Cheng-Wen Wu, NTHU 22
Classical Test AlgorithmsClassical Test Algorithms Zero-one and checkerboard algorithms do not
have sufficient coverage
Other algorithms are too time-consuming for large RAM Test time is the key factor of test cost Complexity ranges from N2 to NlogN
Need linear-time test algorithms with small constants March test algorithms
mbist1.10 Cheng-Wen Wu, NTHU 23
March TestsMarch Tests Zero-One (MSCAN)
Modified Algorithmic Test Sequence (MATS) [Nair, Thatte & Abraham 1979]
OR-type address decoder fault
AND-type address decoder fault
MATS+ [Abadir & Reghbati 1983] For both OR- & AND-type AFs and SAF
)}1();1();0();0({ rwrw
)}1();1,0();0({ rwrw
)}0();0,1();1({ rwrw
)}0,1();1,0();0({ wrwrw
mbist1.10 Cheng-Wen Wu, NTHU 24
March TestsMarch Tests Marching 1/0 [Breuer & Friedman 1976]
For AF, SAF, and TF
MATS++ [Goor 1991] Also for AF, SAF, and TF Complete and irredundant
)}1,1,0();0,0,1();1(
);0,0,1();1,1,0();0({
rwrrwrw
rwrrwrw
)}0,0,1();1,0();0({ rwrwrw
mbist1.10 Cheng-Wen Wu, NTHU 25
March TestsMarch Tests March X
For AF, SAF, TF, & CFin
March C [Marinescu 1982] For AF, SAF, TF, & all CFs---redundant
March C- [Goor 1991] Also for AF, SAF, TF, & all CFs---irredundant
)}0();0,1();1,0();0({ rwrwrw
)}0();0,1();1,0();0(
);0,1();1,0();0({
rwrwrr
wrwrw
)}0();0,1();1,0(
);0,1();1,0();0({
rwrwr
wrwrw
mbist1.10 Cheng-Wen Wu, NTHU 26
March TestsMarch Tests Limitations
Sequential faults in address decoders RF NPSF
(9N-2) for 2-CF [Marinescu 1982]
(2NlogN+11N) for 3-CF [Cockburn 1994]
Solutions Address sequence variation
Hopping Pseudorandom
mbist1.10 Cheng-Wen Wu, NTHU 27
Coverage of March TestsCoverage of March Tests
MATS++ March X March Y March C-SAF 1 1 1 1TF 1 1 1 1AF 1 1 1 1SOF 1 .002 1 .002CFin .75 1 1 1CFid .375 .5 .5 1CFst .5 .625 .625 1
☞ Extended March C- (11N) has a 100% coverage of SOF
mbist1.10 Cheng-Wen Wu, NTHU 28
Testing Word-Oriented RAMTesting Word-Oriented RAM
Background bit is replaced by background word MATS++:
Conventional method is to use logm+1 different backgrounds for m-bit words m=8: 00000000, 01010101, 00110011, and
00001111
Apply the test algorithm logm+1=4 times, so complexity is 4*6N/8=3N
)},,'();',();({ rawarawarawa
mbist1.10 Cheng-Wen Wu, NTHU 29
Cocktail-March AlgorithmsCocktail-March Algorithms
Motivation: Repeating the same algorithm for all logm+1
backgrounds has redundancy Different algorithm targets different faults
Approach: Use multiple backgrounds in a single algorithm run Merge and forge different algorithms and
backgrounds into a single algorithm
Good for word-oriented memories
mbist1.10 Cheng-Wen Wu, NTHU 30
March-CWMarch-CW Algorithm:
March C- for solid background (0000) Then a 5N March for each of other standard
backgrounds (0101, 0011):
Result: Complexity is (10+5logW)N, where W is word
length and N is word count Test time is reduced by 39% if W=4, as compared
with extended March C- Improvement increases as W increases
)},,',',({ rawarawawa
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Comparison (Full Coverage)Comparison (Full Coverage)
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Testing NPSFTesting NPSF NPSF test approaches
Tiling Multi-background march
Easy BIST implementation 5-cell neighborhood
WN
E
ES
WN
ES
B
B
B
N, E, W, SDeleted neighborhood cells: N, E, W, SBase cell: B
BNeighborhood cells: and
mbist1.10 Cheng-Wen Wu, NTHU 33
NPSF ModelsNPSF Models Static NPSF (SNPSF)
BC forced to a certain state due to a certain deleted neighborhood (DN) pattern
Passive NPSF (PNPSF) BC frozen due to a certain DN pattern
Active NPSF (ANPSF) BC content changes due to a change in DN pattern
Change: a transition in one DN cell, with other DN cells & BC containing a certain pattern
Assumptions: Single NPSF Address scramble table is available Memory is bit-oriented
Word-oriented memory is tested as multiple bit-oriented ones
mbist1.10 Cheng-Wen Wu, NTHU 34
Test StrategyTest Strategy Multi-Background March
To generate all neighborhood patterns
XXXX11 11
1 1
1
1
11
11 0 0 0 0
0
0
000
0
0
1
1 11
11
0 0
00
0 0
0 01 1
1 1
0 0
00
0 0
00X
0 0X
00X0 0 0
11
1 11 1
11 1
111
10
0
1
1
010
0
00
000
X
Solid BG
(FC < 30%)
Another BG
mbist1.10 Cheng-Wen Wu, NTHU 35
Testing PNPSFTesting PNPSF March 17N:
wa wb, ra, wa ra ( ); ( );
(ra) (rb, wa);(ra, wb);
wb wa, ra, wb
rb( , wa);
(rb, );( , );
0 0 0 0
1 1
1 1
1 1
0 0
0 0
1 1
0 0
0 0
1 1
1 1
(w0); (r0);(w1, r1, w0);Alg1:
(w1); (w0, r0, w1); (r1);Alg2:
(w0); (w1); (r1); Alg3:
Alg4: (w1); (w0); (r0);
(w0); (r1); Alg5: (w1);
Alg6: (r0); (w0); (w1);
March Elements NWBES
mbist1.10 Cheng-Wen Wu, NTHU 36
Data Background GenerationData Background Generation Data backgrounds
BG1: all zero BG2: Ar[0], LSB of row address BG3: Ar[1], second bit of row address BG4: Ar[0]Ar[1]
00011011
00011011
00011011
00011011 0 0 0 01 11 11 11 1
00 01 10 11 00 01 10 11
BG.1 BG.2 BG.3 BG.4
00 01 10 1100 01 10 110
00 0 0
0000
00
01000
0 0 1 11
000
0 0 0 0
1 11
11 0 10
00
00 1 1
0
0 00
10
01
11
mbist1.10 Cheng-Wen Wu, NTHU 37
Testing ANPSFTesting ANPSF
March 12N:
(ra)
(wa); (wb, ra, wa); (ra, wb);
(rb, wa);
(rb, wa, wb);
00 00
000
00 0 0 00
0 0 0
1 11 1 1 111 1
11111 1 1
000
1
0
111
01 11
0 00
1( ,w1) ; ( ,w0) ;(w0) ;
( ,w1,w0) ;
( ,w0,w1) ;
(w0) ;
(w1) ; r1
(r0)
(r1)
(r0)r0
r0
r1
mbist1.10 Cheng-Wen Wu, NTHU 38
Time ComplexityTime Complexity
12 N/BG X 8 BG = 96N
Detects all NPSFs
00011011
00011011
0000
00011011
00011011
00011011
00 01 10 1100 01 10 11 00 01 10 11
00 01 10 11 00 01 10 1100011011
00011011
00 01 10 11
00 01 10 1100
00 01 10 11
011011
0 0 00000
000
0
0 0 1010101
0 0 01 11
0 01
1000 0
00 0 1
11
0
01
1
01010
1
10
01 0
BG.8
BG.4BG.3BG.2BG.1
BG.5 BG.6 BG.7
11
10
00 10
10110
1011
0
11111
1
10
00 0
01
00
10 1
11
10
1
10
101
01
01
11
10
00
0
00
01
00
0 1 1 0
11
mbist1.10 Cheng-Wen Wu, NTHU 39
Multi-Port MemoriesMulti-Port Memories Popular architectures
k-port (k > 1) n-read-1-write FIFO
Storage
Address A
Data A
Control APort A
Address B
Data B
Control BPort B
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2-Port Topology2-Port Topology
WL
Interport BL short
Interport WL shortWL
WL
WL
WL
WL
WL
WL
BL BLBL BL
BL BL BL BL
A
B
A
B
A
A
A
A
B
B
B
A
B
B
B
A
1
2
3
mbist1.10 Cheng-Wen Wu, NTHU 41
Inter-Port Word-Line ShortInter-Port Word-Line Short
* Functional test complexity: O(N3)
Faulty
Cell 1
Fault-Free
Cell 2
Address 3
Address 2
Cell 3
Address 1 Cell 1Address 1
Port B
Port A
Cell 2Address 2
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Inter-Port Bit-Line ShortInter-Port Bit-Line Short
Port A
Fault-Free
Port BCell
Address Cell
Address
Faulty
Address Address
Cell Cell
Address
Address
Cell
Cell
* Functional test complexity: O(N2)
mbist1.10 Cheng-Wen Wu, NTHU 43
Address ScramblingAddress Scrambling
B - I/O select
Logical Addr
Physical Addr
A B C D
7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0
row column
D - bit position in a word
A - word line select
C - bit line select
bit1bit2bit3 bit0
03
Address A
Data word A
mbist1.10 Cheng-Wen Wu, NTHU 44
Reading Neighboring CellsReading Neighboring Cells
Read neighboring cells to detect inter-port faults: rN, rS, rE, and rW
0/1 1 1/0 0
1 1 1
0 0 0
E
N
W
S
B
0 0 0
0 1
1 1 1
0/1
mbist1.10 Cheng-Wen Wu, NTHU 45
TAGS-PSTAGS-PS
Single-portTest Algorithm
Multi-portAF Test
Single-portTest Algorithm
March Test
Section 1 Section 2 Section 3
Port 1
Port 2
Port m
Port 1
Port 2
Port m
(a)
(b)
Multi-port Inter-portTestAF Test
Inter-portMPF Test
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Dual-Port RAM TestDual-Port RAM Test
-----
--- ---
(b)
--- - -- --
(a)
- --
1r 0w1rw
0
0w
r
r0
01r w 1r 0ww r 010 0
0r
01r r 1w 1
1
w w
0r 1w 1r 0w1
r 0
1
r
w 0
r
N1r S
w r 0
r
r
1
0
w
r
1r 0
Sr 1Nr 0
Sr 0Nr 1w 0r 1w 1
N
Section 1
r 0
w
0
0
S
- - - -r
0
1
r
Section 2 Section 3
Section 1 Section 2
Section 3
- - - - - -
- - - -
w 1r 0 w 0r 1w 1r 0Port 1
Port 2
Port 1
Port 2
mbist1.10 Cheng-Wen Wu, NTHU 47
Compacted Dual-Port RAM TestCompacted Dual-Port RAM Test
(c)
-
-
(d)
1r 0w1r N S0
N1r w
0
r 1r 0
w 1rr
S
0r
0r 1w 1
w
0w1
0
N0
r
1
0r
0
1r S
0
w 0
w
w 0
r
r 1w 1r 0 r 1 r 0 r
r
Section 1
Section 2
- -
-
- -
Sr
- - - -
-
0
N
- -
Port 1
Port 2
Port 1
Port 2
* Time complexity: 10N
mbist1.10 Cheng-Wen Wu, NTHU 48
Four-Port RAM TestFour-Port RAM Test
- - - -
0w 1w 1r 0w0r
1w 1r 0w0r
1w 1r 0w0r
1w 1r 0w0r
1r N0r N
1r S0r S
1r N0r N
1r S0r S
1r N0r N
1r S0r S
1r N0r N
1r S0r S
1r S0r S
0r N1r N
1r S0r S
0r N1r N
Port 1
Port 2
-
-
Port 3
Port 4
- - - - - - - -- - - -
- - - -
-
Inter-port Test
AF Test
- - - -
* Time complexity: 17N
mbist1.10 Cheng-Wen Wu, NTHU 49
Testing 6-Read-1-Write RAMTesting 6-Read-1-Write RAM
0r
0r0r
0r
0r
1r
1r
1r
1r
1r
1r
1r
1r
1r
1r
0r S
0r S
0r S
1r S
1r S
1r S
1r S
1r S
1r S
0r S1r N
1r N0r S
1r S
1r S
1r S
0r N
0r N
0r N
0r N
0r N
0r N
0r N
0r N
1r N0r S
0r S
0r S
1r N
1r N
1r N
1r N
1r N
1r N1r N
1r N
1r N
1r N0r N
0r N
0r N
0r N
Port 1 - - - ---
Port 3 - --
Port 2 - - -
Port 4 - - -
Port 5 - --
Port 6 - - -
Port 7 - --
M0 M1 M2 M3 M4 M5
Test for ports of
M6
distance 1Test for ports ofdistance 2 distance 3
Test for ports of
0w 0w 0w 0w1w 1w 1w
0r
0r0r
* Time complexity: 13N
mbist1.10 Cheng-Wen Wu, NTHU 50
Flash Memory TestingFlash Memory Testing Testing nonvolatile memories:
Masked ROM---exhaustive; pseudorandom PROM (OTP) & EPROM---dummy row EEPROM & flash memory---dummy row?
Testing flash memory core is hard Customized core and I/O Isolation (accessibility) Reliability issues: disturbances, over
program/erase, under program/erase, data retention, cell endurance, etc.
Long program/erase time
mbist1.10 Cheng-Wen Wu, NTHU 51
Flash Memory OverviewFlash Memory Overview Flash memory can be programmed and erased
electrically Has the advantages of EPROM and EEPROM
A stacked gate transistor with both the control gate (CG) and floating gate (FG):
G
D
SP-Si
n+ n+
Source Drain
Control gate Floating gate
mbist1.10 Cheng-Wen Wu, NTHU 52
Flash Memory Program & EraseFlash Memory Program & Erase
Program Erase
• Program(1 to 0): channel hot-electron (CHE) injection or Fowler-Nordheim (FN) electron tunneling• Erase (0 to 1): FN electron tunneling
• By the entire chip or large blocks (flash erasure)• Different products have different program/erase mechanisms
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Flash Memory Cell TypesFlash Memory Cell Types Stacked-gate Split-gate Select-gate
Operations: Read, Program, Erase (Flash Erase) As opposed to Read and Write in RAM
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Programming Scheme ComparisonProgramming Scheme Comparison
CHE Injection Channel FN Tunneling
High power (dual external supplies)
Low power (single external supply)
Low oxide field stress High oxide field stress
Faster program operation (byte program limited by power)
Slower program operation (improved by page program)
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NOR-Array StructureNOR-Array Structure
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NAND-Array StructureNAND-Array StructureSelect (drain)
Select (source)
WL 1
WL 2
WL 3
WL 4
WL 16
BL i
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Disturbance Example (I)Disturbance Example (I)
WL0
WL1
WL2
BL0 BL1 BL2 BL3
10V
0V
Program Disturbance
Drain-Disturb on "Programmed Cell"
Gate-Disturb on "Erased Cell"
6V 0V
0V
SL SL
0V
0V 6V
10V
0V
10V
Programming
NOR-Type Common Ground – Standard (Stacked Gate)
mbist1.10 Cheng-Wen Wu, NTHU 58
Disturbance Example (II)Disturbance Example (II)
WL0
WL1
WL2
BL0 BL1 BL2 BL3
5V
0V
Read Disturbance
Soft-Program on "Selected Cell"
1V
SL SL
mbist1.10 Cheng-Wen Wu, NTHU 59
Disturbance Example (III)Disturbance Example (III)
BL1
Program Disturbance
Program '1'
WL0
WL1
WL2
BL0
SSL
GSL
2.8V
2.8V
18V
3.3V3.3V
0V
10V
2.8V
BL2
18V
0V
0V
10V
0V
3.3V0V
0V
10V
0V
Program '0'
Gate-Disturb on "Erased Cell"
Gate-Disturb on "Programmed Cell"
mbist1.10 Cheng-Wen Wu, NTHU 60
Disturbance Example (IV)Disturbance Example (IV)
BL1
Read Disturbance
WL0
WL1
WL2
BL0
SSL
GSL
0V
5V5V
5V
5V
BL2
0V
5V
0.7V
5V
5V
Vth=-3VVth=+2V
5V
5V
soft-program
BL1
Erase Disturbance
WL0
WL1
WL2
BL0
SSL
GSL
0V
Floating
Floating
0V
BL2
0V
0V
Floating
0V
0V
Floating
21V
21V
21V21V
21V
21V21V
21V
21V
mbist1.10 Cheng-Wen Wu, NTHU 61
Gate Program Disturb Fault (GPDF)Gate Program Disturb Fault (GPDF)
V(H)
V(H)
V(L)
V(L)
V(Gd)
Conditions:
1.Victim cell initial value is a logic ‘1’
2.Aggressor “10” (program)
Victim “10” (program)Control Gate
Floating Gate
Source Drain
Substrate
G
S D
B
mbist1.10 Cheng-Wen Wu, NTHU 62
Gate Erase Disturb Fault (GEDF)Gate Erase Disturb Fault (GEDF)
V(H)
V(H)
V(L)
V(L)
V(Gd)
Conditions:
1.Victim cell initial value is a logic ‘0’
2.Aggressor “10” (program)
Victim “01” (erase)Control Gate
Floating Gate
Source Drain
Substrate
G
S D
B
mbist1.10 Cheng-Wen Wu, NTHU 63
Drain Program Disturb Fault (DPDF)Drain Program Disturb Fault (DPDF)
V(H)
V(H)
V(L)
V(Gd)
• During programming, erased cells on unselected rows on a bit-line that is being programmed may have a fairly deep depletion region formed under them
• Electrons entering this depletion region can be accelerated by the electric field and injected over the oxide potential barrier to adjacent floating gates
Conditions:
1.Victim cell initial value is a logic ‘1’
2.Aggressor “10” (program) Victim “10” (program)
mbist1.10 Cheng-Wen Wu, NTHU 64
Drain Erase Disturb Fault (DEDF)Drain Erase Disturb Fault (DEDF)
V(H)
V(H)
V(L)
V(L)
V(Gd)
Conditions:
1.Victim cell initial value is a logic ‘0’
2.Aggressor “10” (program)
Victim “01” (erase)Control Gate
Floating Gate
Source Drain
Substrate
G
S D
B
mbist1.10 Cheng-Wen Wu, NTHU 65
Read Disturb Fault (RDF)Read Disturb Fault (RDF)
Control Gate
Floating Gate
Source Drain
Substrate
G
S D
B
Conditions:
1. Occurs on the selected cell
2. Cell initial value is logic ‘1’
Soft-Program• During the read operation,
hot carriers can be injected
from the channel into the FG
even if at low gate voltages
mbist1.10 Cheng-Wen Wu, NTHU 66
Over Erase Fault (OEF)Over Erase Fault (OEF) Flash memory erase mechanism is not
self-limiting
Threshold voltage can be low enough to turn the cell into a depletion-mode transistor
Fault behavior: An unselected cell in the same bit-line has
excessive source-drain leakage current Reading that cell leads to incorrect value
(like DEDF) Cannot be programmed correctly (like TF)
mbist1.10 Cheng-Wen Wu, NTHU 67
Basic RAM Faults for Flash MemoryBasic RAM Faults for Flash Memory
Address-Decoder Fault (AF)
Stuck-At Fault (SAF)
Transition Fault (TF)
Stuck-Open Fault (SOF)
Bridging Fault (BF)
Coupling faults need not be considered!Replaced by disturb faults
mbist1.10 Cheng-Wen Wu, NTHU 68
Reliability ConsiderationReliability Consideration
Reliability characteristics of floating-gate ICs depend on Circuit density, circuit design, and process
integrity Memory array type and cell structure
Reliability stressing and testing must then be oriented toward determining the relevant failure rates for the particular array under consideration
mbist1.10 Cheng-Wen Wu, NTHU 69
Data Retention FaultData Retention Fault Retention time: the time from data storage to the
time at which a verifiable error is detected from any cause Intrinsic retention times exceed millions of years in
the operating temperature range Months at 300°C 1 million years at 150 °C 120 million years at 55 °C
Data Retention Fault (DRF) Static leakage Built-in data retention test circuit
mbist1.10 Cheng-Wen Wu, NTHU 70
Cell Endurance FaultCell Endurance Fault Endurance: a measure of the ability to meet data-
sheet specifications as a function of accumulated program/erase cycles Endurance limit is a result of damage to the
dielectric around the floating gate caused by electric stresses
In many flash devices, the end of endurance is generally caused by hot electron trapping in the charge transport oxide
Cell Endurance Fault (CEF) Threshold window shift due to increased
program/erase cycles Built-in stress test circuit
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Composite Failure Rate DeterminationComposite Failure Rate Determination
125°C dynamic life stress The 125°C dynamic life stress is the standard
MOS memory continuous dynamic read in a burn-in chamber
Endurance test The endurance test is the repeated data
complementing of floating-gate devices, possibly at temperature extremes
Extended data retention stress This test is constituted by a high-temperature bake
with a charge polarity that is opposite to the equilibrium state on the floating gate
mbist1.10 Cheng-Wen Wu, NTHU 72
Typical Test Modes (Characterization)Typical Test Modes (Characterization) Stress (row/column)
Reverse tunneling stress Punch through stress Tox stress DC stress
Mass program Weak erase Leak (thin-oxide, bit-line, etc.) Cell current; cell Vt Margin Etc.
mbist1.10 Cheng-Wen Wu, NTHU 73
Test PatternsTest Patterns A RAM test pattern definition includes both the
data pattern and the address pattern The time to read a pattern is the same as the time
to write a pattern
For flash memories, however, the address and data pattern definitions must be segregated It has long write times relative to the read times
Typical data patterns: Solid, checkerboard, random, etc.
Typical address patterns: Address increment/decrement, address
complement, column/diagonal galloping, etc.
mbist1.10 Cheng-Wen Wu, NTHU 74
Testing GPDFTesting GPDF
Flash
Program the first column
Read all cells except the first column
Flash
Program any column except the first
Read the first column
*Assume reading and programming are done column-wise
Source: Saluja, et al., Int. Conf. VLSI Design, 2000
mbist1.10 Cheng-Wen Wu, NTHU 75
Testing GEDFTesting GEDF
Flash
Program all cells
Read all cells except the last column
Program any column except the last
Read the last column
*Assume reading and programming are done column-wise
Source: Saluja, et al., Int. Conf. VLSI Design, 2000
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Test Coverage: Previous ResultsTest Coverage: Previous Results
Fault DCP DCE DD EF GF
SAF 50% 50% 50% 100% 100%TF 12.5% 50% 50% 87.5% 62.5%AF 40% 0% 0% 44.5% 40%SOF 0% 0% 0% 12.5% 6.2%CFst 25% 25% 25% 50% 50%GPDF 33.3% 0% 0% 100% 33.3%GEDF 0% 100% 75% 100% 100%DEDF 0% 75% 100% 100% 100%DPDF 0% 0% 0% 0% 0%
Source: Saluja, et al., Int. Conf. VLSI Design, 2000
mbist1.10 Cheng-Wen Wu, NTHU 77
March-Based Flash Test: March-FTMarch-Based Flash Test: March-FT {(f); (r1,w0,r0); (r0); (f); (r1,w0,r0);
(r0)}This Flash memory is NOR type (Stacked gate).
Memory size (N) : 65536
Test length : 2(chip erase time) + 131072(word program time) + 393216(word read time)
Test time : 7.207173 sec
SAF : 100% (131072 / 131072) P.S.
TF : 100% (131072 / 131072) Flash Type = NOR
SOF : 100% (65536 / 65536) Gate Type = Stack
AF : 100% (4294901760 / 4294901760) Row Number = 256
CFst : 100% (17179607040 / 17179607040) Col Number = 256
GPD : 100% (16711680 / 16711680) Word Length = 1
GED : 100% (16711680 / 16711680) Chip erase time = 3 sec
DPD : 100% (16711680 / 16711680) Word program time = 9u sec
DED : 100% (16711680 / 16711680) Word read time = 70n sec
RD : 100% (65536 / 65536)OE : 100% (65536 / 65536)
mbist1.10 Cheng-Wen Wu, NTHU 78
Test Length (Bit-Oriented)Test Length (Bit-Oriented)
Notation: F : Flash time P : Program time R : Read time r : row number c : column number
DCP 2(F) + 2r(P) + rc(R)
DCE (F) + (c+1)r(P) + rc(R)
DD (F) + (r+1)c(P) + rc(R)
EF 2(F) + (rc+2r+c-2)(P) + (2rc+r+c-3)(R)
GF 2(F) + (rc+2r+c-1)(P) + (2rc+c+r-2)(R)
FT 2(F) + 2rc(P) + 6rc(R)
mbist1.10 Cheng-Wen Wu, NTHU 79
Test Length (Word-Oriented)Test Length (Word-Oriented) Word length = w:
2(F)+2rc(P)+6rc(R)+log(w)[2(F)+rc(P)+rc(R)]
Solid: 0000 (1111) Standard: 0101 (1010), 0011 (1100)
Ex: word length w = 4 6(F) + 4rc(P) + 8rc(R)
solid background
testing time
standard background
testing time
mbist1.10 Cheng-Wen Wu, NTHU 80
Test Algorithm Generation by Simulation (TAGS)Test Algorithm Generation by Simulation (TAGS)
T(N) Test algorithms
2N
3N
4N
5N
6N
7N
8N
9N
10N
(f); (r1)
(f); (w0); (r0)
(f); (r1,w0); (r0)
(f); (r1,w0,r0); (r0)
(f); (r1,w0,r0); (r0,w0)
(f); (r0); (r1,w0,r0); (r0,w0)
(f); (r1,w0); (f); (r1,w0,r0); (r0)
(f); (r1,w0); (r0); (f); (r1,w0,r0); (r0)
(f); (r1,w0,r0); (r0); (f); (r1,w0,r0); (r0)
mbist1.10 Cheng-Wen Wu, NTHU 81
Embedded Memory TestingEmbedded Memory Testing Memories are one of the most universal cores
In Alpha 21264, cache RAMs represent 2/3 transistors and 1/3 area; in StrongArm SA110, the embedded RAMs occupy 90% area [Bhavsar, ITC-99]
In average SOC, memory cores will represent more than 90% of the chip area by 2010 [ITRS 2000]
Embedded memory testing is increasingly difficult High bandwidth (speed and I/O data width) Heterogeneity and plurality Isolation (accessibility) AC test, diagnostics, and repair
BIST is considered the best solution
mbist1.10 Cheng-Wen Wu, NTHU 82
Embedded RAM Test SupportEmbedded RAM Test Support
Test run Isolation only Isolation & BISTProbe test Tester Tester/BISTPre-BI test Tester BISTBI BI board BISTPost-BI test Tester BISTFinal test Tester Tester/BIST
mbist1.10 Cheng-Wen Wu, NTHU 83
RAM BIST ApproachesRAM BIST Approaches Methodology
Processor-based BIST Programmable
Hardwired BIST Fast Compact
Interface Serial (scan, 1149.1) Parallel (embedded controller; hierarchical)
Patterns (address sequence) March Pseudorandom
mbist1.10 Cheng-Wen Wu, NTHU 84
Typical RAM BIST ArchitectureTypical RAM BIST Architecture
RAMT
est C
ollar (M
UX
)
BIST Module
Controller
Comparator
Pattern
Generator
Go/No-Go
RAM Controller
mbist1.10 Cheng-Wen Wu, NTHU 85
Serial March (SMarch)Serial March (SMarch)
• From March C-
• Serial interface
• One BIST for all (cascaded)
• One-bit read/write at a time, but one pattern per cycle
• Slow
• No diagnostics
})00()00(;)00()01(;)11()10(
;)00()01(;)11()10(;)00()0x({cccccc
cccccc
wrwrwrwrwrwr
wrwrwrwrwrwr
Source: Nadeau-Dostie et al., IEEE D&T, Apr. 1990
Memory Cell Array
X D
ecoder
Y Decoder
Transparent Serial Data-MUX
Addr
SI SO
D Qc
c
mbist1.10 Cheng-Wen Wu, NTHU 86
Syntest MBISTSyntest MBIST
Algorithms: March C- MOVI March C++ Checkerboard
Shared controller for multiple RAMs
Synthesizable RTL code
FSM
Data Generator
Analyzer
ADR Control
CE
OE
WEB
A
D
Q
Pass
BistFail
Finish
Source: Syntest
mbist1.10 Cheng-Wen Wu, NTHU 87
NTHU/GUC EDO DRAM BISTNTHU/GUC EDO DRAM BIST
mbist1.10 Cheng-Wen Wu, NTHU 88
DRAM Page-Mode Read-Write CycleDRAM Page-Mode Read-Write Cycle
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Programmable Memory BIST Programmable Memory BIST (PMBIST)(PMBIST)
mbist1.10 Cheng-Wen Wu, NTHU 90
PMBIST ArchitecturePMBIST Architecture
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Controller and SequencerController and Sequencer Controller
Microprogram Hardwired Shared CPU core IEEE 1149.1 TAP
Sequencer (Pattern Generator) Counter LFSR LUT
mbist1.10 Cheng-Wen Wu, NTHU 92
ControllerController
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SequencerSequencer
Combination Logic #0
Row Address Counter
Column AddressCounter
State
Combination Logic #1
eDRAMcontrolsignal
MCKMCK
Flags
eDRAMBIST
Controller
D Q
D Q
D Q
D Q
D Q
D Q
D Q
D Q
Control Counter
Comparator
mbist1.10 Cheng-Wen Wu, NTHU 94
PMBIST Test ModesPMBIST Test Modes
1. Scan-Test Mode
2. RAM-BIST Mode
1.Functional faults
2.Timing faults (setup/hold times, rise/fall times,
etc.)
3.Data retention faults
3. RAM-Diagnosis Mode
4. RAM-BI Mode
mbist1.10 Cheng-Wen Wu, NTHU 95
PMBIST Controller CommandsPMBIST Controller Commands
Bit 4Addressing order
Bit 3Data type
Bit 2, Bit 1, Bit 0Operations
1: (increasing) 1: d = DB 000: EOT (End of test)0: (decreasing) 0: d = ~DB 001: Rd (READ Cycle)
010: Wd (Early WRITE Cycle)011: RdW~d (READ-WRITE) Cycle
EDO-PAGE-MODE100: Wd (Early WRITE Cycle101: RdW~d (READ-WRITE) Cycle110: RdW~dR~d (READ Early WRITE Cycle)111: Refresh
mbist1.10 Cheng-Wen Wu, NTHU 96
PMBIST Control SequencePMBIST Control Sequence
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BIST Area OverheadBIST Area Overhead
3%
0.3%
Overhead
Mem size
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Processor-Based RAM BISTProcessor-Based RAM BISTProcessor
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On-Chip Processor-Based RAM BISTOn-Chip Processor-Based RAM BIST BIST program is stored in boot ROM during
design phase, and memory BIST is done by executing BIST program
Address bus
Embedded memory
CPU core
BOOT ROM
DATAI bus
DATAO bus
Control bus
I/O port
mbist1.10 Cheng-Wen Wu, NTHU 100
Testing RAM Core by On-Chip CPUTesting RAM Core by On-Chip CPU 6502 assembly program that performs March C-
test algorithm
.org 0HFF00LDX #$$00LDA #$$55
M0: STA 0000,XINXCPX #$$FFBNE M0LDX #$$00
M1: LDA 0000,XCMP #$$55BNE ERRORLDA #$$AASTA 0000,XINXCPX #$$FFBNE M1LDX #$$00
. . . . .
(W0)
(R0W1)
(R1W0)
(R0W1)
(R1W0)
(R0)
March C- algorithm
data background
write data background to memory
read from memory
write data background to memory
mbist1.10 Cheng-Wen Wu, NTHU 101
Test Speed ConsiderationTest Speed Consideration Processor-BIST speed is lower than dedicated
BIST circuit
Total clock cycles to implement MARCH C- is O(114N)
IMM ABX IMP REL
LDA 2 4 - -
LDX 2 - - -
STA - 4 - -
INX - - 2 -
CPX 2 - - -
BNE - - - 2~4
CMP 2 - - -
Table 1. 6502 instruction cycles
mbist1.10 Cheng-Wen Wu, NTHU 102
NTHU Processor-Programmable BISTNTHU Processor-Programmable BIST
BIST core embedded memory
I/O circuitry
BIST circuitry
embedded CPU
1
0
1
0
0
1
0
1
mux_sel
mux_sel = 0 in normal modemux_sel = 1 in BIST mode
on-chip bus
ADDR
DATAO
control
DATAI
A
DI
DO
control
ADDR_cpu
DATAO_cpu
clock_cpu
ctrl_cpu
DATAI_cpu
ADDR_bistDATAO_bist
ctrl_bist
DATAI_sysDATAI_bist
mbist1.10 Cheng-Wen Wu, NTHU 103
Advantages and DisadvantagesAdvantages and Disadvantages Advantages
Reuse of on-chip CPU core Might need modification
Core March elements can be implemented in hardware, allowing different March algorithms to be executed via assembly programming
Disadvantages Some address space will be occupied by PPBIST Area overhead
mbist1.10 Cheng-Wen Wu, NTHU 104
PPBIST ImplementationPPBIST Implementation
mbist1.10 Cheng-Wen Wu, NTHU 105
PPBIST Data RegistersPPBIST Data Registers
Register Function
RBG Store background data
RAL Store lowest address
RAH Store highest address
RME Store current March element
RIR Instruction register
RFLAG Status register
RED Erroneous response of defective memory cell
REA Address of defective memory cell
mbist1.10 Cheng-Wen Wu, NTHU 106
PPBIST Test ProcedurePPBIST Test Procedure
CPU write data back groundCPU write start/stop addressCPU write MARCH element instructionCPU write START instruction to wrapper
BIST core(R0W1)
BIST core(R1W0)
BIST core(R0W1)
BIST core(R1W0)
BIST core(W0)
BIST core(R0)
compare error?
complete?
write error flagwrite faulty addresswrite faulty data
write complete flag
yes
yes
nono
CPU take over
mbist1.10 Cheng-Wen Wu, NTHU 107
PPBIST Example Using 6502PPBIST Example Using 6502 6502 assembly program that performs March C-
test algorithm under the proposed BIST scheme
START: LDA #$$55STA 0HFFE0LDA #$$00STA 0HFFE1LDA #$$00STA 0HFFE2LDA #$$FFSTA 0HFFE3LDA #$$0FSTA 0HFFE4
M0: LDA #$$00STA 0HFFE5JSR BIST
M1: LDA #$$01. . . . . .
END: LDA #$$04STA 0HFFE6JMP FINISH
BIST: LDA #$$00STA 0HFFE6
LOOP: LDA 0HFFE7CMP #$$01BEQ ERRORCMP #$$FFBNE LOOPRTS
ERROR: LDA #$$03STA 0HFFEAJMP FINISH
mbist1.10 Cheng-Wen Wu, NTHU 108
PPBIST ExamplePPBIST Example Addresses of the registers in the BIST experiment
Register Address
RBG FFE0
RAL FFE1 ~ FFE2
RAH FFE3 ~ FFE4
RME FFE5
Register Address
RIR FFE6
RFLAG FFE7
RED FFE8
REA FFE9 ~ FFEA
March elements and the corresponding RME
M0 M1 M2 M3 M4 M5
0H 1H 2H 3H 4H 5H
mbist1.10 Cheng-Wen Wu, NTHU 109
Experimental ResultsExperimental Results Total test time in terms of clock cycles
The sum of all the March elements' test time plus 30 clock cycles
10N clock cycles to perform March C-
Test time of each March element :
M0 M1 M2 M3 M4 M5
1N 2N 2N 2N 2N 1N
mbist1.10 Cheng-Wen Wu, NTHU 110
Comparison of BIST MethodologiesComparison of BIST Methodologies
BIST scheme Test time H/W overhead Routing overhead
Integrated BIST core Short Low High
On-chip processor Very long Zero Zero
Ours Short Very low zero
mbist1.10 Cheng-Wen Wu, NTHU 111
RAM BIST CompilerRAM BIST Compiler
Use of RAM cores is increasing. SRAM, DRAM, flash RAM Multiple cores
RAM BIST compiler is the trend.
BRAINS (BIST for RAM in Seconds) Proposed BIST Architecture Memory Modeling Command Sequence Generation Configuration of the Proposed BIST
mbist1.10 Cheng-Wen Wu, NTHU 112
BRAINS OutputsBRAINS Outputs
Synthesizable BIST design At-speed testing Programmable March algorithms Optional diagnosis support
BISD
Activation sequence
Test bench
Synthesis script
mbist1.10 Cheng-Wen Wu, NTHU 113
BIST Synthesis FlowBIST Synthesis Flow
GUI
RAM/BISTDescription
Parser
CompileEngine
MemoryLibrary
BIST Template
Synthesis
Cell Library
RTL
Netlist
mbist1.10 Cheng-Wen Wu, NTHU 114
NTHU/GUC PMBIST ArchitectureNTHU/GUC PMBIST Architecture
Controller
Memory
MBS
Test C
ollar
Sequencer
Comparator
MBCMBRMSI
MSO
MRD
MBO
MCK
NormalAccess
Controls
Address
D
Q
Programmable Memory BIST
TPG
mbist1.10 Cheng-Wen Wu, NTHU 115
Controller SequencerTest
PatternGenerator
Test Command/Information StorageModule
Serialdata in
Serialdata out
Error Error
ToMemory
Address
BISTcontrolsignals
MemoryCommandCommand
Hand-shaking
PMBIST with ScanPMBIST with Scan
Source: Cheng, et al., DFT00
mbist1.10 Cheng-Wen Wu, NTHU 116
SequencerSequencer
ControlModuleControlModule
Address GeneratorAddress Generator
Sequence GeneratorSequence Generator
Command GeneratorCommand Generator
Error Handling Module
address
command
errorinfo.
go
errorsignature
mbist1.10 Cheng-Wen Wu, NTHU 117
State Diagram of Control ModuleState Diagram of Control Module
BISTapplyBISTapply
BISTdoneBISTdone
BISTidle
BISTidle
BISTapplyBISTapply
BISTdoneBISTdone
BISTidle
BISTidle
BISTactiveBISTactive
For DRAMFor SRAM
mbist1.10 Cheng-Wen Wu, NTHU 118
DRAM Page-Mode OperationDRAM Page-Mode Operation
mbist1.10 Cheng-Wen Wu, NTHU 119
Memory Specification TechniquesMemory Specification Techniques
Memory SpecificationsI/O SpecificationCommand SpecificationTask SpecificationDelay Constraint SpecificationAC Parameter Specification
Support customized memories.
mbist1.10 Cheng-Wen Wu, NTHU 120
I/O SpecificationI/O Specification
Four parameters IO_type IO_width IO_latency IO_packet_length
IO_type: input, output, or inout
IO_width: port width (#bits), can be a constant or specified by user
mbist1.10 Cheng-Wen Wu, NTHU 121
I/O SpecificationI/O Specification IO_latency: port latency
mbist1.10 Cheng-Wen Wu, NTHU 122
I/O ModelingI/O Modeling IO_packet_length: #bits packed within a clock
cycle for the port
mbist1.10 Cheng-Wen Wu, NTHU 123
Command SpecificationCommand Specification
Specifies the memory’s instructions
mbist1.10 Cheng-Wen Wu, NTHU 124
Task SpecificationTask Specification Specifies a complete memory operation
A task can be a single command or a sequence of commands.
mbist1.10 Cheng-Wen Wu, NTHU 125
Delay Constraint SpecificationDelay Constraint Specification
Specifies the minimal time interval between any two tasks
mbist1.10 Cheng-Wen Wu, NTHU 126
AC Parameter SpecificationAC Parameter Specification Specifies input and output delays
Specified parameters will be inserted into the synthesis script.
mbist1.10 Cheng-Wen Wu, NTHU 127
Memory Specification ExampleMemory Specification Example
For ZBT SRAM: Method A:
@latency D = 1; @task write = {write};
Method B: @latency D = 0; @task write = {pre_write, post_write};
The BIST circuit from method A is faster than the one from method B, but it has higher area overhead
mbist1.10 Cheng-Wen Wu, NTHU 128
Sequence GenerationSequence Generation
For each March element, the compiler generates the command sequence according to the read task, write task, and minimum delay between the two tasks
For example: task read = {A} task write = {B, C} minimum delay between read and write = 10ns clock period = 10 ns Then the (rw) element becomes {A, nop, B, C}
One can also optimize the command sequence
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Fast Access ModeFast Access Mode
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Diagnosis SupportDiagnosis Support The BIST circuit scans out the error information
(element, address, signature, and polarity) during the diagnosis mode.
Assume address 20h stuck-at 64h:
mbist1.10 Cheng-Wen Wu, NTHU 131
Multiple RAM CoresMultiple RAM Cores Controller and sequencer can be shared.
controller
Test pattern generator
Test pattern generator
sequencer
Ram Core ARam Core A
Ram Core BRam Core B
Ram Core CRam Core CTest pattern generator
sequencer
mbist1.10 Cheng-Wen Wu, NTHU 132
Experimental ResultsExperimental Results The Built-In Memory List
DRAM EDO DRAM SDRAM DDR SDRAM
SRAM Single-Port Synchronous SRAM Single-Port Asynchronous SRAM Two-Port Synchronous Register File Dual-Port Synchronous SRAM Micron ZBT SRAM
BRAINS can support new memory architecture easily
mbist1.10 Cheng-Wen Wu, NTHU 133
Experimental ResultsExperimental Results
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Experimental ResultsExperimental Results Four single-port SRAM BIST circuits share the same controller and
sequencer.
Size of the SRAM core: 8K x 16
OriginalBIST area for single-port SRAM: 1438 (gates)Total area = 1438 * 4 = 5752 (gates)
Sharedgate count: 3350
mbist1.10 Cheng-Wen Wu, NTHU 135
Experimental ResultsExperimental Results 8K x 16 single-port synchronous SRAM (0.25um)
Area: Die size: 1780.74 x 755.07 um2
BIST area: 80.1 x 583.48 um2
Area overhead : 3.4%
mbist1.10 Cheng-Wen Wu, NTHU 136
Experimental ResultsExperimental Results 2K x 32 two-port register file (0.25um)
Die size: 1130.74 x 936.34 um2
BIST area: 77.88 x 620 um2
Area overhead: 4.5%
mbist1.10 Cheng-Wen Wu, NTHU 137
Why RAM Diagnostics?Why RAM Diagnostics? Memory testing is more and more important
Memories are key components Represent about 30% of the semiconductor market Dominate the chip area/yield
Memory testing is more and more difficult Growing density, capacity, and speed Emerging new architectures & technologies Growing need for embedded memories
Why diagnostics? Yield improvement
Repair and/or design/process debugging
mbist1.10 Cheng-Wen Wu, NTHU 138
Fault Model SubtypesFault Model Subtypes
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NTHU-FTC BIST ArchitectureNTHU-FTC BIST Architecture
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Test ModeTest Mode
In Test Mode it runs a fixed algorithm for production test and repair Only a few pins need to be controlled, and BGO
reports the result (Go/No-Go)
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Fault Analysis ModeFault Analysis Mode In Fault Analysis Mode, we can apply a longer
March algorithm for diagnosis FSI captures the error information of the faulty
cells
EOP format:
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Error Catch and AnalysisError Catch and Analysis Locate the faulty cells
Identify the fault types
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How to Identify Fault Type?How to Identify Fault Type?
RAM Circuit/Layout Tester/BIST Output
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March DictionaryMarch Dictionary
March 11N
E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10
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March Signature and Error MapMarch Signature and Error Map
March Signature (Syndrome)
Error Map
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MECA SystemMECA System
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Error AnalyzerError Analyzer
Data log parser
Tester/BIST data log
Fault analysis
Error maps
Fault maps
March
Dictionary
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Fault AnalysisFault Analysis
Derive analysis equations from the fault dictionary
Convert error maps to fault maps by the equations
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Test Algorithm GenerationTest Algorithm Generation Start from a base test: generated by TAGS or
user-specified Generation options reduced to read-insertions
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Diagnostic ResolutionDiagnostic Resolution
Diagnostic resolution
faults detectable of #
faults habledistinguis of # resolution Diagnostic
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Experimental ResultsExperimental Results
Proposed diagnosis framework has been applied to commercial embedded SRAMs
Results for a 16Kx8 embedded SRAM (FS80A020) are shown
Tester log from Credence SC212 is examined
Address remapping (logical to physical) is applied
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The Total Error BitmapThe Total Error Bitmap
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Fault BitmapsFault Bitmaps
Idempotent Coupling Fault Stuck-at 0
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Redundancy and RepairRedundancy and Repair Problem: We keep shrinking the feature size and
increasing the chip density and size. How do we maintain the yield?
Solutions: Fabrication
Material, process, equipment, etc. Design
Device, circuit, etc. Redundancy and repair
On-line EDAC (extended Hamming code; product code)
Off-line Spare rows and/or columns
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From BIST to BISRFrom BIST to BISR
BISTBIST BISDBISD BIRABIRA BISRBISR
•BIST: built-in self-testBIST: built-in self-test•BIECA: built-in error catch & analysisBIECA: built-in error catch & analysis
-BISD: built-in self diagnosisBISD: built-in self diagnosis-BIRA: built-in redundancy analysisBIRA: built-in redundancy analysis
•BISR: built-in self-repairBISR: built-in self-repair
•BIST: built-in self-testBIST: built-in self-test•BIECA: built-in error catch & analysisBIECA: built-in error catch & analysis
-BISD: built-in self diagnosisBISD: built-in self diagnosis-BIRA: built-in redundancy analysisBIRA: built-in redundancy analysis
•BISR: built-in self-repairBISR: built-in self-repair
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RAM Built-In Self-Repair (BISR)RAM Built-In Self-Repair (BISR)
RAM
MU
XBIST
Redundancy
Analyzer
Reconfiguration MechanismS
pare
Ele
me
nts
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RAM RedundancyRAM Redundancy 1-D: spare rows (or columns) only
SRAM Algorithm: Must-Repair
2-D: spare rows and columns Local and/or global spares NP-complete problem Conventional algorithm:
Must-Repair phase Final-Repair phase
Repair-Most (greedy) [Tarr et al., 1984] Fault-Driven (exhaustive, slow) [Day, 1985] Fault-Line Covering (b&b) [Huang et al., 1990]
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Redundancy ArchitecturesRedundancy Architectures
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An SRAM with BISRAn SRAM with BISR
[Kim et al., ITC 98][Kim et al., ITC 98]
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A DRAM Redundancy ExampleA DRAM Redundancy Example
4 local spare rows per block
2x4=8 global spare columns
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DefinitionsDefinitions Faulty line: row or column with at least one faulty
cell.
A faulty line is covered if all faulty cells in the line are repaired by spare rows and/or columns.
A faulty cell not sharing any row or column with any other faulty cell is an orthogonal faulty cell.
r: number of (available) spare rows
c: number of (available) spare columns
F: number of faulty cells in a block
F’:number of orthogonal faulty cells in a block
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Example Block with Faulty CellsExample Block with Faulty Cells
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Repair-Most (RM)Repair-Most (RM)
• Run BIST and construct bitmap.• Construct row and column error counters.• Run Must-Repair algorithm.• Run greedy Final-Repair algorithm.
• Run BIST and construct bitmap.• Construct row and column error counters.• Run Must-Repair algorithm.• Run greedy Final-Repair algorithm.
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Worst-Case Bitmap (After Must-Worst-Case Bitmap (After Must-Repair)Repair)
r=2; c=4r=2; c=4
•Max F=2rc.•Max F=2rc.
•Max F’=r+c.•Max F’=r+c.
•Bitmap size: (rc+c)(cr+r).•Bitmap size: (rc+c)(cr+r).
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Local Repair-Most (LRM)Local Repair-Most (LRM) RM is not good enough for embedded RAM.
Large storage requirement: bitmap and counters Slow
LRM improves the performance. Repair-Most based Improved heuristics Early termination rules Concurrent BIST and BIRA No separate Must-Repair phase
LRM reduces the storage required. Smaller local bitmap
From (rc+c)x(cr+r) to mxn
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LRM AlgorithmLRM Algorithm Activated by BIST whenever a faulty cell is
detected.
Fault Collection (FC) Collects faulty-cell addresses. Constructs local bitmap. Counts row and column errors.
Spare Allocation (SA) Allocate spare rows or columns when bitmap is full. Allocate spare rows or columns at end.
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LRM: FC and SALRM: FC and SA
(1,0), (1,6), (2,4), (3,4), (5,1), (5,2)(1,0), (1,6), (2,4), (3,4), (5,1), (5,2)
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LRM ExampleLRM Example
(5,2)(5,2) (5,4),(5,6),(5,7)(5,4),(5,6),(5,7) (7,3)(7,3)
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Local Optimization (LO)Local Optimization (LO) LMR has drawbacks:
Selecting line with largest fault count may be slow. Multiple lines may need to be selected for repair. Area overhead is still high. Repair rate depends on bitmap size.
LO has a better repair rate based on same hardware overhead, i.e., a higher repair efficiency. Fault Collection (FC)
Records faulty cells in bitmap until it is full. Spare Allocation (SA)
Exhaustive search performed for repairing all faults. Bitmap cleared; process repeated until done.
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LO: Column*/Row Selection for SALO: Column*/Row Selection for SAA 1 means that the corresponding
col is selected for repair, unless empty.A 1 means that the corresponding
col is selected for repair, unless empty.
* Assume column selection has a lower cost than row selection.* Assume column selection has a lower cost than row selection.
Col selection vectorCol selection vector
1. Col 5 selected for repair.1. Col 5 selected for repair.
Row selection vectorRow selection vector
2. Row 5 is selected for repair.2. Row 5 is selected for repair.
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LO ExampleLO Example
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Essential Spare Pivoting (ESP)Essential Spare Pivoting (ESP) Maintain high repair rate without using a bitmap.
Small area overhead.
Fault Collection (FC) Collect and store faulty-cell address using row-
pivot and column-pivot registers. If there is a match for row (col) pivot, the pivot is an
essential pivot. If there is no match, store the row/col addresses in
the pivot registers. If F > r+c, the RAM is unrepairable.
Spare Allocation (SA) Use row and column pivots for spare allocation.
Spare rows (cols) for essential row (col) pivots. SA for orthogonal faults.
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ESP ExampleESP Example
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Cell Fault Size DistributionCell Fault Size Distribution
Mixed Poisson-exponential distribution.Mixed Poisson-exponential distribution.
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Repair Rate ComparisonRepair Rate Comparison
•1,552 RAM blocks.•1,024x64 bits per block.•r from 6 to 10.•c from 2 to 6.•LRM bitmap: rxc.•LO bitmap: 8x4.
•1,552 RAM blocks.•1,024x64 bits per block.•r from 6 to 10.•c from 2 to 6.•LRM bitmap: rxc.•LO bitmap: 8x4.
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Normalized Repair RateNormalized Repair Rate
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Repair Rate (r=10)Repair Rate (r=10)
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Normalized Repair Rate (r=6)Normalized Repair Rate (r=6)
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Area OverheadArea Overhead
Overhead is about 5-12% for 16Mb DRAM, r=8, and c=4.Overhead is about 5-12% for 16Mb DRAM, r=8, and c=4.
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Computation Time (Simulated)Computation Time (Simulated)