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Unit II Interrupt Structure

Interrupt Vector Table (IVT)

ISR

Hardware and software Interrupts

Internals of DOS

DOS loading DOS memory map

Internal and eternal commands of DOS

!IOS " DOS Interrupts

#oncepts of $S$% &'' " O *les #oncepts of TSR

8259($rogrammable Interrupt #ontroller)+ ,eatures%!loc- Diagram% #ontrol " status registers% Interfacing "$rogramming

#omputer emory " emory apping in ./ !it

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Interrupts

0n interrupt refers to t1e c1ange instate of t1e #$U as a result of acondition w1ic1 is eternal to t1esystem or wit1in t1e system&

T1e terms eception% trap% super2isorcall% system call are t1e synonyms of

t1e term interrupt&

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Intel De*nition Of Interrupt

Interrupts and eceptions are special -inds ofcontrol transfer3 t1ey wor- somew1at li-eunprogrammed #044s&

T1ey alter t1e normal program 5ow to 1andle

an eternal e2ent or to report error oreceptional condition&

T1e di6erence between interrupts andeception is t1at t1e interruptsare used

1andle async1ronous e2ents (processor doesnot wait for an e2ent to occur ) eternal to t1eprocessor and exceptions1andle conditionsdetected by t1e processor itself in t1e course ofeecuting instructions&

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0n interrupt is a 1ardware signal t1at informst1e #$U to temporarily 1alt its currentacti2ities and transfer control to a program

called interrupt 1andler or Interrupt Ser2iceRoutine (ISR)&

T1e #$U would 1a2e to constantly c1ec- foreternal e2ents in t1e absence of interrupts

w1ic1 is called as $olling3 wit1 interrupts % t1e#$U can perform some ot1er operation andstill respond to an e2ent as soon as it occurs&

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Interrupt vs. Polling

7 $olling0s- t1e de2ice if it 1as any data

0ll intelligence is in t1e #$U

CPU controls interaction with thedevice

7 InterruptsDe2ice tells t1e #$U t1at is ready wit18for

data or needs ser2ice by interrupting t1e #$U

Intelligence is mo2ed to t1e de2ice Device informs the CPU when it needs

service

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91ic1 is better8faster:

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;&Interrupts are more complicated

Di

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0n interrupt is an eternal e2ent w1ic1 informst1e #$U t1at a de2ice needs its ser2ice&

T1ere are BC. interrupts (types)+ IT AA% IT

A@%E% IT ,, in t1e FAF.&

91en eecutes an interrupt% microprocessor

automatically sa2es t1e 5ag register% t1e

instruction pointer% and t1e code segmentregister on t1e stac-% and goes to a *edmemory location&

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#lassi*cation I

Interrupts can be broadly categoriGedinto ; groups+

@&'ternal Hardware Interrupts

B&Internal Hardware Interrupts

;&Software Interrupts (IT

instructionEE)

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@&'ternal Hardware Interrupts +Re?uests fromperip1eral de2ices for processor action or attention&

It is due to t1e acti2ity eternal to t1e processor&

B&Internal Hardware Interrupts+ are t1e eceptions%generated internally due to t1e illegal or in2alidoperation inside t1e processor% suc1 as illegal

opcode% address error (illegal memoryreference)%arit1metic error (di2ide by Gero%o2er5ow% etc)&

;&Software Interrupts+ are pseudo interruptspro2iding a mec1anism to implement t1e systemser2ices w1ic1 are accessed using t1e system calls&

T1e source of t1is is t1e program w1ic1 accessest1e system ser2ice by eecuting a system call(e+

IT instruction in FAF.)&

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What is Software interrupts?

T1e Software interrupts are programinstructions& T1ese instructions are insertedat desired locations in a program& 91ilerunning a program% if software interrupt

instruction is encountered t1en t1e processoreecutes an interrupt ser2ice routine&

What is Hardware interrupt?

If an interrupt is initiated in a processor by an

appropriate signal at t1e interrupt pin% t1ent1e interrupt is called Hardware interrupt&

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What is the dierence betweenHardware and Software interrupt?

T1e Software interrupt is initiated byt1e main program% but t1e Hardwareinterrupt is initiated by an eternalde2ice&

#l i* ti II

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#lassi*cation II(!ased On T1e Source Of

Interrupt)@&Hardware InterruptsB&'ception Interrupts;&Software InterruptsT1e interrupts can be again categoriGed asmas-able interrupts and non=mas-ableinterrupts&as-able interrupts can be enabled or disabledusing program instructions suc1 as STI or #TI&

T1e signal on ITR line of FAF. is an eampleof mas-able interrupt&T1e non=mas-able interrupts can ne2er bedisabled& '+ I

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Hardware Interrupts enerated from an eternal signal applied to

I line or ITR input line of FAF.& T1e interrupt on ITR line can be disabled byclearing t1e interrupt 5ag (I,) in t1e 5agregister % i&e&% if t1e I, is cleared #$U does notrespond to t1e signal on t1e ITR line&

#$U 1a2e an instruction to disable t1einterrupts w1en a section of t1e code 1as torun wit1out being disturbed by eternal e2ents&

Hence % most #$Us also 1a2e a special

interrupt called a on= mas-able interrupt(I)%w1ic1 is ser2iced e2en w1en all t1e ot1erinterrupts are disabled&

T1e I is used to signal emergencies suc1 as

memory failure or power failure&

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'ception Interrupt

0 signal from some condition generatedin t1e FAF. by t1e eecution of aninstruction&

'+ Di2ide by Gero interrupt

0n attempt to perform di2ision by Gerowill automatically interrupt t1e

eecution of t1e program& Ot1er eamples+ Di2ide o2er5ow % 0n

illegal memory reference

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Software Interrupts

Treated li-e 1ardware interrupts%ecept t1at t1ey are ne2er disabled&

Use to implement t1e system call orser2ice instead of calling t1eprocessor directly&

'ample + 'ecution of Interrupt

instruction ITEE&

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Interrupt 0ctions

T1e microprocessor c1ec-s to see ifany interrupt 1as been re?uested att1e end of eac1 instruction cycle &

If t1e interrupt signal is sensed andinterrupt 5ag is set or t1e interrupt isI % t1en FAF. performs EE&&

i

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Interrupt 0ctions ,ollowing are t1e actions initiated on t1e occurrence

of an interrupt+

@& Decrements t1e stac- pointer by B and sa2es t1e 5ag registeronto t1e stac-&S$ S$ > B3 S$J 5ags J

B& #lears t1e interrupt 5ag in t1e 5ag register to disable t1e ITRinterrupt& I, AJ

;& #lears t1e trap 5ag in t1e 5ag register to stop generation oft1e single step interrupt& T, AJ

/& Decrement t1e stac- pointer by B and sa2es t1e code segmentregister onto t1e stac-& S$ S$ > B3 S$J #SJ

C& 4oads t1e code segment register wit1 t1e segment address oft1e interrupt ser2ice routine(ISR)S segment of ISR J

.& Decrement t1e stac- pointer by B again and sa2es t1einstruction pointer onto t1e stac-& S$ S$ > B3 S$J I$J

K& 4oads instruction pointer wit1 t1e o6set address of t1einterrupt ser2ice routine in t1e code segment of t1e ISR&I$o6set of ISRJ

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Interrupt

Push FlagsClear IF!FPush C"Push IPFetch I"#

$ddress%C" & ''''()*+,-IP & ''''()*+,2-

P/P IPP/P C"P/P Flags

Interrupt "ervice

Procedure

Push #egisters

Pop #egistersI#0!

I"# 1od

ainline$rogram

I 8ITR8 IT

H D 0 I 9 -:

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How Does 0n Interrupt 9or-:

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T1e LF. family of processors can recogniGeBC. di6erent interrupts&

It reser2es t1e lowest @AB/ bytes ofmemory for a table containing t1eaddresses for eac1 of t1e BC. possibleinterrupts -nown as interrupt 2ector

(pointer)table& emory 0ddresses + AAAAAH to AA;,,H

(IVT)

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Since / bytes are re?uired to storet1e #S and I$ for eac1 ISR % t1e tablecan 1old t1e starting addresses of

BC. interrupt procedures&

T1e address of an ISR stored ininterrupt 2ector table is called as t1einterrupt 2ector or interrupt pointer&

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T1e diagram s1ows t1e organiGation of BC.interrupt pointers in t1e memory table&

'ac1 double word pointer (B byte for I$and B byte for #S) is identi*ed by anumber from A to BCC -nown as typenumber of t1e interrupt i&e& type refersto IT w1ose ISR 2ector is stored atmemory location L /

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91en an interrupt occurs (1ardware% software oreception)% t1e processor multiplies interruptnumber by / and loo-s at t1e resulting memorylocation to *nd t1e address of t1e piece of codew1ic1 1andles t1e interrupt&

T1e processor sa2es t1e 5ag register and t1e current

address (#S%I$) in t1e program onto t1e stac-%disables I,% T, 5ags% and Mumps to t1e beginning oft1e interrupt 1andler&

91en t1e interrupt 1andler completes its eecution%

it in2o-es a special instruction (IR'T) to 1ando2ercontrol to t1e interrupted process% by retrie2ing t1epre2iously sa2ed 5ags and return address from t1estac- and places t1em bac- in t1e appropriateregisters in t1e #$U&

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,ig+ 0n O2er2iew ofser2icing of interrupt by

microprocessor

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#urrentprogram

eecution

Durationof ISR

eecution

'ecutionresumes

1ere

Interruption

$us15ags%return

address

Decode

t1einterrupt

$ointsto IVT

#ontrolreturns

$opreturnaddress and5ags

'ecute ISR

etaddress of ISR

Interruptprocessing

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T1e interrupt 1andler 1as to be careful topreser2e t1e registers used by it&

T1e registers used to communicate t1e

result to t1e program t1at in2o-ed t1einterrupt need not be sa2ed&

If t1e interrupt is triggered by a 1ardwareinterrupt% t1en t1e interrupt 1andler 1as

to preser2e all t1e registers% since registersare not used to communicate t1e result tot1e 1ardware interrupting system&

Interrupt #e3uest 4ines

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Interrupt #e3uest 4inesI#67

T1e microprocessor 1as to 1andle large no& of

tas-s simultaneously and it would beimpossible for it to respond immediately toe2ery interrupt&

T1e $rogrammable Interrupt #ontroller ($I#)

-nown as #$U Receptionist is a special c1ipt1at forms a ?ueue and sends 1ardwareinterrupts to t1e microprocessor one at a time&

'2ery 1ardware de2ice w1ic1 re?uests t1e

processorNs attention t1roug1 an interrupt isassigned wit1 Interrupt Re?uest 4ines (IR)&

It is a direct line to t1e $I# from 1ardwarede2ice&

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FAF. Interrupt Types

@&Di2ide !y Pero Interrupt (Type A)+ 91en t1e?uotient from eit1er a DIV or IDIV instruction is toolarge to *t in t1e result register% FAF. willautomatically eecute type A interrupt&

B&Single Step Interrupt (Type @)+in single stepmode% system will eecute one instruction andstop& 9e can c1ec- t1e contents of registers andmemory locations& If t1ey are correct % we can tell

t1e system to go on and eecute t1e netinstruction&i&e& system will stop after it eecutes eac1instruction and wait for furt1er direction from user&

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FAF. Interrupt Types

;&on as-able Interrupt (Type B)+

T1e FAF. will automatically do a type B interruptresponse w1en it recei2es a low=to=1ig1 transitionon its I input pin&

91en it does a type B interrupt %FAF. will pus1t1e 5ags on t1e stac- % reset T, and I, % and pus1t1e #S 2alue and I$ 2alue for t1e net instructionon t1e stac-&

It will t1en get t1e #S 2alue for t1e start of t1etype B interrupt=ser2ice procedure from addressAAAA0H and t1e I$ 2alue for t1e start of t1eprocedure from address AAAAFH&

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FAF. Interrupt Types/&!rea-point Interrupt (Type ;)+

It is produced by eecution of t1e IT ;instruction&

T1e main use of type ; interrupt is toimplement a brea-point function in a system

Used in debuggingT1e system eecutes t1e instructions up to t1ebrea-point and t1en goes to t1e brea-pointprocedure&

T1e brea-point feature eecutes all t1einstructions upto t1e inserted brea-point andt1en stops eecution&

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C&O2er5ow Interrupt (Type /)

T1e type / interrupt is used to c1ec-o2er5ow condition after any signedarit1metic operation in t1e system&

T1e FAF. o2er5ow 5ag O, will be set ift1e signed result of an arit1meticoperation on B signed no&s is too large

to be represented in t1e destinationregister or memory location&

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Interrupt $riorities

Interrupt Priorit

Di2ide 'rror% IT n%ITO

Hig1est

I

ITR

Single > Step 4owest

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icrocomputer system designre?uires t1at I&O de2ices suc1 as-eyboards% displays% sensors and

ot1er components recei2e ser2icingin a an e

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SQI$

T1e most common met1od of ser2icing suc1 de2ices

is t1e $olled approac1&

T1is is w1ere t1e processor must test eac1 de2ice inse?uence and in e6ect as- eac1 one if it needs

ser2icing& It is easy to see t1at a large portion of t1e main

program is looping t1roug1 t1is continuous pollingcycle and t1at suc1 a met1od would 1a2e a serious

detrimental e6ect on system t1roug1put% t1uslimiting t1e tas-s t1at could

be assumed by t1e microcomputer and reducingt1e cost e6ecti2eness of using suc1 de2ices&

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SQI$

0 more desirable met1od would be one t1at wouldallow t1e microprocessor to be eecuting its mainprogram and only stop to ser2ice perip1eralde2ices w1en it is told to do so by t1e de2ice itself&

In e6ect% t1e met1od would pro2ide an eternalasync1ronous input t1at would inform t1eprocessor t1at it s1ould complete w1ate2erinstruction t1at is currently being eecuted andfetc1 a new routine t1at will ser2ice t1e re?uestingde2ice&

Once t1is ser2icing is complete% 1owe2er% t1eprocessor would resume eactly w1ere it left o6&

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SQI$

T1is met1od is called Interrupt &

It is easy to see t1at systemt1roug1put would drasticallyincrease% and t1us more tas-s couldbe assumed by t1e microcomputer tofurt1er en1ance its cost

e6ecti2eness&

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SQI$

T1e $rogrammable Interrupt #ontroller($I#) functions as an o2erall manager in anInterrupt=Dri2en system en2ironment&

It accepts re?uests from t1e perip1erale?uipment% determines w1ic1 of t1eincoming re?uests is of t1e 1ig1estimportance (priority)% determines w1et1ert1e incoming re?uest 1as a 1ig1er priority2alue t1an t1e le2el currently beingser2iced% and issues an interrupt to t1e#$U based on t1is determination&

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SQI$

'ac1 perip1eral de2ice or structure usually 1as aspecial program or routine t1at is associatedwit1 its speci*c functional or operationalre?uirements3 t1is is referred to as a ser2ice

routine& T1e $I#% after issuing an Interrupt to t1e #$U%

must some1ow input information into t1e #$Ut1at can point t1e $rogram #ounter to t1eser2ice routine associated wit1 t1e re?uestingde2ice& T1is pointer is an address in a2ectoring table and will often be referred

to% in t1is document% as 2ectoring data

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SQI$ T1e FBC0 is a de2ice speci*cally designed for use in

real time% interrupt dri2en microcomputer systems& It manages eig1t le2els or re?uests and 1as built=infeatures for epandability to ot1er FBC0s (up to ./le2els)&

It is programmed by t1e systems software as an I8Operip1eral&

0 selection of priority modes is a2ailable to t1eprogrammer so t1at t1e manner in w1ic1 t1e re?uestsare processed by t1e FBC0 can be con*gured tomatc1 1is system re?uirements&

T1e priority modes can be c1anged or recon*gured

dynamically at any time during t1e main program& T1is means t1at t1e complete interrupt structure can

be de*ned as re?uired% based on t1e total systemen2ironment&

'nd Intel Doc J

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$rogrammable Interrupt#ontroller FBC0

Interrupts can be used for a 2ariety ofapplications&

'ac1 of t1ese interrupt applications re?uires aseparate interrupt input&

If we are wor-ing wit1 FAF.% we get only Binputs ITR and I&

,or applications w1ere we 1a2e multiple

interrupt sources% we use eternal de2icecalled a priority interrupt controller $I#J tofunnel t1e interrupt signals into a singleinterrupt input on t1e processor&

F t /f 8259$

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Features /f 8259$ F le2els of interrupts&

#an be cascaded in master=sla2e con*guration to 1andle

./ le2els of interrupts& Internal priority resol2er&

,ied priority mode and rotating priority mode&

Indi2idually mas-able interrupts&

odes and mas-s can be c1anged dynamically&

0ccepts IR% determines priority% c1ec-s w1et1er incomingpriority current le2el being ser2iced% issues interruptsignal&

In FAFC mode% pro2ides ; byte #044 instruction& In FAF.mode% pro2ides F bit 2ector number&

$olled and 2ectored mode&

Starting address of ISR or 2ector number is programmable&

o cloc- re?uired&

,ig+ Internal !loc- Diagram of

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,ig+ Internal !loc- Diagram ofFBC0

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0rc1itecture Of FBC0

@ I t t R t R i t

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@&Interrupt Re?uest RegisterIRRJ

T1e interrupts at IR input lines are1andled by Interrupt Re?uestRegister internally&

IR stores all t1e interrupt re?uests init in order to ser2e t1em one by oneon t1e priority basis&

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B&In=Ser2ice Register ISRJ

T1is stores all t1e interrupt re?uestst1ose are being ser2ed&

ISR -eeps trac- of t1e re?uests beingser2ed&

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;&$riority Resol2er

T1is unit determines t1e priorities of t1einterrupt re?uests appearing simultaneously&

T1e 1ig1est priority is selected and storedinto t1e corresponding bit of ISR during IT0

pulse& T1e IRA1as t1e 1ig1est priority w1ile t1e IRK

1as t1e lowest one% in *ed priority mode&

T1e priorities may be altered byprogramming t1e FBC0 in rotating prioritymode&

/ I t t - R i t

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/&Interrupt as- RegisterIRJ

T1is register stores t1e bits re?uiredto mas- t1e interrupt inputs&

IR operates on IRR at t1e directionof t1e $riority Resol2er&

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C&Interrupt #ontrol 4ogic

T1is bloc- manages t1e interruptand interrupt ac-nowledge signals tobe sent to t1e #$U for ser2ing one of

t1e F interrupt re?uests& T1is also accepts t1e interrupt

ac-nowledge (IT0) signal from #$U

t1at causes t1e FBC0 to release2ector address on to t1e data bus&

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.&Data !us !u6er

T1is tristate bidirectional bu6erinterfaces internal FBC0 bus to t1emicroprocessor system data bus&

#ontrol words% status and 2ectorinformation pass t1roug1 data bu6erduring read or write operations&

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K&Read 8 9rite #ontrol 4ogic

T1is circuit accepts and decodescommands from t1e #$U&

T1is bloc- also allows t1e status oft1e FBC0 to be transferred on to t1edata bus&

F #ascade !u6er 8

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Fascade !u6er 8#omparator T1is bloc- stores and compares t1e IDs of

all t1e FBC0s used in t1e system& ; I 8O pins #0S A=B are outputs w1en t1e

FBC0 is used as a master&

T1e same pins act as inputs w1en t1eFBC0 is in sla2e mode&

T1e FBC0 in master mode sends t1e ID oft1e interrupting sla2e de2ice on t1esepins&

T1e sla2e t1us selected% will send itspreprogrammed 2ector address on t1e

data bus during t1e net IT0 pulse&

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$in Diagram Of FBCinimum ode

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,unctional Description Of

FBC Signals

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@& #S+ T1is is an acti2e low c1ip selectsignal for enabling RD and 9Roperations of FBC0& IT0 function isindependent of #S&

B& 9R + T1is pin is an acti2e=low writeenable input to FBC0& T1is enables it toaccept command words from #$U&

;& RD+ T1is is an acti2e > low read enableinput to FBC0& 0 low on t1is lineenables FBC0 to release status ontot1e data bus of #$U&

/ D D + T1ese pins form a bidirectional

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/& DK> DA+ T1ese pins form a bidirectional

data bus t1at carries F=bit data eit1er tocontrol word or from status word registers&T1is also carries interrupt 2ectorinformation&

C& #0SA > #0SB #ascade 4ines+ 0 singleFBC0 pro2ides F 2ectored interrupts& Ifmore interrupts are re?uired % t1e FBC0 isused in cascade mode& In cascade mode% amaster FBC0 along wit1 F sla2es FBC0can pro2ide up to ./ 2ectored interruptlines& T1ese ; lines act as select lines for

addressing t1e sla2es FBC0&

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.&S$ 8 '

Sla2e $rogram 8 'nable !u6er

Dual purpose pin

91en t1e c1ip is used in bu6eredmode% it can be used as an output tocontrol bu6er transrecei2ers (')&

If not in bu6ered mode it is used as

input to designate w1et1er t1e c1ip isused as+

a master (S$W @) or a sla2e (' W A)&

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K&IT

T1is pin goes 1ig1 w1ene2er a 2alidinterrupt re?uest is asserted&

T1is is used to interrupt t1e #$U andis connected to t1e interrupt input of#$U&

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F&IRA> IRK

Interrupt Re?uests

T1ese pins act as inputs to acceptinterrupt re?uests to t1e #$U&

In edge triggered mode% an interruptser2ice is re?uested by raising an IRpin from a low to a 1ig1 state and

1olding it 1ig1 until it is ac-nowledged%Must by latc1ing it to 1ig1 le2el% if usedin le2el triggered mode&

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&IT0

Interrupt 0c-nowledge

T1is pin is an input used to strobe >in FBC0 interrupt 2ector data on to

t1e data bus&

In conMunction wit1 #S % 9R % andRD pins % t1is selects t1e di6erent

operations li-e% writing commandwords% reading status words&

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@A& 0A0DDR'SS 4I'

T1is pin acts in conMunction wit1 t1e#S% 9R% and RD pins&

It is used by t1e FBC0 to decip1er

2arious #ommand 9ords t1e #$Uwrites and status t1e #$U wis1es toread&

It is typically connected to t1e #$U0A address line (0@ for FAF.% FAFF)&

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FBC0 $in Description

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Interfacing Tec1ni?ue

'it1er $olling Or Interrupt Dri2en

Interrupt Se?uence In FAF.

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Interrupt Se?uence In FAF.T1e interrupt se?uence in an FAF. > FBC0 system is described

as follows+

@& One or more IR lines are raised 1ig1 t1at set correspondingIRR bits&

B& FBC0 resol2es priority and sends an IT signal to #$U&

;&T1e #$U ac-nowledges wit1 IT0 pulse&

/& Upon recei2ing an IT0 signal from t1e #$U% t1e 1ig1estpriority ISR bit is set and t1e corresponding IRR bit is reset&

T1e FBC0 does not dri2e data bus during t1is period&

C&T1e FAF. will initiate a second IT0 pulse& During t1isperiod FBC0 releases an F=bit pointer on to data bus from

w1ere it is read by t1e #$U&.&T1is completes t1e interrupt cycle& T1e ISR bit is reset at t1e

end of t1e second IT0 pulse if automatic end of interrupt(0'OI) mode is programmed& Ot1erwise ISR bit remains setuntil an appropriate 'OI command is issued at t1e end of

interrupt subroutine&

,ig+FBC0 #onnected To 0n FAF.

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g

0DA

0DA

0DK

ITR

IT0

DA

DKIT0

IRA

IRKIT

InterruptInput

FAF. FBC0

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FBC0 O2er2iew " System

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FBC0 O2er2iew " System#onnections

If FAF. interrupt 5ag is set and t1e ITR input recei2es a

1ig1 signal % t1e FAF. will@&Send out two interrupt ac-nowledge pulses on its IT0

pin to t1e IT0 pin of FBC0 $I#& T1e IT0 pulses tellt1e FBC0 to send t1e desired interrupt type to t1eFAF. on t1e data bus&

B&ultiply t1e interrupt type it recei2es from t1e FBC0by / to produce an address in t1e interrupt 2ectortable&

;&$us1 t1e 5ags on t1e stac-&/lear I, and T,&C&$us1 t1e return address on t1e stac-&.&et t1e starting address for t1e interrupt procedure

from t1e interrupt=2ector table and load t1at address in#S and I$&

K&'ecute t1e interrupt > ser2ice procedure&

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F=bit data bus allows t1e FAF. to sendcontrol word to t1e FBC0 and read astatus word from t1e FBC0&T1e RD

and 9R inputs control t1ese transfersw1en t1e de2ice is selected by assertingits c1ip select (#S) input low&

T1e F=bit data bus also allows t1e FBC0to send interrupt types to t1e FAF.&

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'ig1t interrupt inputs labeled IRA t1roug1IRK &

If FBC0 is properly enabled% an interrupt

signal applied to any one of t1ese inputswill cause t1e FBC0 to assert its IToutput pin 1ig1&

If t1is pin is connected to t1e ITR pin of an

FAF. and if t1e FAF. interrupt 5ag is set %t1en t1e 1ig1 signal will cause t1e ITRresponse&

$ROR0I TH' FBC0

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$ROR0I TH' FBC0

T1e FBC0 accepts two types ofcommand words generated by t1e #$U+

@& InitialiGation #ommand 9ords (I#9s)B& Operation #ommand 9ords (O#9s)

@ InitialiGation #ommand 9ords (I#9s)+ !efore

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@& InitialiGation #ommand 9ords (I#9s)+ !eforenormal operation can begin% eac1 FBC0 in t1esystem must be broug1t to a starting point =by a

se?uence of B to / bytes timed by 9R pulses&B& Operation #ommand 9ords (O#9s)+ T1ese aret1e command words w1ic1 command t1e FBC0 tooperate in 2arious interrupt modes& T1ese modes

are+a& ,ully nested mode

b& Rotating priority mode

c& Special mas- mode

d& $olled modeT1e O#9s can be written into t1e FBC0 anytime

after initialiGation&

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#ommand 9ords Of FBC0

T1e command words of FBC0 areclassi*ed in B groups+

@&InitialiGation command words I#9sJ

B&Operation command words O#9sJ

I#9sJ

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I#9sJ !efore it starts functioning% t1e FBC0 must

be initialiGed by writing two to four commandwords into t1e respecti2e commandregisters&

T1ese are called as initialiGation commandwords I#9sJ&

If 0AW A and D/W @% t1e control word is

recogniGed as I#9@&

ICW1contains the control bits for edge / level

triggered mode, single / cascade mode, calladdress interval and whether ICWis

re!uired or not, etc"

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If 0AW @% t1e control word isrecogniGed as I#9B&

#he ICW$stores details regarding

interrupt vector addresses"

T1e initialiGation se?uence of FBC0is described in t1e form of 5ow c1artin net slide&

,ig+ InitialiGation Se?uence Of

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g ?FBC0

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aster8Sla2e in I#9/ is only used int1e bu6ered mode&

Level Triggered Mode Vs Edge

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Level Triggered Mode Vs. EdgeTriggered Mode

In le2el triggered mode% ser2ice willbe re?uested w1ene2er a 1ig1 le2elis present on an IR input&

In edge=triggered mode% a signal onan IR input must go from low to 1ig1

and stay 1ig1 until ser2iced&

Fig: Initialization Command Word ICW1

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' $ $ $5 :4!I;

$DI"*

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InitialiGation Se?uence Once I#9@ is loaded % t1e following

initialiGation procedure is carried outinternally+

a)T1e edge sense circuit is reset% i&e& by defaultFBC0 interrupts are edge sensiti2e&

b)IR is cleared&c)IRK input is assigned t1e lowest priority&

d)Sla2e mode address is set to K&

e)Special mas- mode is cleared and status readis set to IRR&

f) f) If I#/W A % all t1e functions of I#9/ are set toGero& aster 8 sla2e bit in I#9/is used in t1e

bu6ered mode only&

I#9

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I#9B

In FAF. based system 0@C= 0@@of t1einterrupt 2ector address are insertedin place of TK= T;respecti2ely&

T1e remaining ; bits (0F%0T% 0@A) are

selected depending upon t1e

interrupt le2el% i&e& from AAA to @@@for IRAto IRK&

Fig: Initialization Command Word ICW2

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g

: ! ! !5 !, != $:'

$9 $8

A0 D7 D6 D5 D4 D3 D2 D1 D0

ICW2

"n 808+/88 $ased system A15 A11of t,e interrupt vector

address inserted in place of T7 T3 respectively and t,e

remainin - $itsA8 A10

A10 A9 A8 !"l"#t"d a##ording to int"rr$%t r"&$"'t l"("l)T*"+ ar" not t*" addr"'' lin"' o, -i#ro%ro#"''or

A0 .1 '"l"#t' ICW2

% t

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%ote

#ompulsory command words ininitialiGation se?uence of FBC0 +

I#9@and I#9B

Optional command words +

I#9; and I#9/

I#9

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I#9;

I#9;is read only w1en t1ere are moret1an one FBC0s is in t1e system % i &e &cascading is used (S4 W A)&

T1e S4 bit in I#9@ indicates w1et1ert1e FBC0 is in cascade mode or not&

T1e I#9;loads an F=bit sla2e register&

I#9 I t d

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I#9; In aster ode

In master mode i&e& S$ W @ or inbu6er mode 8 S W @ in I#9/J% t1eF=bit sla2e register will be set bit=wise

to X@N for eac1 sla2e in t1e system&

T1e re?uesting sla2e will t1en release

t1e second byte of a #044 se?uencereleased by it on t1e Data !us &

-a't"r mod" ICW3

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: " " "5 ", "= "2 ": "'

: ' ' ' ' ' ID2 ID: ID'

A0 D7 D6 D5 D4 D3 D2 D1 D0

A0 D7 D6 D5 D4 D3 D2 D1 D0

-a't"r mod" ICW3

!n . 1 // In In%$t *a' a 'la("

. 0 In In%$t do"' not *a(" a

'la("

!la(" mod" ICW3

D2D1D0 000 to 111 ,or I0to I7or 'la(" 1 to 'la(" 8

Fig: ICW3 in -a't"r !la(" -od"

I#9 In Sla2e ode

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I#9; In Sla2e ode

In sla2e mode S$ W A or if !U, W @and 8S W A in I#9/J bits DBto DAidentify t1e sla2e% i&e& AAA to @@@ for

sla2e @ to sla2e F&

T1e sla2e compares t1e cascade inputs

wit1 t1ese bits and if t1ey are e?ual%t1e second byte of t1e #044 se?uenceis released by it on t1e data bus&

I#9

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I#9/

T1e use of t1is command worddepends on t1e I#/bit of I#9@&

If I#/W@% I#9/is used% ot1erwise it is

neglected&

IC@ @ 0uto 'OI ode

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A0 D7 D6 D5 D4 D3 D2 D1 D0

: ' ' ' "F*;

1UF ;>" $0/I

?P;

IC@,

,ig+ I#9/ !it ,unctions

@W

Special ,ully ested ode

AW

ot Special ,ully estedode

@W

FAF. 8 FAFFode

AW

#S > FA 8 FCode

A on !u6ered ode

@ A !u6ered ode 8Sla2e

@ @ !u6ered ode 8

aster

W

AW

ormal 'OIode

I#9/

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T1e bit functions of I#9/ +

@&S,+"pecial fully nested mode is selected&

If !U, W @% t1e bu6ered mode is selected&

In t1e bu6ered mode% S$8' acts as enableoutput and t1e master8sla2e is determinedusing t1e 8S bit of I#9/&

B& 8S+

If 8S W @% FBC0 is a master&If 8S WA% FBC0 is sla2e&

If !U, W A% 8S is to be neglected&

# /

I#9

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;& 0'OI+ If 0'OI W @% t1e automatic end of

interrupt mode is selected&

/&Y$ + If t1e Y$ bit is A% t1e #S=FC system

operation is selected& If Y$W@% FAF.8FF operation is

selected&

I#9/

/peration Command

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p@ords

Once FBC0 is initialiGed using t1e commandwords for initialiGation % it is ready for its normalfunction

T1e c1ip FBC0 is ready to accept interrupt

re?uests at its input lines& FBC0 1as its own way of 1andling t1e recei2ed

interrupts called as modes of operation&

T1ese modes of operations can be selected byprogramming&

9riting ; internal registers called asoperation command word registers&

O#9s

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O#9s T1e data written into t1e operation

command word registers (bit pattern) iscalled as operational command words&

In t1e t1ree operation command wordsO#9@% O#9Band O#9;% e2ery bit

corresponds to some operationalfeature of t1e mode selected% eceptfor a few bits t1ose are eit1er @ or A&

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,ig+ Operation #ommand

9ords

O#9

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: ; ; ;5 ;, ;= ;2 ;: ;'

A0 )7 )+ )5 )# )- ). )1 )0

1 -a' !"t

0 -a' "'"t

se To mas t,e un2anted interrupt re3uests4

"f t,e mas $it is 0 t,e correspondin interrupt re3uest isena$led

1 t,e re3uest is disa$led4

O#9@

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O#9@sets and clears t1e mas-bits in t1e Interrupt as-Register (IR)&

O#9

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O#9B

In O#9Bt1e ; bits% R% S4 and 'OI controlt1e end of interrupt% t1e rotate mode andt1eir combinations&

T1e t1ree bits 4B% 4@ and 4A in O#9Bdetermine t1e interrupt le2el to be selectedfor operation% if S4 bit is acti2e i&e& @&

Used to reset a bit in t1e in=ser2ice register&

CW2A ) ) ) ) ) ) ) )

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A0 )7)+ )5 )# )- ). )1 )0

' ' : *onA"peciBc 0/I C/;;$*D

' : : "P0CIFIC 0/I C/;;$*D

: ' : #/!$!0 /* */*"P0CIFIC 0/IC/;;$*D

: ' ' #/!$!0 I* $U!/;$!IC 0/I ;/D0)"0!-

' ' ' #/!$!0 I* $U!/;$!IC 0/I )C40$#-

: : : #/!$!0 /* "P0CIFIC 0/I C/;;$*D

: : ' "0! P#I/#I! C/;;$*D+

' : : */ /P0#$!I/*

: # "

4

0

/I

' ' 42 4: 4'

' : 2 = , 5

A @ A @ A @ A @A A @ @ A A @ @

A A A A @ @ @ @

I )

/ In t*i' -od" 0 2 ar" $'"d

O#9

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O#9;

In operation command word ; (O#9;)% ift1e 'S bit% i&e& enable special mas-mode bit is set to @% t1e S bit is enabledto select or mas- t1e special mas- mode&

91en 'S bit is A t1e S bit isneglected&

If t1e S bit% i&e& special mas- mode bit

is @% t1e FBC0 will enter special mas-mode pro2ided 'SW@&

O#9

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O#9;

'S + 'nable Special as- ode&91en 'S W@ it enables t1e Sbit to set or reset t1e Special as-

ode&91en 'S W A t1e S bit becomesa Zdont care[ &

O#9

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O#9;

S+ Special as- ode If 'S W @ and S W @ t1e FBC0

will enter Special as- ode&

If 'S W @ and S W A t1e FBC0will re2ert to normal mas- mode&

91en 'S W A% S 1as no e6ect&

9;

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' ' 0";;

";; ' : P ## #I"A0 )7 )+ )5 )# )- ). )1 )0

*o $ction ' '' :

#eset "pecial;as

: '

"et "pecial;as

: :

A A o0ctionA @

@ A Read IRR onnet RD pulse

@ @ Read ISR onnet RD pulse

1 6oll

Command

0 (o 6oll

Command

O#9

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O#9;

7 If 'SW@ and SWA% t1e FBC0will return to t1e normal mas- mode&

Operating odes of FBC

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Operating odes of FBC

T1e di6erent modes of operation ofFBC0 can be programmed by

setting or resting t1e appropriate bitsof t1e I#9 or O#9&

T1e di6erent modes of

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operation of FBC0@&,ully ested ode

B&'nd ofInterrupt ('OI)

;& 0utomaticRotation

/&0utomatic 'OIode

C&Speci*c

Rotation

.&Speci*c as- ode

K&'dge " 4e2el TriggeredodeF&Reading FBC Status

&$oll #ommand

@A&Special ,ully estedode

@@&!u6ered ode

@Bascade ode

: Full *ested ;ode

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:.Full *ested ;ode

Default mode of operation of FBC0 T1is mode is entered after initialiGation unless

anot1er mode is programmed&

IRA1as t1e 1ig1est priority and IRK1as t1e

lowest&

91en interrupt re?uests are noticed% t1e 1ig1estpriority re?uest amongst t1em is determinedand t1e 2ector is placed on t1e data bus&

T1e corresponding bit of ISR is set and remainsset till t1e microprocessor issues an 'OIcommand Must before returning from t1e ser2iceroutine or t1e 0'OI bit is set&

: Full *ested ;ode

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:.Full *ested ;ode

If t1e ISR (in ser2ice) bit is set% all t1esame or lower priority interrupts arein1ibited but 1ig1er le2els will generate

an interrupt% t1at will be ac-nowledgeonly if t1e microprocessor interruptenable 5ag I, is set&

T1e priorities can afterwards bec1anged by programming t1e rotatingpriority modes&

2 0nd of Interrupt 0/I7

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2.0nd of Interrupt 0/I7

T1e ISR bit can be reset eit1er wit1 0'OI bitof I#9/or by 'OI command% issued beforereturning from t1e interrupt ser2ice routine&

T1ere are two types of 'OI commandsspeci&cand non'speci&c&

91en FBC0 is operated in t1e modes t1atpreser2e fully nested structure% it can

determine w1ic1 ISR bit is to be reset on 'OI& 91en non=speci*c 'OI command is issued toFBC0 it will be automatically reset t1e1ig1est ISR bit out of t1ose already set&

2 0nd of Interrupt 0/I7

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2.0nd of Interrupt 0/I7

91en a mode t1at may disturb t1e fullynested structure is used% t1e FBC0 is nolonger able to determine t1e last le2elac-nowledged&

In t1is case a speci*c 'OI command isissued to reset a particular ISR bit&

0n ISR bit t1at is mas-ed by t1e

corresponding IR bit% will not be clearedby non=speci*c 'OI of FBC0% if it is inspecial mas- mode&

= $utomatic #otation

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=.$utomatic #otation

T1is is used in t1e applications w1ere allt1e interrupting de2ices are of e?ualpriority&

In t1is mode% an interrupt re?uest IR le2elrecei2es lowest priority after it is ser2edw1ile t1e net de2ice to be ser2ed getst1e 1ig1est priority in se?uence&

Once all t1e de2ice are ser2ed li-e t1is%t1e *rst de2ice again recei2es 1ig1estpriority&

, $utomatic 0/I ;ode

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,.$utomatic 0/I ;ode

Till 0'OIW@ in I#9/% t1e FBC0operates in 0'OI mode&

In t1is mode% t1e FBC0 performs a

non=speci*c 'OI operation at t1etrailing edge of t1e last IT0 pulseautomatically&

T1is mode s1ould be used only w1en anested multile2el interrupt structure isnot re?uired wit1 a single FBC0&

5 "peciBc #otation

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5."peciBc #otation

In t1is mode a bottom priority le2elcan be selected% using 4B% 4@ and 4Ain O#9B and RW@% S4W@% 'OIWA&

T1e selected bottom priority *esot1er priorities&

5 "peciBc #otation

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5."peciBc #otation

If IRC is selected as a bottom priority%t1en IRC will 1a2e least priority andIR/ will 1a2e a net 1ig1er priority&

T1us IR. will 1a2e t1e 1ig1est priority& T1ese priorities can be c1anged

during an 'OI command by

programming t1e rotate on speci*c'OI command in O#9B&

"peciBc ;as ;ode

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."peciBc ;as ;ode

In speci*c mas- mode% w1en a mas-bit is set in O#9@% it in1ibits furt1er

interrupts at t1at le2el and enablesinterrupt from ot1er le2els% w1ic1 arenot mas-ed&

.0dge and 4evel

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!riggered ;ode

T1is mode decides w1et1er t1einterrupt s1ould be edge triggered or

le2el triggered& If bit 4TI of I#9@WA t1ey are edge

triggered% ot1erwise t1e interrupts

are le2el triggered&

8.#eading 8259 "tatus

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8.#eading 8259 "tatus

T1e status of t1e internal registers ofFBC0 can be read using t1is mode&

T1e O#9;is used to read IRR and ISRw1ile O#9@ is used to read IR&

Reading is possible only in no polled

mode&

9.Poll Command In polled mode of operation% t1e IT output of

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In polled mode of operation% t1e IT output ofFBC0 is neglected% t1oug1 it functions

normally% by not connecting IT output or bymas-ing IT input of t1e microprocessor&

T1e poll mode is entered by setting $W@ inO#9;&

T1e FBC0 is polled by using softwareeecution by microprocessor instead of t1ere?uests on IT input&

T1e FBC0 treats t1e net RD pulse to t1eFBC0 as an interrupt ac-nowledge&I E E E E @2 @: @'

)7 )+ )5 )# )- ). )1 )0

"f & 1 t,ere is an

interrupt

inary code

of ,i,est

priority level

Fig: data Word , 8259

9.Poll Command

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9.Poll Command

0n appropriate ISR bit is set% if t1ere is are?uest&

T1e priority le2el is read and a data word isplaced on to data bus% after RD isacti2ated&

0 poll command may gi2e more t1an ./priority le2els&

T1is 1as not1ing to do wit1 t1e FAF.interrupt structure and t1e interruptpriorities&J

:'."pecial Full *ested; d

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;ode T1is mode is used in more complicated system%

w1ere cascading is used and t1e priority 1as tobe programmed in t1e master using I#9/&

T1is is somew1at similar to t1e normal nested

mode& In t1is mode% w1en an interrupt re?uest from a

certain sla2e is in ser2ice% t1is sla2e canfurt1er send re?uest to t1e master% if t1e

re?uesting de2ice connected to t1e sla2e 1as1ig1er priority t1an t1e one being currentlyser2ed&

:'."pecial Full *ested; d

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;ode

In t1is mode% t1e master interrupt t1e#$U only w1en t1e interrupting de2ice1as a 1ig1er or t1e same priority t1an t1eone current being ser2ed&

In normal mode% ot1er re?uests t1an t1eone being ser2ed are mas-ed out&

91en entering t1e interrupt ser2ice

routine t1e software 1as to c1ec- w1et1ert1is is t1e only re?uest from t1e sla2e&

:'."pecial Full *ested; d

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;ode

T1is is done by sending a non=speci*c'OI can be sent to t1e master%ot1erwise no 'OI s1ould be sent&

T1is mode is important% since in t1eabsence of t1is mode% t1e sla2ewould interrupt t1e master only once

and 1ence t1e priorities of t1e sla2einputs would 1a2e been disturbed&

::.1uered ;ode

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::.1uered ;ode

91en t1e F;BC0 is used in t1esystems w1ere bus dri2ing bu6ers

are used on data buses& T1e problem of enabling t1e bu6ers

eists& T1e FBC0 sends bu6er

enable signal on S$8 ' pin%w1ene2er data is placed on t1e bus&

:2.Cascade ;ode

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:2.Cascade ;ode T1e FBC0 can be connected in a system

containing one master and eig1t sla2es(maimum) to 1andle up to ./ priority le2els&

T1e master controls t1e sla2es using #0SA=#0SB w1ic1 act as c1ip select inputs(encoded) for sla2es&

In t1is mode% t1e sla2e IT outputs areconnected wit1 master IR inputs&

91en a sla2e re?uest line is acti2ated andac-nowledged% t1e master will enable t1esla2e to release t1e 2ector address duringsecond pulse of IT0 se?uence&

:2.Cascade ;ode

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:2.Cascade ;ode

T1e cascade lines are normally low and containsla2e address codes from t1e trailing edge oft1e *rst IT0 pulse to t1e trailing edge of t1esecond IT0 pulse&

'ac1 FBC0 in t1e system must be separatelyinitialiGed and programmed to wor- in di6erentmodes&

T1e 'OI command must be issued twice% one for

master and t1e ot1er for t1e sla2e& 0 separate address decoder is used to acti2ate

t1e c1ip select line of eac1 FBC0&

,ollowing ,ig s1ows t1e details of t1e circuitconnections of FBC0 in cascade sc1eme&

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IT'RRU$T S'U'#'OUT$UTS

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OUT$UTS

#S=FA% #S=FCT1is se?uence is timed by t1ree IT0pulses&

During t1e *rst IT0 pulse t1e #044opcode is enabled onto t1e data bus&

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During t1e second IT0 pulse t1e loweraddress of t1e appropriate ser2ice routineis enabled onto t1e data bus&

91en Inter2al W /% bits 0C=0K areprogrammed% w1ile 0A= 0/ areautomatically inserted by t1e FBC0&

91en Inter2al W F only 0. and 0K areprogrammed% w1ile 0A=0C areautomatically inserted

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FAF.% FAFF

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FAF. mode is similar to #S=FA mode

ecept t1at only two Interrupt 0c-nowledgecycles are issued by t1e processor and no#044 opcode is sent to t1e processor&

T1e *rst interrupt ac-nowledge cycle issimilar to t1at of #S=FA% FC systems int1at t1e FBC0 uses it to internally freeGe

t1e state of t1e interrupts for priorityresolution and as a master it issues t1einterrupt code on t1e cascade lines at t1eend of t1e IT0 pulse&

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On t1is *rst cycle it does not issue anydata to t1e processor and lea2es its databus bu6ers disabled&

On t1e second interrupt ac-nowledgecycle in FAF. mode t1e master (or sla2e ifso programmed) will send a byte of datato t1e processor wit1 t1e ac-nowledged

interrupt code composed as follows(note t1e state of t1e 0DI mode control is

ignored and 0C = 0@@ are unused in FAF.

mode

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Interfacing " $rogrammingFBC

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FBC

$roblem+ S1ow FBC0 interfacing connectionswit1 FAF. at t1e address AK/& 9rite an 04$to initialiGe t1e FBC0 in single le2eltriggered mode% wit1 call address inter2al of/% non=bu6ered% no special fully nestedmode& T1en set t1e FBC0 to operate wit1IR. mas-ed%IR/ as bottom priority le2el% wit1

special 'OI modes& Set special mas- modeof FBC0& Read IRR and ISR into registers !Hand !4 respecti2ely&

Solution+ 4et t1e starting 2ector address isAAAA+AA@A& T1e interconnections of FBC0

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wit1 FAF. are s1own in *g below+

$' D D D5 D, D= D2 D: D'

A A A A @ @ @ @ @

Al2ays don*t care for al2aysset to 0 808+ system set to 1

"C'# needed

!ingl" 8259A

Call addr"''

int"r(al o, 4

"("l

trigg"r"d

mod"

"C'1 & 1

T,e 808+ is interfaced 2it, lo2er

$yte of t,e 808+ data $us ,ence A0line of t,e microprocessor is

a$andoned and A1of t,e

microprocessor is connected 2it,

A0 of t,e 8.59A

! ! !5 !, != $:' $9 $8

"C'. vector address & 00000010 for ":-

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@ A A A A A @ @& 8- ;

":- %elected

T,ere is no slave ,ence t,e "C'- is as iven $elo2

$' D D D5 D, D= D2 D: D'

@ A A A A A A A A "C'-& 0 0;

A#t$all+ ICW3 i' not at all n""d"d "#a$'" in ICW1 t*" 8259A i' '"t ,or 'ingl"

mod")

T*" ICW4 '*o$ld " '"t a' '*on "lo:

$' D D D5 D, D= D2 D: D'@ A A A A A A A @ "C'#& 0 1;

or 808+ system

(ormal !

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":+ mased

T,e

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$' D D D5 D, D= D2 D: D'

A A @ @ A @ A @ A :ead "::

(o 6oll%pecial

mas mode

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p g y

Refer $dvanced ;"D/"Programming 1 #a Dunanpage o& / to page o& /C

DOS 0n OS t1at pro2ides general de2ice=independent

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0n OS t1at pro2ides general% de2ice independentaccess to t1e resources of a computer&

De2ices+ -eyboards% screens% dis- dri2ers

De2ice independent+ no need to address de2icesspeci*cally% since DOS " its de2ice dri2ers can

1andle t1e operation at t1e de2ice le2el& DOS ,unctions+

@&,ile anagement

B&Input 8 Output

;&$rogram 4oading

/&emory anagement

C&Interrupt Handling

T1e Structure Of S=DOS

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S > DOS is partitioned into se2erallayers t1at ser2e to isolate t1e -ernellogic of OS% and t1e userNs perception oft1e system% from 1ardware it is runningon&

T1ese layers are+

@&T1e !IOS (!asic Input 8 Output System)

B&T1e DOS -ernel

;&T1e command processor (S1ell)

T1e !IOS odule

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Speci*c to indi2idual computer system

Is pro2ided by t1e manufacturer of t1esystem&

It contains default resident 1ardware

dependent dri2ers for t1e following de2ices+@onsole display and -eyboard (#O)

B&4ine printer ($R)

;&0uiliary de2ice (0U)/&Date and time (#4O#Q\)

C&!oot dis- de2ice (!loc- de2ice)

!IOS odule

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S=DOS -ernel communicates wit1 t1ese

de2ice dri2ers t1roug1 I8O re?uest pac-ets T1en translate t1e dri2ers t1ese re?uests into

proper commands for t1e 2arious 1ardwarecontrollers&

ost primiti2e parts of 1ardware dri2ers arelocated in RO so t1at t1ey can be used bystand=alone applications %diagnostics % and t1e

system startup programs& Resident dri2ers + dri2ers built into !IOS

Installable dri2ers+ installed during systeminitialiGation by D'VI#' command in

OrganiGation Of DOS / maMor components

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1" I("S)S+

a& $erforms initialiGation functions at boot up timeb& #ontains de2ice dri2ers t1at supplement t1e primiti2e I8O

support in RO !IOS&

c& Store on a dis- as a 1idden system *le

$" *S+(S"S)S+a& 0cts as DOS -ernel

b& #oncern wit1 *le management% memory management% andinput8output&

" C(**-%+"C(*+

a& 0 command processor or s1ellb& Interface between user and OS

c& Displays DOS prompt% monitors t1e -eyboard and processesuser commands

/ !oot Sector

ap Of #on2entionalemory

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emory

C/;;$*D.C/; transient portioneGecuting programs ma erase it7

02ailable for programsN use

#O0DO resident portion (resides permanently )

System *les IO&S]S and SDOS&S]S

!IOS data area

Interrupt ser2ice table0=

+#0=

DOS > !IOS Interface

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!IOS contains a set of routines in RO topro2ide de2ice support&

!IOS tests and initialiGes attac1ed

de2ices and pro2ides ser2ices t1at areused for reading to and for writing fromt1e de2ices&

DOS > !IOS Interface

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User $rograms

Hardware 8 De2ices

DOS

!IOS

System $rogram 4oader DOS supports B types of eecutable

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pp ypprograms+

@) O

B) &''

0 O program consists of one segment

t1at contains code% data and t1e stac-& asiGe ./Q

0n &'' program may be 2irtually any siGe

and it consists of separate code% data andstac- segments and C@B=byte 1eaderpresent

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0 O program is an absoluteimage of t1e eecutable program%

but wit1 relocatable addressinformation&

Segments Stac-+ eed to de*ne an &'' program wit1 a

t - t 1 #O

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stac- segment% w1ereas a O program

automatically generates a stac-& Data + 0n &'' program usually de*nes a datasegment and initialiGes t1e DS register wit1 t1eaddress of t1at segment& Since t1e data for a

O program is de*ned wit1in t1e codesegment% no need to de*ne t1e data segmenteit1er&

#ode +0n eit1er O program combines t1e

$S$% stac- % data segment% and code segmentinto one code segment % in a maimum of ./Qbytes&

InitialiGation 91en DOS loads a #O program for eecution

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91en DOS loads a O program for eecution %it automatically initialiGes all segment registers

wit1 t1e address of $S$& Since t1e #S and DSregisters will contain t1e correct initial segmentaddress% t1e user program does not 1a2e to loadt1em&

!ecause addressing begins at an o6set of @AAHbytes from t1e beginning of t1e $S$% code anOR directi2e as OR @AAH immediatelyfollowing t1e code S''T or OD' statement&

T1e OR directi2e tells t1e assembler to begingenerating t1e obMect code at an o6set of @AAHbytes past t1e start of t1e $S$% w1ere t1eactual O program begins&

91at Is $rogram Segment $re*

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DOS loads O and &'' programs foreecution into a program segment andcreates a $S$ at o6set AAH and t1e programitself at o6set @AAH of t1e segment&

'' H ': $n I*! 2' instruction CD2'7 to facilitate the return to D/"

'2 H '= !he segment address of the last paragraph of memor allocatedto the program as GGGG'. For eG( ,'J is indicated as ''$'meaning $'''')'-

', '9 #eserved K D/"

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', H '9 #eserved K D/"

'$ H 'D !erminate address segment address for I*! 227

'0 H :: Ctrl 1rea eGit address segment address for I*! 2=7

:2 H :5 Critical error eGit address segment address for I*! 2,7

: H : #eserved K D/"

:8 H 21 Default File andle !aKle

2C H 2D "egment address of programLs environment

20 H =: #eserved K D/"

=2 H == 4ength of the File andle !aKle

=, H = Far Pointer to the handle taKle

=8 H ,F #eserved K D/"

5' H 5: Call to D/" function I*! 2: and #0!F752 H 51 #eserved K D/"

5C H 1 Parameter area : formatted as a standard unopened FC1 M:7

C H F Parameter area 2 formatted as a standard unopened FC1 M27%overlaid if the FC1 at 5C is opened

8' H FF 1uer for a default D!$ Command line string7

Stac- grows downward from topof segment

!!:!

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$rogram code and data

$rogram segment pre*C!:0100

C% 0000;

)%0000;

!%0000;%%0000; ,ig+ 0 emory Image of atypical O > type program

after loading

Stac- segment 3 stac- growsdownward from top of segment

!!:!

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Data segment

$rogram code

$rogram segment pre*C!:0100

)%0000;

!%0000;

%%0000;

,ig+ 0 emory Image of atypical &'' > type programimmediately after loading

,ile Handles

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0 *le 1andle is simply a number t1at refers toa speci*c de2ice&

DOS deli2ers a *le 1andle w1en you open a*le for input or create a *le for output&

T1e operation in2ol2es t1e use of an 0S#IIPstring and DOS function ;#H or ;DH&

T1e *le 1andle is a uni?ue one=word number

returned in t1e 0 t1at we sa2e in a word dataitem and use for all subse?uent re?uests toaccess *le&

>Table

'ac1 byte in t1e BA=byte default *le 1andle tablerefers to an entry in a DOS table t1at de*nes t1e

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refers to an entry in a DOS table t1at de*nes t1erelated de2ice or dri2er&

Initially% t1e table contains A@A@A@AAAB,,E,,%w1ere t1e *rst A@ refers to t1e -eyboard% t1esecond A@ to t1e screen% and so on&

T1e table of BA 1andles so DOS allows a

maimum of BA *les open at one time&

!$140 D0NIC0 $*D40 D0NIC0

': Console ' JeKoard "tandardinput7

': Console : JeKoard standardoutput7

': Console 2 "creen standard error7

'' C/;:"erialport7

= $uGiliar

$S$ FA > ,,H + Default DT0 !u6er

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T1is portion of $S$ is called a default bu6er fort1e DT0

0S#IIP Strings Tell DOS t1e address of an 0S#IIP string containing t1e

l i f 1 *l di - d i di 1 d

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location of t1e *le+ dis- dri2e% directory pat1% and

*lename 0ll are optional and wit1in apostrop1es

,ollowed by a byte of 1e Geros

So t1e name gi2en

T1e ma lengt1 of t1e string is @BFbytes T1e following code de*nes a dri2e and *lename+

$0TH0@ D! XD+^Test&asmN%AAH

T1e bac-slas1 acts as a pat1 separator&

0 byte of Geros terminates t1e string&

,or interrupts t1at re?uire an 0S#IIP string% load its o6set addressin t1e D register

4'0 D%$0TH0'

Interrupts

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@& To et t1e address of $S$+mo2 a1%C@1 3Re?uest address of $S$

int B@1 3#all DOS

mo2 'S%! 3 Sa2e $S$ address in 'S !y determining t1e address of $S$% t1e data can

be accessed in order to process speci*ed *les orto ta-e special action&

DOS function C@H deli2ers to t1e ! register t1esegment address of current $S$&

T1e abo2e code gets address of $S$ and storesit in 'S register&

B) Create File (A I*! 2: =C OV 0H% ;#H 3 Re?uest create *le

4'0 D *lename 3 0S#IIP string

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4'0 D% *lename 3 0S#IIP string

OV #% *le attribute 3 (AAAA= OR04% AAA@=R'0D

O4]% AAAB= HIDD' )

IT B@H 3 #all DOS

i2en a proper pat1name it creates a new *le indesignated directory&

If t1e speci*ed *le already eits% it is truncated to

Gero lengt1& In eit1er case% t1e *le is opened and a 1andle is

returned t1at can be used by t1e program forsubse?uent access to t1e *le&

;) /pen File( I*!2: =D

OV 0H% ;DH 3 Re?uest open *le

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OV 0H% ;DH 3 Re?uest open *le

OV 04% 0##'SS OD'3 (AA= Read% A@=9rite%@A=Read8write)

4'0 D% fname 3 0ddress of pat1name

IT B@H 3 #all DOS

If a *le wit1 t1e gi2en *lename eists% t1e operation setst1e record lengt1 to @%assumes t1e *leNs currentattribute% sets t1e *le pointer to A%clears t1e carry 5ag%and sets a 1andle for t1e *le in t1e 0 w1ic1 is to beused for all subse?uent operations&

If t1e *le does not eist% t1e operation sets t1e carry 5agand returns an error code in t1e 0&

/) #ead File( I*! 2: =F

OV 0H% ;,H 3 Re?uest read record

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?

OV !% Handle 3 ,ile 1andle

OV #% 4engt1 3 Record lengt1

4'0 D% I$R'# 3 0ddress of input record

IT B@H 3 #all DOS

T1is function is used to read t1e contents oft1e *le& T1e number of bytes to be read %and t1e address of t1e input area is passed

into t1e register # and D respecti2ely& 0 2alid operation deli2ers t1e record to t1e

program% clears t1e carry 5ag% and sets t1e0 to t1e number of bytes actually read&

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DOS commands

"nternal / !>ternal Commands

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T1e user commands t1at areaccepted by #O0DO fall into; categories+

@&Internal commandsB&'ternal commands

;&!atc1 commands

Internal #ommand

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Int"rnal Command' ;

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Internal #ommands are located in memoryand do not re?uire furt1er dis- access w1ent1ey are used&

#O$]% D'4% DIR% V'R% T]$'% $RIT%R'

Intrinsic commandst1ose are carried outby code embedded in #O0DO itself&

t1e routines for t1e internal commands are

included in transient part of#O0DO

'T'R04 DOS #O0DST1ey reside on t1e DOS dis- and re?uire a dis-

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T1ey reside on t1e DOS dis- and re?uire a dis-

access to be used #HQDSQ% ,OR0T% DISQ#O$] %D%#D%RD

0Gtrinsic commandsor transient programs aret1e names of t1e programs stored in dis- *les&

!efore t1eir eecution% t1ese programs must beloaded from t1e dis- into t1e transient programarea (T$0) of memory&

0s soon as an eternal command 1as completedits wor-% it is discarded from memory3 1ence itmust be reloaded from dis- eac1 time it isin2o-ed&

,OR0T

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'9 DISQS 0] !' ,OR0TT'D04R'0D] OR OT

USI TH' ,OR0T #O0D

IITI04IP'S3 !] 9RITI #OD' O ITTO 0SSI TR0#QS 0D S'#TORS9H'R' ]OUR D0T0 9I44 !' STOR'D&

,OR0T 'R0S'S 0D #H'#QS O4DDISQS ,OR 'RRORS

DIR'#TOR]

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TH' DIR #O0D IS 0 IT'R04DOS #O0D US'D TO 4IST#OT'T

DIR DIR89

DIR8$

#O$] #O0D

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TH' #O$] #O0D 0Q'S 0S'#OD #O$] O, 0 ,I4' OTO0OTH'R D'STI0TIO

I, ]OU 90T TO #O$] SO'THI,RO O' DIR'#TOR] TO 0 DISQ

]OU UST !' I TH0T DIR'#TOR]

#O$] DO'S OT 'R0S' TH'ORII04

D'4 OR 'R0S'

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R'OV'S D0T0 9IDO9S C IS H'4$,U4 ,OR THIS

O#' 'R0S'D % 0 ,I4' #0OT !'

R'#OV'RD U4'SS US' 0 S$'#I04UTI4IT] 4IQ' ORTO UTI4ITI'S

T]$'

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4IST OR T]$'S TH' #OT'TS O, 0,I4' O TH' S#R''

US',U4 ,OR 3 !0T% TT%

QDIR(D)% #HDIR(#D) %RDIR(RD)

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( )

D 0Q'S 0 DIR'#TOR] #D #H0'S DIR'#TOR]

RD R'OV'S 0 DIR'#TOR]

'0$4'S

!atc1 ,iles

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Tet *les t1at contain lists of ot1erintrinsic % etrinsic % or batc1commands&

T1ese *les are processed by a specialinterpreter t1at is built into t1etransient portion of #O0DO&

T1e interpreter reads t1e batc1 *leone line at a time and carries out eac1of t1e speci*ed operations in order&

TSR $rograms It is a DOS program t1at on eecution is

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It is a DOS program t1at on eecution is

loaded in t1e memory and is resident in t1ememory till it is remo2ed or system is reboot&

$resent in t1e memory e2en if not acti2e

Ot1er programs (transient) run and free t1ememory bloc- in use after completion orsystem aborting t1em&

TSR performs t1e tas- in bac-ground

any TSRs in memory at a time Typically include cloc-s% calculators% screen

sa2ers

TSR 91ile running anot1er program in DOS % press t1e

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91ile running anot1er program in DOS % press t1e

present -eyboard -ey or t1e combination of -eysand TSR program will pop up in 2iew&

#an be loaded any time

ostly no option for unloading so stay in memory

0cti2e TSR+ responds to a 18w interrupt e&g& pop upprograms

$assi2e TSR+ acti2ated in response to an eplicitcall from an eecuting application program& T1ey

contain a callable library of routines& T1ey can alsoetend some !IOS or DOS call& '&g& mouse dri2er&

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@ Ser2ices pro2ided by DOS +i&,ile anagement

ii&emory anagement

iii&$rogram 4oadingi2&Input 8 Output

a&one of abo2e b&0ll of abo2e

c& I " ii only d&iii " i2

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B& 91ic1 is an absolute image of t1eeecutable program:

a& 0 O b& 0 &'' c& $S$ d& 0ll

a%b%c

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;& T1e di6erence (s) between O*le and &'' *le is 8are+

@&SiGe of *le

B&o& of Segments present in eac1 *le;&C@B byte 1eader

/&$S$ before *le start

a & 0ll of abo2e b& one of abo2e

c& @%B%; Only d& ; only

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/& Types of TSR program is 8 are+

a& @ b& B c& ; d&/

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C& 91ic1 cac1e is used to speed upt1e paging operation in t1e computermemory:

a& T!4 b&T4! c&$age table d&0ll of t1ese

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.& T1e registers pus1ed onto t1estac- due to ISR eecution are+

aSb& #S%I$

c& #S% I$% ,40S

d& #S% I$% T,%I,

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K& 91ic1 5ag is responsible for singlestep eecution of program:

a&I,

b&Trap ,lag

c&Direction ,lagd&0ll of abo2e

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F& FBC0 c1ip is a+

a&Timer

b&icrocontroller

c&icroprocessor

d& $rogrammable Interrupt #ontroller

& 9it1 reference to FBC0 IRR% $R% ISR% IRstands for+

a&Interrupt Re?uest Register% $riority Resol2er% In

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a&Interrupt Re?uest Register% $riority Resol2er% In

Ser2ice Register% Interrupt as- Register respecti2ely&

b& Interrupt Re?uest Register% $riority Register% InSer2ice Register% Interrupt as- Register respecti2ely&

c& Interrupt Re?uest Register% $riority Resol2er% InSer2ice Register% Input as- Register respecti2ely&

d& Interrupt Re?uest Register% $riority Resol2er%Interrupt Ser2ice Register% Interrupt as- Registerrespecti2ely&

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&@A ,or mas-ing t1e interruptre?uests t1e operational commandword used is+

a& O#9@ b& O#9B ;&O#9; /&

one of abo2e

6: K

An'"r ="+

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6: K

62 a

6= c

6, K

65 1

6 c

6 K

68 d

69 a

6:' a

iK@& 91ic1 of t1e following statement(s) is 8

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g

are true about t1e ./=bit R,40S register iniK :

i".ower $'bits same as 0.-S register

ii"2pper $ bits are reserved

iii".ower $ bits are reserved

a&0ll of abo2e

b&one of abo2e

c&i only

d&i " ii

iK

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B& 91ic1 of t1e following statement(s) is8are true related to features of iK:

i"%ehalem microarchitecture support with 34I

ii"5 bit 6I4

iii"(n chip 042

iv"7*8 . cache shared b9 all cores

a& one of abo2e b& i " ii

c& i %ii% i2 d& all ofabo2e

Instruction Set

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; t1e 2ersions of R'$ instructions+i"64 , 64:

ii"64%, 64%:

a& i only b& ii only c& i " ii d&one

Instruction Set

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/ acro and $rocedurei".i;e macro procedure e