mos-ak_jms by rohit anand

7/31/2019 MOS-AK_JMS by rohit anand

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Principles of the 1-T DRAMConcept on SOI

Jean-Michel Sallese, Serguei Okhonin, Pierre FazanMikhail Nagoga

LEG Laboratory, Swiss Federal Institute of Technology, EPFL,1015 Lausanne, Switzerland


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1T/1C DRAM cell area : 8F 2 (F: min. feat. size)

Capacitor does not scale below 100 nm (30 fF) Alternate Memory Solutions : exotic materials, large cells and complex:

FERAM : 1T / 1 FeCap - MRAM : 1T / 1 MTJ - OUM : 1T / 1 R

Capacitor-less DRAM Cells : some attempts, still complex: 2T cell on bulk Si or SOI, Tunnel diode .

Objective of this work: a 1T cell Use SOI MOSFETs Scales with CMOS < 100 nm

Introduction

CBL

WL

T


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PD SOI-Mosfet Floating Body Effects:Floating Body Device operation instabilities:

Kink effect Self heating Transient effects:

Current overshooting Current undershooting

1T DRAM : exploits such effects: Use SOI body charging to store information.

Use SOI transistor to read stored information.

Introduction

Gate

Si

Buried OxideS DSiO 2 + + +

PD-SOI Nmosfet


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1T-DRAM Concept Store excess of + or - charges in the Body of PD

SOI-MOSFETs Use the transistor amplifying mode: 1T Gain Cell

VG > V ON

VDD VDD

VDD /2

Vcc/2

00

VG > V ON

1T/1C-DRAM True 1T-DRAM

BL1

C BLC Cell

BL1

+/ V

+ + +

- - -

Read bycurrentsensing

I1, I 0

Store 1

Store 0

Read bychargesharing


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Samples :0.25 m PD-SOI N&P MOSFETs from LETI 0.13 m PD-SOI N&P MOSFETs from IMEC

Data Writing (PD N-mosfet):Write a 1 :

Channel impact ionization : excess of holes

Write a 0 : Forward biasing body junction: default of holes

Data Reading:Read the information stored by current sensingNon destructive read

Data Refreshing:DRAM= data loss with timeRefresh operations needed

1T-DRAM Operation Modes


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Writing 1 Use impact ionization mechanism:

Example of voltage for 0.25 m NMOS devicesfor writing 1 in 3 ns


Gate

SiBuried Oxide

S D+ + +SiO 2

0.6V

0V 2V

PD-SOI NMOS


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Writing 0 Use hole removal mechanism:

Example of voltage for 0.25 m NMOS devicesfor writing 0 in 3 ns


PD-SOI NMOS

Gate

Si

Buried Oxide

S D+ + +- - -0V -2.3V

0.6V

SiO 2


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Writing 1 & Writing 0( 0.25 m PD N-mosfet, W/L = 25/0.5 m )


0

1 10 -5

2 10 -5

3 10 -5

4 10 -5

5 10 -5

0 5 10 15 20

R e a

d C u r r e n

t [ A

]

Time [s]

"1"

"0"

W/L=25/0.5 m


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Data reading: current sensing

Key difference vs 1T/1C-DRAM: Non destructive read

But refresh needed: charge loss due to generations & recombinations


0.6V

0.3V

- +

I read

-10

0

10

20

30

40

50

0 0.5 1 1.5

R e a

d C u r r e n

t [ u A ]

Gate Voltage [V]

180 mV

"1"

"0"

VD = 0.2 V1 & 0 meas. 1 ms after pulse

S t e a d y

S t a t e


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2D Simulation & Mechanisms

Device structure

N-channel FETon SOI (0.3 m)

Gate oxide:4.5nm

Source DrainGate

oxide 400nm

Si-substrate

Body: 3.10 17 to 1.10 18


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During Writing 1 VG= 0.6V V S= 0V VD= 2V

S D

Gate

S

Gate

D

Holes generated byImpact Ionizationat high V D (2V)

Hole Flux due to ImpactIonization:Positive charge in the body


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After Writing 1 VG= 0.6V V S= 0V VD= 0.3V

DD

SS

Gate Gate

Excess of holes in the body

Excess of channel electrons: Drain current increases

until holes are evacuatedthrough forward junctionleakage

Hole density Hole Flux density


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After Writing 1

0 ms

1 ms4 ms14 ms

100 ms400 ms3 s

Decay of the body potential as afunction of time after Writing 1


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During Writing 0 VG= 0.6V V S= 0V VD= -1V

Gate Gate

S S DD

Holes are removed after a few ns

Hole current density after 1 ns after 3 ns


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DD SS

GateGate

after 10 ns after 100 ns: steady state


During Writing 0


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Gate

DS


After Writing 0 VG= 0.6V V S= 0V VD= 0.3VDefault of holes in the body

Default of channel electrons: Drain current decreases

Hole density

Gate

DS

Reverse junction leakagegenerates holes in the body


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After Writing 0

3 s1.5 s700 ms300 ms10 ms

0 ms

Decay of the body potential as afunction of time after Writing 0


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1T-DRAM Cell Scaling

Demonstration for small W/L and 3 ns operation High endurance: >10 15 extrapolated

-20

-10

0

10

20

30

40

50

60

0 50 100 150 200

I s [ A / m

]

Time [ s]

L = 150 nmW = 400 nm

-20

0

20

40

60

80

0 50 100 150 200 250 300 350 400Time [ns]

L = 0.2 mW = 10 m

Writing "0"

3ns drain pulse

Writing "1"3ns drain pulseembedded into7ns gate pulse

I s [ A / m

]


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Conclusion

1T/1C-DRAM cells: does not scale below 100 nm SOI DRAM = true 1T-DRAM = 4F 2 cell Exploits Floating Body charging of PD SOI-MOSFETs No capacitor, no new materials, no additional masks

Standard CMOS logic or memory process Ideal for merged logic/memory SOC applications Non destructive read in a refresh interval High switching speed: 3 ns demonstrated Scalable

mos-ak_jms by rohit anand

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