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ECE 3040: Chapter 3 PN Junction

Chapter 3 The PN Junction

3.1 PN-Junction Electrostatics

3.2 I-V Characteristic

3.3 Dynamic Behavior

3.4 Diode Circuit Models3.5 Diode Applications and Circuits

3.6 SPICE Analysis

Literature:

Pierret, Chapter 5-7

Jaeger Blalock, Chapter 3

Acknowledgement Oliver Brand for slides

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The PN Junction

I = Is eqVA /kT "1

I-V Characteristic

P N

Circuit Symbol

+ Forward Bias

Reverse Bias +

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3.1 PN Junction: Electrostatics

3.1.1 PN Junction Basics

Junction Approximations

Band Structure

Built-In Potential

3.1.2 Step PN Junction Equilibrium VA= 0

External Bias VA!0

Pierret, Chapter 5, page 195-226

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3.1.1 PN Junction Basics

Example: Diffusion of acceptor atoms (e.g. boron) in n-substrate

Metallurgical junction at NA= NDor ND NA=0

Net Doping

ND NA

Pierret, Fig. 5.1

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Doping Profile Approximations

for PN Junctions

Approximations for doping profile in pn junctions:

Step Junction: approximation for ion implantation or shallowdiffusioninto lightly doped wafer

Linearly Graded Junction: approximation for deep diffusionin

moderately to heavy doped wafer

Step Junction Linearly Graded Junction

Pierret, Fig. 5.2

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PN Junction

Band Diagram Equilibriumrequires the Fermi

levelto be constantacross thedevice

Regions far away from the

metallurgical junction will beunaffected

Electrons diffusefrom n- to p-side, holes from p- to n-side,leaving behind unbalanceddopant site charges

This space chargecreates anelectric field(band bending),resulting in a carrier driftbalancing the carrier diffusion(Jtot= 0) Pierret, Fig. 5.3

qVbi

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PN Junction

Band Diagram Equilibriumrequires the Fermi

levelto be constantacross thedevice

Regions far away from themetallurgical junction will beunaffected

Electrons diffusefrom n- to p-side, holes from p- to n-side,leaving behind unbalanceddopant site charges

This space chargecreates anelectric field(band bending),resulting in a carrier driftbalancing the carrier diffusion(Jtot= 0) Pierret, Fig. 5.5

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PN Junction Built-in Potential

The built-in potentialcanbe calculated from theband diagram:

With the results from Chapter 2.5

we obtain

Vbi =1

qEi"EF( )p"side + EF"Ei( )n"side

#$%

&'(

p =NA =nie(Ei"EF)/kT p " side withNA >>ni

n =ND =nie(EF "Ei)/kT n" side withND >>ni

Vbi =1

qkT ln

NAni

"

#$

%

&'+ kT ln

NDni

"

#$

%

&'

(

)*

+

,-=

kT

qln

NAND

ni2

(

)

**

+

,

--

Pierret, Fig. 5.4

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PN Junction Depletion Approximation

To obtain quantitative solutions forthe electrostatic variables, thePoisson equationneeds to besolved:

This requires the knowledge of thecharge distribution, which itself (nand p) is influenced by the potential

The depletion approximationisoften used to approximate the chargedistribution:

1.

The carrier concentration n andp is negligible in the depletionregion, i.e. for -xp"x "xn

2. The charge density outside thedepletion region is zero

Pierret, Fig. 5.6

"#$ =%

Ks$0=

q p & n+ND &NA

Ks$0

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Electrostatics

From charge distribution toelectric field:

From electric field to electrostaticpotential:

"#$ =%

Ks$0or in1D

d$dx

=

%

Ks$0

"=

#$V or in1D "=

#

dV

dx

Pierret, Fig. 5.9

Example:Step Junction

d!0

!(x)

" =!(x) = 1Ks!0

#(x) dx$%

x

"

dV

0

V(x)

! = V(x) = " #(x) dx"$

x

!

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3.1.2 Step Junction: VA= 0 Assuming depletion approximation

and a step junction, the chargedensity in the depletion region is

The electric fieldis obtained byintegration

with the boundary conditions

!(-xp) = !(xn) = 0

" =

#qNA #xp $ x $ 0

+qND 0 $ x $ xn

0 x < xp or x > xn

%

&'

'

d"0

"(x)

#=

1

Ks"0$(x) dx

%&

x

#

Pierret, Fig. 5.9

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Step Junction with VA= 0

Resulting electric field:

The electric potentialis obtained bya second integration

with the boundary conditionsV(-xp) = 0 and V(xn) = Vbi

"(x) =#qNAKs"0

xp + x( ) #xp $ x $ 0

#qND

Ks"0xn# x( ) 0 $ x $ xn

%

&''

('

'

dV

0

V(x)

"=#

$(x) dx

#%

x

"

Pierret, Fig. 5.9

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Step Junction: Charge Considerations

The electric field must be continuous at x = 0, yielding:

This constitutes that the total charge within thedepletion region must sum to zero, i.e. the positivecharge on the n-side is balanced by the negativecharge on the p-side of the junction

This overall charge neutrality is a direct consequenceof the assumption that the electric field vanishesoutside the depletion region, as follows from Gauss

law

"qNAKs#0

xp = "qNDKs#0

xn

qNAxp = qNDxn

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Step Junction with VA= 0

Resulting electric potential:

The electric potential is continuous atx = 0, yielding:

Together with the charge neutralityrelationship NAxp= NDxn, thisequation can be used to determine xnand xp

V(x) =

qNA2Ks"0

xp + x( )2

#xp $ x $ 0

Vbi#qND2Ks"0

xn# x( )2

0 $ x $ xn

%

&''

(''

Pierret, Fig. 5.9qNA2Ks"0

xp2= Vbi #

qND2Ks"0

xn2

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Step Junction Depletion Layer Width

We obtain for xnand xp:

Thus, the depletion layer width W is

xn =2Ks"0q

NA

ND NA +ND( )Vbi

xp =2Ks"0q

ND

NA NA +ND( )Vbi

W = xn + xp =

2Ks"0q

NA +NDNAND

Vbi

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Step Junction

with VA!0

Assumption: Externally

applied voltage VAiscompletely dropped

across the depletion

region I.e., negligible voltage

drop at contacts andacross the quasi-neutral

regions

+ VA

p n

VA> 0: Reduces potential

step across junction

VA< 0: Increases potential

step across junction

Pierret, Fig. 5.12

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Step Junction

with VA!0

Forward Bias VA> 0:Potential drop acrossthe depletion regiondecreases; majoritycarrier diffusion

dominates, resulting in alarge forward currentflow

Reverse Bias VA< 0:Potential drop acrossthe depletion region

increases; minoritycarrier driftdominates,resulting in a smallreverse current flow

Pierret, Fig. 5.12

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Step Junction with VA!0

Bias VAcan be implemented in equations byreplacing Vbiwith Vbi VA:

Forward Bias VA> 0 Reduced depletion layer width

Reduced space charge

Reduced electric field

Reduced potential drop across junction

Reverse Bias VA< 0

Increased depletion layer width

Increased space charge

Increased electric field

Increased potential drop across junction

W =2Ks"0q

NA +NDNAND

Vbi #VA( )

Pierret, Fig. 5.11

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3.2 PN Junction: I-V Characteristic

3.2.1 Qualitative Derivation

3.2.2 Quantitative Derivation

Minority Carrier Distribution

Minority Carrier Currents

I-V Characteristic Saturation Current

3.2.3 Junction Breakdown

Avalanche Breakdown

Zener Breakdown

Pierret, Chapter 6.1, page 235-259

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3.2.1 Qualitative Derivation

(a) Equilibrium

Under equilibrium, thenet current flow is zero,i.e. the electron/holedrift and diffusioncurrents balance eachother

Electron Currents:

Majority carrier diffusion current from n- to p-side

Minority carrier drift current from p- to n-side Hole Currents:

Majority carrier diffusion current from p- to n-side

Minority carrier drift current from n- to p-side

J = Jdrift + Jdiff = 0

Pierret, Fig. 6.1

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Qualitative Derivation

(b) Forward Bias

Forward bias (VA> 0)reduces the potential

drop across the

depletion region

As a result, the majoritycarrier (electron andhole) diffusion over the

potential hill increases

exponentially, resultingin a net current flow

across the junction The minority carrier

drift currents remain

constantPierret, Fig. 6.1

Majority carrier

density decreases

exponentially with

increasing energy

E

n(E)

p(E)

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Qualitative Derivation

(c) Reverse Bias

Reverse bias (VA< 0)increases the potential drop

across the depletion region

As a result, the majoritycarrier (electron and hole)

diffusion current over thepotential hill is suppressed

for VA> few kT

The minority carrier drift

currents remain constant,

thus resulting in asaturation current flowing in

reverse direction

Pierret, Fig. 6.1

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3.2.2 Quantitative Derivation

Solution Strategy

1. Calculate the minority carrier concentrationin thequasineutral regions on the p- and n-side of the

junction by solving the continuity equation

2. Calculate the minority carrier current densitiesatthe edges of the depletion region x = xn

and x = -xp

3. Calculate the total current densityflowing through

the diode by adding the hole and electron minority

carrier density, assuming no generation/recombination effects in the depletion region

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1-D Continuity and Current Equations

1-D Current Density Equation

1-D Continuity Equation

Which terms do we have to consider?

Jp= q

pp!"qD

p

dp

dx

Jn= q

nn!+qD

n

dn

dx

!np(x,t)

!t= +n

p

n

!"

!x+

n"!n

p

!x+D

n

!2n

p

!x2 +G

L#np#n

p0

$n

!pn(x,t)!t

= #pn

p!"!x

#p"

!pn!x

+Dp!

2

pn

!x2 +G

L# pn #pn0

$p

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PN Junction: IV CharacteristicAssumptions for Quantitative Derivation

Steady state conditions

Non-degenerately doped step junction

One-dimensional pn-junction

Low-level injection in quasineutral regions

No generation/recombination processes other thanthermal recombination/generation in the diode

xp xn

!= 0 !!0 != 0

Quasineutralp-region

Quasineutraln-region

Depletionregion

xx

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0 =Dnd2"np

d #x 2 $

"np

%n

=Dnd2np

d #x 2 $

np $ np0

%n

for #x & 0

0 =Dp

d2"pn

dx2 $

"pn

%p

=Dp

d2pn

dx2 $

pn $ pn0

%p

for x & 0

PN Junction: IV Characteristic

Continuity Equation

Continuity equation for quasineutral regions

Steady state (dpn/dt = dnp/dt = 0)

No E-field, i.e. all drift terms are zero

No R-G other than thermal R-G (e.g., GL

= 0)

withnp = np0 + "np and pn = pn0 + "pn

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PN Junction: IV Characteristic Minority Carrier Concentration

General solution

Boundary conditions at ohmic contacts:Assumption: wide quasineutral regions, i.e.

"np #x $ % = 0 & B = 0

"pn x$ %( ) = 0 & D = 0

"np( #x ) =Ae$ #x /Ln

+Be #x /Ln for #x % 0

"pn(x) = Ce$x /Lp

+Dex /Lp for x % 0

withLn = Dn&n andLp = Dp&p

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Boundary conditions at edge of depletion region:

Assumption: Equation is true also for applied VA!

Vbi =kT

qlnNAND

ni2

=

kT

qlnpp0nn0

ni2

=

pp0np0 =ni2

kT

qlnnn0np0

" nn0 =np0eqVbi /kT

Vbi " Vbi #VA

$

nn=

npe

q Vbi#VA( ) /kT

$ np =nne#q Vbi#VA( ) /kT

%nn%nn0

weak injection

nn0e#qVbi /kT

=np0

!

"

#

#

$

#

#

eqVA/kT

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Boundary conditions at edge of depletion region (cont.):

np = np0 eqVA /kT

and similar pn = pn0 eqVA /kT

or !np = n

p0 e

qVA/kT

"1#$%& at " xp, i.e. 'x = 0

!pn = p

n0 e

qVA/kT "1#$

%& at + xn, i.e. x = 0

" A = np0 e

qVA /kT #1 and C = pn0 eqVA /kT #1

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Minority Carrier

Concentration

Thus, the minoritycarrier distributionsin the quasi-neutralregions become:

"np( #x ) = np0

eqVA /kT $1[ ] e$ #x /Ln"pn(x) = pn0

eqVA /kT $1[ ] e$x /L

p

Forward Bias Reverse Bias

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PN Junction: IV CharacteristicMinority Carrier Concentrations

Forward Bias Reverse Bias

Pierret, Fig. 6.8

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PN Junction: IV Characteristic Diffusion Current Densities

The minority carrier diffusion currents in thequasineutral regions can be derived from the minoritycarrier distributions by

Thus, at the edges of the depletion region

Jn( "x ) = +qDnd#np

d "x= $

qDnnp0

Lne

qVA /kT $1[ ] e$ "x /Ln

Jp(x) = $qDpd#pn

dx= +

qDppn0

Lpe

qVA /kT $1[ ]e$x /Lp

Jn

x = "xp( )

= "Jn

( #x = 0) = +qDnnp0

LneqVA /kT "1

[ ]Jp x = +xn( ) = +Jp(x = 0) = +

qDppn0

LpeqVA /kT "1[ ]

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PN Junction: IV Characteristic Diffusion Current Densities

Pierret, Fig. 6.7

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PN Junction: IV Characteristic Total Current

Assuming that there is no R-G in the depletion region,the total current density flowing through the pn

junction is the sum of the minority carrier currents at

the edges of the depletion region

J = Jn x ="xp( ) + Jp x = +xn( )

=

qDnnp0

Ln

+

qDppn0

Lp

#

$%

&

'(

) Js

!

"

#

#

#

$

#

#

#

eqVA /kT "1[ ]

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PN Junction: IV Characteristic

Pierret, Fig. 6.6

Reverse Bias VA< 0

For |VA| > few kT/q, a small

saturation current Jsisflowing through the pn

junction

Forward Bias VA> 0

For |VA| > few kT/q, the

current flowing through thejunction increases

exponentially

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PN Junction: Saturation Current

The saturation current density is given by

The saturation current depends on the intrinsic

carrier concentration niand, thus, is stronglytemperature and material dependent

The saturation current is dominated by the

contribution from the lower doped side of the junctionin case of asymmetrical junctions

Js =qDnnp0

Ln+

qDppn0

Lp=

qDnni2

LnNA+

qDpni2

LpND

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Real

IV Characteristic

Junction Breakdown

Junction Breakdown

Pierret, Fig. 6.9

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3.2.3 Junction Breakdown

Junction or Reverse-Bias Breakdown:current flowing in a pn-junction under reverse bias suddenly increases drastically if reverse

bias is increased over the so-called breakdown voltage VBR;breakdown process is reversible if the junction is not overheated

(current must be limited)

The breakdown voltagedepends on

Junction doping(the non-degenerate doping in case of a n+-p orp+-n junction)

Temperature

Radius of curvaturein case of junctions with curved non-planar

edges because of larger electric fields in the curved edges; thiseffect becomes important for shallow junctions

The basic breakdown processesare

Avalanching

Zener process(dominating if VBR< 4.5 Eg/q)

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Breakdown Voltage in Planar p+-n/n+-p Junctions

Doping conc. of lightly doped side! Pierret, Fig. 6.11

Zenerdominating

VBR "1

NB0.75

Avalanchedominating

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Avalanche Breakdown

Avalanching Process

Minority carriers in junctiondepletion region gain enoughkinetic energy to generateelectron-hole pairsduring

an impact; this is calledimpact ionization

This way, the

number of carriers

can increasetremendously,

similar to a snow

avalanche, ultimately causinga junction breakdown

Pierret, Fig. 6.12

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Zener

Breakdown Breakdown current due

to quantum mechanicalcarrier tunnelinginhighly-doped, degenerate

pn-junctions Physical background:

there is a quantum

mechanical probabilitythat a particle can tunnel

through a potential

barrier even if its energyis smaller than the barrier

heightPierret, Fig. 6.13 & 6.14

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3.3 PN Junction: Dynamic Behavior

Small-Signal Analysis

Equivalent Circuit

Forward-Bias / Reverse-Bias Characteristics

Depletion Layer Capacitance

Diffusion Admittance

Pierret, Chapter 7, page 301-324

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Small-Signal Analysis Equivalent Circuit

AC current iflowing throughthe diode biased by small

AC voltage vasuperimposed

on DC bias VA

Small-signal admittance Y

consists of capacitive C andconductive G component:

Equivalent circuit of diode

consists of junctionadmittance Y and series

resistance Rsof quasineutralregions

Y = i / va =G +j"C

Pierret, Fig. 7.1 & 7.2

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PN Junction: Small-Signal Behavior

(a) Reverse Bias Small signal behavior is dominated byjunctionor depletion-

layer capacitance Cj

The junction capacitance Cjarises from majority carrier

(charge) oscillationsat the edges of the depletion region

Conductance is very small (i.e., very high resistance)

(b) Forward Bias

With increasing forward bias, the diffusion admittance

Yd= Gd+ i Cddominates the small signal behavior

The diffusion capacitance Cdarises from minority-carrier(charge) oscillationsin the quasineutral regions adjacent to

the depletion region

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Junction

Capacitance

The so-called junction or depletion-

layer capacitance originates fromcharge oscillations at the edge of

the depletion region caused by the

applied ac voltage va The capacitance resulting from the

small oscillations of the depletionregion around its steady-state width

W is equivalent to that of a parallel

plate capacitor with width W

Cj =dQ(VA,va)

dva=

Ks"0A

W(VA)

Pierret, Fig. 7.4

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Junction Capacitance Cj

Junction capacitance Cjdepends on the applied dc bias VA,

because the depletion layer width W is a function of VA; in caseof a step junction, the depletion layer width becomes

Characteristics of Cj

Cjoriginates from majority carrier oscillations

Cjdecreases with increasing reverse bias -VA Varactor diodes use Cjas voltage-controlled capacitor

Majority carrier response time in Si is < 10-10s, i.e. Cjisfrequency-independent up to very high frequencies

W =2Ks"0q

NA +NDNAND

Vbi #VA( )

Cj =Ks

"

0

A

W(VA)=

Ks

"

0

A

2Ks"0q

NA +NDNAND

Vbi #VA( )

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Junction Capacitance Cj The junction capacitance Cjcan be expressed in terms of its value

Cj0for VA= 0:

The measurement of the junction capacitance is used as diagnosistool (C-V measurement) to get an inside view of the junction;assuming an asymmetric step junction, e.g. ND NA= NB, oneobtains:

The linear 1/Cj2vs. VArelationship has a slope proportional to NB

-1and an intersection with the V-axis at VA= Vbi

Cj =Ks"0A

2Ks"0q

NA +NDNAND

Vbi

=Cj(Vbi)#Cj0

! "### $###

1

1$VAVbi

%

&'

(

)*

=

Cj0

1$VAVbi

%

&'

(

)*

1

Cj2=

2

qKs"0A2

NB

Vbi #VA( )

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Forward-Bias Diffusion Admittance

The diffusion admittance

is caused byminority carrieroscillations in the quasi-neutral

regions adjacent to the

depletion region

Small signal equivalent circuitof forward-biased pn-junctionconsists of

junction capacitance Cj,

diffusion capacitance CD, and

diffusion conductance GD Minority carrier lifetime limits the

frequency up to which the

minority carriers can follow vaPierret, Fig. 7.8

YD =GD +j"CD

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Diffusion Admittance Relationship AC behavior can be extracted similar to dc behavior from

continuity equations (example: p+-n junction) Continuity equation for n-side minority carriers

with the minority carrier distribution

Using separation of variables, two DEs for the dc and ac terms

result:

"#pn(x,t)

"t=Dp

"2#pn(x,t)

"x2 $

#pn(x,t)

%p

"pn(x,t) = "pn(x) +!

pn(x,#) ej#t

0 =Dp"2#pn

"x2

$#pn

%p

0 =Dp"2!pn

"x2 $

!

pn

%p / 1+j&%p( )

same as dc

similar to dcbut

!

"p = "p / 1+j#"p

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"pn(#,t) = 0

"pn(xn,t) =ni2

NDeq VA +

!

va( ) /kT $1%&'

()*

=

ni2

ND

eqVA /kT $1

[ ]="pn(xn)"

#

$

$

%

$

$

+

ni2

ND

eqVA /kT eq!

va /kT $1

( )

%

&

'

(

)

*

=

!

pn(xn,+) ej+t

"

#

$

$

$

$

%

$

$

$

$

Diffusion Admittance Relationship Boundary Conditions:

for qva kT, we can simplify using ex#1 + x for small x

!

pn

(xn

,") ej"t =ni2

NDeqVA /kT

q!

va

kT

!

pn(xn,") =ni2

NDeqVA /kT

qvakT

v(t) = VA + va ej"t

=!

va

"#$

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Diffusion Admittance Relationship Using the newboundary conditions and the modified minority

carrier lifetime, the ac diffusion current becomes (in analogy tothe dc diffusion current)

Idiff =qADpni

2

LpNDeqVA/kT "1[ ] =qA

Dp

#p

ni2

ND

=Is

! "# $#

eqVA/kT "1[ ]

idiff =qADp

#p1+j$#p

ni2

ND

qvakT

eqVA/kT

%

&'

(

)*

= ISq

kT

eqVA/kT

=G0=dI

dVA

!

"

#

#

$

#

#

1+j$#pva =YDva

DC

AC

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Diffusion Admittance Relationship The diffusion admittance YDfor the p

+n diode

consists of a conductive part GDand a capacitive part CD

For #p= 1 $s, we get "#p= 1 at f = "/2$= 160 kHz

YD =GD +j"CD =idiffva

=G0 1+j"#p

GD =G0

21+ "2#p

2+1$

%&'()1/2

*" #p


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3.4 PN Junction: Diode Models

3.4.1 Load-Line Analysis

3.4.2 Ideal Diode Model

3.4.3 Constant Voltage Drop Model

3.4.4 Breakdown Model

Jaeger & Blalock, Chapter 3.10-3.12, page 96-112

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Diode Circuit Analysis

Establish simple diodemodelsto facilitate (dc)analysis of circuits containingdiodes

Example: Series circuit of

voltage source, resistor anddiode

Note: V and R may representThvenin equivalentof morecomplicated two-terminalnetwork

Goal: Find quiescentoperating pointor Q-pointofdiode

Jaeger, Blalock, Fig. 3.22

V = IDR+V

D

What are the values

for VDand ID?

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3.4.1 Load-Line Analysis

Load-Line Analysis =Graphical analysisif diode

I-V characteristic is onlyavailable in graphical form

Analysis approach:

Write load-line equation

Plot load-line and diode I-V

characteristic

Q-point is defined by

intersection of load line anddiode I-V characteristic


V = IDR+VD

10 = ID10

4+V

D

ID = !10

!4VD+10

!3

V=10 VR = 104%

Q-point = (0.95mA, 0.55V)

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Load-Line Analysis The Mathematical Approach

Goal: Find intersectionof load line and diode I-Vcharacteristic using mathematical software package

Given are R = 104%, V = 10 V, IS= 10-13A and

kT/q = 0.026 V, unknown are VDand ID

The Mathematicafunction FindRootyieldsVD= 0.597 V and ID= 0.940 mA

ID

= !1

R

VD

+

V

RID = I

Se

qVD/kT !1"#

$%

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3.4.2 Ideal-Diode Model

Approximationof non-linear diodecharacteristic by piece-wise linearmodel

Ideal Diode Model =Approximation with two straight-line segments

If diode is forward-biased, voltageacross diode is zerovD = 0 for iD> 0, i.e.short circuit

If diode is reverse-biased,current through diode is zeroiD

= 0 for vD

< 0, i.e.open circuit

Diode is assumed to be eitheron or off


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Ideal Diode Model

Analysis procedure:

Select model for diode

Identify diode anode (positive

terminal) and cathode (negative

terminal) and label VDand ID

Make (educated) guess on

diode region of operation based

on circuit configuration

Analyze circuit with appropriate

diode model

Check results for consistency

with assumptions

What about our simple

example?



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Example: Analysis with Ideal-Diode Model

Voltage source tries to forward-bias diode, so we replace it by

short-circuit (ON state)

IDis now easily obtained:

The current (positive) is consistent with the assumption that the

diode is ON

ID =

V

R=1mA

VD = 0 V

Jaeger, Blalock, Fig. 3.27&28

60


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3.4.3 Constant Voltage Drop Model

Piecewise linear model

accounting for constantvoltage drop across forward-

biased diode (associated

with turn-on voltageofdiode)

Turn-on voltage= voltage required to obtain

significant conduction;

typically 0.5-0.7 V

Constant voltage drop (CVD)

model: simulation of diode

by series connection ofideal diode and voltage

source


61


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Constant Voltage Drop Model

If diode is forward-biased, voltage across diode is turn-on

voltage vD = Vonfor iD> 0, i.e.constant voltage source

If diode is reverse-biased, current through diode is zeroiD = 0 for vD < Von, i.e.open circuit

We choose Von= 0.6 V &.


62


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Example: Analysis with CVD Model

Voltage source tries toforward-bias diode, so we

replace it by voltage source

(ON state)

IDis again easily obtained:

ID =

V !Von

R= 0.94mA

VD = 0.6 V


63


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Multi-Diode Circuits

Ideal diode and CVD model

enable hand-analysis of morecomplex diode circuits havingtwo or more diodes

Alternative: SPICE analysis(see Chapter 3.6)

Example problem: Find Q-pointsof both diodes in two-diodecircuit!

Approach: Try all (four) possiblediode states (one after theother) and check whetherresults are consistent with

assumptions

Result (using ideal diode model):D1 off: (0 mA; 1.67 V)D2 on: (1.67 mA; 0 V)

64


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3.5 Diode Applications & Circuits

3.5.1 Temperature Sensors

Diode Temperature Coefficient

PTAT Sensor

3.5.2 Rectifier Circuits

Half-Wave Rectifier Circuits

Full-Wave Rectifier Circuits

Full-Wave Bridge Rectifier Circuits

3.5.3 Voltage Regulators

3.5.4 Additional Applications

Jaeger & Blalock, Chapter 3.13-3.16, page 113-128

65


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3.5.1 Temperature Sensors Diode Temperature Coefficient

Forward-biased diode (operated with constant bias current) is

frequently used for temperature sensing:

Challenge: ISis proportional to ni2and thus (strongly) depends

on temperature; as a result, the VDvs. T relationship is

nonlinear

Work-around: PTAT circuit using a differential setup with 2

identical diodes

ID = I

Se

qVD /kT !1"#$% & VD =

kT

qlnI

D

IS

+1"

#'

$

%()

kT

qln

ID

IS(T)

"

#'

$

%(

dVD

dT=

k

qlnID

IS

!

"#

$

%&'

kT

q

1

IS

dIS

dT

66


67/106


PTAT Electronic Thermometer PTAT = proportional to absolute

temperatureConcept

Two identical diodes biased by current

sources I1and I2

Resulting PTAT voltage, i.e., difference

in voltage drop across the two diodes is

proportional to the absolute temperature

PTAT voltage circuit is heart of most of

todays digital thermometers

VPTAT

=VD1!V

D2 =

kT

qln ID1

IS

"

#$

%

&'! ln

ID2

IS

"

#$

%

&'

(

)**

+

,--=

kT

qln ID1

ID2

"

#$

%

&'

dVPTAT

dT

=

k

q

ln I

D1

ID2

"

#

$%

&

' =VPTAT

T

Jaeger, Blalock, page 88

67


68/106


3.5.2 Rectifier Circuits Rectifier circuit converts an ac voltage to a pulsatingdc

voltage; in combination with a filter, a nearly constant dc outputvoltage can be generated

Virtually every electronic device plugged into the wall utilizes arectifier circuit to convert the 120-240V, 50-60Hz ac power line

source to a proper dc voltage

DC power supplies are a commodity and fairly inexpensive

Jaeger, Blalock, page 128

Power Cube Cell Phone Charger

68


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Half-Wave Rectifier with Resistive Load

Sinusoidal voltage source vS= VPsin"t is

connected to a series combination of diodeD1and resistor R

Using the ideal diode model, we find that thediode is ON for vS> 0 and OFF for vS< 0,resulting in a pulsating output voltage v0

Jaeger, Blalock, Fig. 3.42 & 3.44

69


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Half-Wave Rectifier

with Resistive Load

If the input voltage amplitude(e.g. VP"10 V) is not largecompared to the voltage drop(0.5-1.0 V) across the forward-biased diode, the CVD modelshould be used for circuit analysis

In many applications, atransformeris used to step-down the power line voltage to adesired level

To remove time-varyingcomponents from outputwaveform, a filter capacitorisusually added


vS

! 0 v0

=VP

sin"t #Von

vS < 0 v

0 = 0

70


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Rectifier Filter Capacitor

Peak Detector Circuit

Assumption: initially uncharged

capacitor, i.e. v0(0)=0

As input voltage rises, diode turns on

and capacitor is charged tov0= Vdc= VP Von

At peak of input voltage waveform,

the current through the diode tries toreverse direction (because

iD= C d(vS Von)/dt), thus reversebiasing the diode and disconnecting

the capacitor from the power supply

With no discharge possibility,

v0= Vdc= VP Vonstays constant;in a rectifier however, a resistive load

R is connected in parallel to C,providing a discharge path


71


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73/106


Ripple Voltage Vr

The ripple voltage Vrshould be as small as possible

Voltage across capacitor during discharge process

The ripple voltage is thus given by

v0( !t ) = V

P" V

on( )e" !t /RC for !t =t"

T

4# 0

Vr =v

0 !t = 0( )"v0 !t =T" #T( )= V

P" V

on( ) e0 "e

"T"#T( )/RC$%&

'()

!T"#T!RC

VP" V

on( ) 1" 1+T" #T

RC

$

%&

'

()

*

+,

-

./

!#T!T VP" Von( )

R

= Idc

" #$ %$

T

C

Vr = I

dc

T

C

73


74/106


Conduction Interval "T At the beginningof the conduction interval t= T'T, we have

Assuming TRC and 'TT, both cosine and exponential function

can be expanded in a Taylor series (cos(T-'T) = cos('T))

Solving for 'T yields

Conduction angle %C

v0( !t = T" #T) = vs( !t = T" #T)"Von

VP! V

on( )e!(T!"T)/RC

=VPcos # T! "T( )$% &' !Von

VP

!Von( ) 1! T! "T

RC

#$%%

&'((= V

P1! )"T( )

2

2

#

$

%%

&

'

((

!Von

!T "1

#

2T

RC

VP$V

on

VP

=

1

#

2Vr

VP

!C ="#T $

2Vr

VP

74


75/106


Peak Diode Current IP

The charge lost during thedischarge period must besupplied to the capacitor duringthe short charging cycle,resulting in large diode currents

Assuming 'TT, the chargelostduring one period T isQ = I

dcT; this charge must be

supplied to the capacitor duringthe charging interval 'T

Assuming a triangular shapedcurrent pulse through the diode(see SPICE simulation), theresulting peak diode current IPbecomes

Jaeger, Blalock, Fig. 3.54Q = I

dcT = I

P

!T

2" I

P = I

dc

2T

!T Note: the peak currentcan be 10s of ampere

75


76/106


Surge Current ISC Surge current ISC= Peak current

during initial charging process ofcapacitor

During the initial charging, the

diode current is determined by

the charging current of the(uncharged) capacitor

In actual devices, ISCis reduced

due to series resistances ofdiode and transformer (you can

investigate this with SPICE)


id(t) = i

C(t)!C d

dtV

Psin"t#

$% &

'(

= "CVP

= ISC

!

cos"t

ISC

= !CVP

76


77/106


78/106


Half-Wave Rectifier Example

Assume:

VP= 10 Vrms= 14.1 Vp(60 Hz)R = 15 %C = 25,000 $F !!Von= 1 V (because of large currents)RS= 0.2 %

DC output voltage Vdc: Output current Idc:

Ripple voltage Vr:

Conduction interval 'T and angle %C:

Diode peak current IP: Diode surge current ISC:

PIV:

Diode power dissipation:

Vr = (I

dcT) /C = 0.58 V

!T " #

$12V

r/ V

P = 0.761ms

!C ="#T = 0.287 rad =16.4

IP

= (2 Idc

T) / !T = 38 A

ISC

=!CVP =133 A

PIV ! 2V

P = 28.2V

PD1

= VonIdc

= 0.87W

PD2

=

4

3

T

!TR

SIdc

2= 4.42 W

Vdc =VP

!Von

=13.1V

Idc

= Vdc/ R = 0.87A

78


79/106


Half-Wave Rectifier with Negative

Output Voltage

By grounding either the top of the capacitor (compared to the

bottom in Jaeger/Blalock, Fig. 3.48) or reversing the diode, therectifier circuit produces a negative output voltage, i.e. the

diode conducts on the negative half-cycle of the transformer


Vdc

= ! VP! V

on( )

79


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Full-Wave Rectifier Circuits

Operation Principle Center-tapped transformergenerates two voltages with equal

amplitude but 180 phase shift

Resulting are two half-wave rectifier circuits operating on

alternate half-cyclesof input waveform

D1charges C during one half cycle, D2charges C during the

other half cycle

Advantages

Capacitor discharge

time cut in half

Thus, requires only

one-half the filtercapacitance for a

given ripple voltageJaeger, Blalock, Fig. 3.58

80


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82/106


Full-Wave Rectifier Circuit

DC output Voltage Vdc:

Ripple Voltage Vr:

Conduction Interval 'T:

Conduction Angle %C:

Peak Diode Current IP:

PIV:

Vr =

VP!V

on( )R

T

2C= I

dc

T

2C

Vdc = VP

!Von( )

!T "1

#

2T

2RC

VP$V

on

VP

=

1

#

2Vr

VP

!C ="#T $

2Vr

VP

IP = I

dc

2T

2!T

PIV = 2 V

P

82


83/106


Full-Wave Bridge Rectification

Bridge arrangement of 4 diodes eliminates the need for a center-tappedtransformer

vS> 0 half cycle: D2and D4ON; D1and D3OFF

vS< 0 half cycle: D1and D3ON; D2and D4OFF

Output dc voltage is now reduced by 2 diode voltage drops

PIV rating for each diode is reduced: PIV #VP


Vdc

= VP! 2V

on

83


84/106


Full-Wave Bridge Rectification

Half Cycle vS> 0:

Half Cycle vS< 0: Jaeger, Blalock, Figs. 3.64 and 3.65

84


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Rectifier Comparison

Rectifier

Parameter

Half-Wave

Rectifier

Full-Wave

Rectifier

Full-WaveBridge

Rectifier

Filter Capacitor

PIV Rating 2 VP 2 VP VP

Peak Diode

Cur. (const. Vr)

Highest

IP

Reduced

IP/2

Reduced

IP/2

Comments Least complexity

Smaller capacitor

Requires center-

tapped transformer

2 diodes

Smaller capacitor

4 diodes

C =VP!V

on

Vr

T

R

C =VP!V

on

Vr

T

2R

C =VP! V

on

Vr

T

2R

85


86/106


3.5.4 Additional Diode Applications(not discussed in ECE3040)

DC-to-DC Converters

Wave-Shaping Circuits

Clamping or DC Restoring Circuit

Clipping or Limiting Circuit Piecewise Linear Transfer Function Circuit

Optoelectronic Devices

Photo Diodes

Solar Cells

Light-Emitting Diodes

86


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3.6 Diode SPICE Model

3.6.1 Circuit Simulation using SPICE

OrCAD Capture and PSPICE

Introduction to PSPICE Simulation

3.6.2 SPICE Diode Model

3.6.3 Sample Problem

Jaeger & Blalock, Chapter 3.9, page 94-96

M.E. Herniter, Schematic Capture with CadencePSPICE, Prentice Hall, 2nd edition, 2003

87


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3.6.1 Circuit Simulation using SPICE

SPICE is a general purpose circuit simulation program

originally developed at EECS Departmentof UC Berkeley Capabilities:

Analysis Types: DC, AC, transient (and more)

Circuit elements: resistors, capacitors, inductors, mutual

inductors, independent and dependent voltage and current

sources, lossless and lossy transmission lines, switches,uniform distributed RC lines, semiconductor devices

including diodes, BJTs, JFETs, MESFETs, and MOSFETs

Implementations:

PSPICE: http://www.orcad.com/; a limited student version of

PSPICE (version 9.1) is distributed with Jaeger & Blalock; ademo CD with version 15.7 can be downloaded from OrCAD

PSPICE(Cadence) and HSPICE(Synopsys) areimplemented in major integrated circuit design tools

88


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Limits of PSPICE Student Version

Circuit simulation limited to

64 nodes

10 transistors

2 op-amps or 65 digital primitive devices

10 transmission lines Device characterization using Model Editor limited to diodes

Stimulus generation limited to sine waves (analog) and clocks(digital)

Sample library of approx. 39 analog and 134 digital parts

(compared to 11,300 analog and 1,600 digital device models inthe standard package)

Display of simulation data only (no saving, except Print Screen)

89

Start Capt re St dent


90/106


Start Capture Student

90

Start New Project


91/106


Start New Project

91

Place Parts from Database


92/106


Place Parts from Database

92

PSPICE Model Parameters


93/106


PSPICE Model Parameters

93

Place Ground


94/106


Place Ground

Note: One GND must be named 0!!!

94

Wire Circuit Define Parameters


95/106


WireCircuit, Define Parameters

and Create Simulation Profile

circuit must have a GND named0

95

Simulation Settings Time Domain


96/106


Simulation Settings Time Domain

RUN

96

Run Simulation and


97/106


Display Results in OrCAD PSPICE

97

Plot Traces in OrCAD PSpice


98/106


Plot Tracesin OrCAD PSpice

98

3 6 2 SPICE Di d M d l


99/106


3.6.2 SPICE Diode Model

Nonlinear behavior of diode ismodeled by voltage

controlled current source iD

Model equation for iDincludes

ideal exponential diode

behaviorplus term that

accounts for carriergeneration in the depletion

regionof the diode

Junction Cjand diffusion CD

capacitancesare connected

in parallel

Series resistance Rsaccounting for finite

resistance of quasi-neutralregions


99

SPICE Di d M d li


100/106


SPICE Diode Model

ParameterECE3040

SymbolSPICE

Default

Value

Saturation Current IS IS 10 fA

Series Resistance Rs RS 0 %

Ideality Factor n N 1

Transit Time #t TT 0 sec

Zero-Bias Junction Cap. for unit area CjA CJO 0 F

Built-In Potential Vbi VJ 1 V

Junction Grading Coefficient M 0.5

Relative Junction Area RAREA 1

iD =

IS exp

vD

NVT

!

"#

$

%&'1

(

)**

+

,--

CD =TT

iD

NVT

for vD! 0

Cj =

CJO

1"vDVJ

#

$%

&

'(

M for v

D) 0

VT =

kT

q

100


101/106


Sample Problem Half-Wave Rectifier without Transformer

Voltage Source VSINAmplitude = 15 V

Frequency = 60 Hz

Offset = 0V

Ideal DiodeIS = 10 fA, N = 1RS = 0, Cj= CD= 0

Filter Capacitance

C = 20 mF = 20,000 $F

Load ResistanceR = 15 %

101

DC O tp t Voltage & C rrent


102/106


ioutput

DC Output Voltage & Current

DC Output Voltage: Vdc#14 V

DC Output Current: Idc#0.93 A

voutput

vinput

102

Di d C t


103/106


Diode Current

Peak Diode Current: IP#33 A

Diode Surge Current: ISC#115 A

ISC

IP

103

DC Output Voltage for C = 1 mF


104/106


DC Output Voltage for C = 1 mF

Modification: filter capacitance decreased from C = 20 mF to C = 1 mF

Increased ripple voltage due to reduced RC time constant

voutput

vinput

104

Diode with R = 0 1 #


105/106


ISC

IP

Diode with RS= 0.1 #

Modification: introduce diode series resistance RS= 0.1 %

Reduced IPand ISC; C only charged after several cycles

voutput

vinput

105

Diode with R = 0 1 #


106/106

ISC

IP

Diode with RS= 0.1 #

Modification: introduce diode series resistance RS= 0.1 %

Reduced IPand ISC; C only charged after several cycles

msb_chapter3+v2

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