Negative Bias Temperature Negative Bias Temperature Instability (NBTI)Instability (NBTI)

Physics, Materials, Process, Physics, Materials, Process, and Circuit Issuesand Circuit Issues

Dieter K. SchroderDieter K. SchroderArizona State UniversityArizona State University

Tempe, AZTempe, AZ

IntroductionIntroduction� What is NBTI?� Material Issues� Device Issues� Circuit Issues� Effect of

� Hydrogen� Nitrogen� Water� Fluorine� Deuterium� Boron� Stress

� NBTI Minimization

What Is NBTI?What Is NBTI?� Negative bias temperature instability occurs mainly in

p-channel MOS devices� Either negative gate voltages or elevated temperatures

can produce NBTI, but a stronger and faster effect is produced by their combined action� Oxide electric fields typically below 6 MV/cm� Stress temperatures: 100 - 250°°°°C � Drain current, transconductance, and

“off” current decrease� Absolute threshold voltage

increase� Such fields and temperatures

are typically encountered during burn in, but are also approached in high-performance ICs during routine operation 105

106

107

1970 1980 1990 2000

Eox

(V/c

m)

Year

Parametric ImpactParametric Impact� Material

� Interface traps, Dit

� Oxide charges, Not

� Device� Threshold voltage, VT

� Transconductance, gm

� Subthreshold slope, S� Mobility, µµµµeff

� Drain current, ID,lin, ID,sat

� Circuit� Gate-to-drain capacitance, Cgd

� Delay time, td

Device Lifetime LimitsDevice Lifetime Limits

� NBTI – key reliability issue

1

2

3

2 2.5 3 3.5 4 4.5 5

VD

D (V

)

Oxide Thickness (nm)

Hot Carrier Limit Region

SIA Roadmap

T=100oC

NBTI Limit Region

N. Kimizuka et al., IEEE VLSI Symp. 73 (1999)

MOSFET PerformanceMOSFET Performance

2)/1()2/( DDTDDoxeffD

DDd VVVCLW

CI

CVt−−−−

========µµµµ

� MOSFET drain current depends on� Dimensions: W, L, Cox ~ 1/tox

� Mobility: µµµµeff

� Voltages: VG, VD, VT

� Delay time: td

2)()2/( TGoxeffD VVCLWI −−−−==== µµµµ

ID � and td � if VT� and µµµµeff �

When device parameter change exceeds a certain value ���� failure

Earliest NBTIEarliest NBTI� Generation of fixed charge and interface states

with negative gate bias was observed very early during MOS development – in 1967!

0

1 1012

2 1012

3 1012

-3 106-2 106-1 1060 100

(111)(100)(111)(100)

(Qf+

Qit)

/q (c

m-2

)

Electric Field (V/cm)

T=300oCtox=200 nm

B.E. Deal et al., J. Electrochem. Soc. 114, 266 (1967)

Typical NBTI FeaturesTypical NBTI Features� Interface traps, Dit, and positive oxide charges,

Not, are generated at similar rates

otit ND ∆∆∆∆≈≈≈≈∆∆∆∆

0.1

1

10

0.1

1

10

100 101 102 103 104

Not

Dit

∆∆ ∆∆Not

(cm

-2)

∆∆ ∆∆Dit (cm

-2eV-1)

Stress Time (s)

VVTT, Transconductance, Transconductance� Charge pumping current Icp ~ interface state

density Dit

� Transconductance gm ~ effective mobility µµµµeff ~ Dit

10-1

100

101

102

103

101 102 103 104 105

- ∆∆ ∆∆V

T (m

V);

∆∆ ∆∆I c

p (p

A)

Stress Time (s)

W/L = 10 µµµµm/2 µµµµm

∆∆∆∆VT

tox=15 nm, T=135oC

VG=-8 V

∆∆∆∆Icp

C. Schlünder et al. Microelectron. Rel. 39, 821 (1999)

10-3

10-2

10-1

100

101

102

100 101 102 103 104- ∆∆ ∆∆V

T (m

V);

- ∆∆ ∆∆g m

/gm

oStress Time (s)

L=0.1 µµµµm, tox=2.2 nm

∆∆∆∆VT

VG=-2.3 V, T=100oC

∆∆∆∆gm/gmo

N. Kimizuka et al., IEEE VLSI Symp. 92 (2000)

Threshold VoltageThreshold Voltage

� Threshold voltage of p-channel MOSFETs decreases with stress time. Why?

0

2

4

6

8

10

10-3 10-2 10-1 100 101

- ∆∆ ∆∆V

T (m

V)

Stress Time (h)

W/L = 10 µµµµm/2 µµµµm

tox=15 nm, T=135oC

VG=-8 V

C. Schlünder et al. Microelectron. Rel. 39, 821 (1999)

ox

SF

ox

it

ox

oxMST C

QCQ

CQ

V ++++++++−−−−−−−−==== φφφφφφφφ 2

SiOSiO22 and SiOand SiO22/Si Interface/Si Interface

� Si, Si/SiO2 interface, SiO2 bulk, and oxide defect structure

This looksreally messy!

A: Si-Si Bond(Oxygen Vacancy)B: Dangling BondC: Si-H BondD: Si-OH Bond

Si

D

B

Hydrogen

A

C

+

+

+

+

+

Oxygen

Dangling Bond (Dit)

Interface TrapsInterface Traps� Si has 4 electrons� At the surface, Si atoms are

missing: Dit ~ 1014 cm-2eV-1

� After oxidation: Dit ~ 1012 cm-2eV-1

� After forming gas (H2/N2) anneal: Dit ~ 1010 cm-2eV-1

� Dit are energy levels in the band gap at the Si surface

� Hydrogen is very important?

NBTI MechanismNBTI Mechanism� A hole (h) is attracted to the Si/SiO2 interface� It weakens the Si-H bond until it breaks� The hydrogen (H) diffuses into the oxide or Si

substrate� If H diffuses into the Si, it can passivate boron ions

� Leaves an interface trap (Dit)

Holes Are The Problem !Holes Are The Problem !

J = 2.25x104 A/cm2

P. Nguyen, ASU

ElectromigrationVia Electromigration

T.S. Sriram and E. PiccioliCompaq

40 µµµµm

L. Wagner, IRPS 2004

Flip Chip Voiding

W plugt = 38 h

10 µµµµm

10 µµµµm

G. Dixit, IRPS 2004

Cu Voids

Chip Delamination

L. Wagner, IRPS 2004

K. Tu, UCLA

Solder Bump EMp+ p+

n-type

Interface Trap ChargeInterface Trap Charge� Band diagrams of the Si substrate of a p-channel MOS

device shows the occupancy of interface traps and the various charge polarities for an n-substrate

� Acceptor with electron: negative charge� Donor without electron: positive charge

� (a) negative interface trap charge at flat band � (b) positive interface trap charge at inversion

(Heavy line: interface trap occupied by an electron; light line: unoccupied by an electron)

EV

EC

Ei

EF

"0"Acceptors

EV

EC

Ei

EF

Dit

Donors "0"

"-" "0""+"

"0"

(b)(a)

Threshold VoltageThreshold Voltage� Nit and Nf ≈≈≈≈ 1010 cm-2; 0.1 µµµµm x 1.0 µµµµm gate (A = 10-9 cm2),

there only 10 interface traps and 10 fixed oxide charges at the SiO2/Si interface under the gate ���� ∆∆∆∆VT

� For tox = 5 nm ���� ∆∆∆∆VT ≈≈≈≈ -5 mV. For ∆∆∆∆VT = -50 mV, device failure ���� ∆∆∆∆Nit = ∆∆∆∆Nf = 1011 cm-2

� Suppose that in a matched analog circuit, one MOSFET experiences ∆∆∆∆VT ≈≈≈≈ -10 mV and the other ∆∆∆∆VT ≈≈≈≈ -25 mV. This 15 mV mismatch in a VT = -0.3 V technology ���� 5% mismatch. High performance analog transistor pairs that require mismatch tolerances of 0.1% to 0.01%.

oxoxoxooxox

fitT txt

xxxx

tAK

qC

QQV 3

913

19

102.9101045.320106.120 −−−−====−−−−====−−−−====++++−−−−====∆∆∆∆ −−−−−−−−

−−−−

εεεε

Reaction Reaction –– Diffusion ModelDiffusion Model� Holes interact with Si-H bond� Holes weaken Si-H bond� At elevated temperature, the Si-H bonds dissociate

� Initially� Dit generation ~ Si-H dissociation rate (reaction limited)

� Later� Dit generation ~ hydrogen diffusion rate (diffusion limited)

++++++++ ++++••••≡≡≡≡→→→→++++≡≡≡≡ HSiSihSiHSi 33

M.A. Alam, IEDM, 2003; IRPS 2005

Reaction Reaction –– Diffusion ModelDiffusion Model

)0()( ====−−−−−−−−==== −−−− xNNkNNkdt

dNHitritHSif

it

H-Si

-VGn-Si

-VGn-Si

0 n-Si

H -SiH-Si

H-SiH -Si

H -Si

H-SiH -Si

H -SiTime

Th

resh

old

Vol

tag

e

Reaction

Diffusion

Hydrogen ModelHydrogen Model� Hydrogen from Si substrate drifts to SiO2/Si

interface � Ho near/at SiO2/Si interface traps a hole ���� H+

� H+ depassivates Si-H bond ���� Dit and H2

� Some H+ drifts into SiO2 ���� Not

233 HSiSiHSiHSi ++++••••≡≡≡≡����++++≡≡≡≡ ++++

D.M. Fleetwood et al. Appl. Phys. Lett. 86, 142103 (2005)

Device DependenceDevice Dependence

TG

T

linD

linD

DDTGlatD

oxefflinD

VVV

II

VVVVLVLCW

I

−−−−−−−−====����

−−−−−−−−++++

====

δδδδδδδδεεεε

µµµµ

,

,

, )2/(/1

/

TG

T

satD

satD

nTGoxsat

satTG

TGoxsatsatD

VVV

nII

VVCWvLVV

VVCWvI

−−−−−−−−====����

−−−−≈≈≈≈++++−−−−

−−−−====

δδδδδδδδεεεε

,

,

2

, )()(

L dependence� Long channel: n ≈≈≈≈ 2, short channel: n ≈≈≈≈ 1� Hence long channel degradation worseID dependence� ID,sat worse than ID,lin due to n

Device DependenceDevice Dependencetox dependence� With scaling, tox ���� and VG-VT (headroom) ����� Hence thin oxide degradation worse for same VT

µµµµeff dependence

� For same VT, as tox ���� δδδδDit ����, ���� µµµµeff ����

� Hence mobility degradation worse for thin oxides

itit qDC ==== oxoox

it

ox

itT t

KDq

CDqV

εεεεδδδδδδδδδδδδ ========

How Can This Be ?How Can This Be ?� The lower picture is after the parts are moved� Where does the missing hole come from?

Effect on CircuitsEffect on Circuits

Inverter Vin Vout n-MOS p-MOSBias Stress Stress

1 VDD 0 V PBTI Off State

2 0 V VDD Off State NBTI

VDD

VSS

VinVout

Time

V(t

)Vin(t) Vout(t)

p-MOSNBTI

CMOS Inverter DegradationCMOS Inverter Degradation

0.1

1

10

0 1000 2000 3000 4000 5000- ∆∆ ∆∆

VT

(mV

)

Stress Time (s)

p-MOS NBTI

T=105oC

|VG |= 2.8 V

n-MOS Off State

n-MOS PBTIp-MOS Off State

� p-MOS NBTI degradation is dominant degradation mechanism during static inverter stress

V. Reddy et al. IEEE 40th Ann. Int. Rel. Symp., 248 (2002)

Effect on CircuitsEffect on Circuits

� Occurs primarily in p-channel MOSFETs with negative gate voltage bias and is negligible for positive gate voltage

� In MOS circuits, it occurs most commonly during the “high” state of p-channel MOSFETs inverter operation

� Leads to timing shifts and potential circuit failure due to increased spreads in signal arrival in logic circuits

� Asymmetric degradation in timing paths can lead to non-functionality of sensitive logic circuits ���� product field failures

Circuit DependenceCircuit Dependencetd dependence

� Circuit delay degrades with VT increase� ISCAS C423: 10% after 10 yrs*

CGD dependence� With stress, Dit ����, Cit ����, ���� CGD ����

� Important for analog circuits (Miller effect)

TG

T

d

d

D

DDd VV

Vn

tt

ICV

t−−−−

====����==== δδδδδδδδ

A.T. Krishnan et al., IEDM 14.5.1, 2003

Operating Voltage

Dra

in C

urr

ent

Sh

ift Headroom

Limited (VG - VT)-1

DegradationLimited (δδδδVT)

������������

����������������

−−−−====

0

25.0

expEE

EVV

Kttt ox

oxTGd

dδδδδ

* B.C. Paul et al., IEEE Electron Dev. Lett. 26, 560 (2005)

Circuit DegradationCircuit Degradation

� VT shifted model captures only ~60% (20%) of the degradation for digital (analog) circuits

����������� ����

����

����

������������������

�����������

���������������� �

!��"#�����$� ��������

�$%�%����

���

����#�&�������%��'(���

��

VTShifted Model

Model

-1.0%

Change in Unity Gain Bandwidth

(Analog)

-3.2%Channel charge

RO Frequency

Degradation (Digital)

Accounts for NBTI impact

on

�������������������� ��)� �*����

$� ���������%+������ -1.3%-4.5%Channel charge

+ MobilityDegraded I+ V only

+,-,+,-.������������ ��)� �*�����)�

��$

%���#��� ���$

$� �������-4.4%-4.9%

Channel charge + Mobility +

�GD

Including �GD

Degradation

A.T. Krishnan IRPS 2004

Circuit DegradationCircuit Degradation� Degradation in digital circuits

� FPGA performance� Ring oscillator fmax

� SRAM static noise margin� Microprocessor

� Degradation in analog circuits� Current mirror� Operational amplifier

DC Versus AC StressDC Versus AC Stress� Stress creates interface traps

( ) � Dit generation

� Initially determined by Si-H dissociation rate

� Later determined by hydrogen diffusion from interface

� When stress is terminated hydrogen diffuses back� Interface traps are passivated

� dc: Dit generation� ac: Dit generation, passivation

M.A. Alam, IEDM, 2003

ac stress leads to reduced degradation!

••••≡≡≡≡ SiSi3

Damage RelaxationDamage Relaxation

� When stress is terminated, degradation relaxes� For sufficiently long times, all damage is “healed”� Important to indicate the time between stress

termination and NBTI measurements

� Threshold voltage� Drain current� Transconductance� Interface traps� Mobility

9

11

13

15

17

10-3 10-2 10-1 100 101 102 103

∆∆ ∆∆ID

lin (%

)

Recovery Time (s)

T=125oC

Recovery 1 ms after stress termination

S. Rangan et al., IEDM, 2003

Damage RelaxationDamage Relaxation� For sufficiently long recovery time, damage

disappears� Temperature dependent� Higher temperature, less recovery

� Hydrogen diffuses further from SiO2/Si interface and is not available during recovery

� If hydrogen diffuses all the way to the poly-Si gate, it may “disappear”

S. Rangan et al., IEDM, 2003

0

0.4

0.8

10-3 10-2 10-1 100 101 102 103 104

Frac

tion

Rem

aini

ng

Recovery Time (s)

T=125oC

Stress and recovery temperatures equal

T=-40o, 25oC

DC Versus AC StressDC Versus AC Stress

� Dynamic stress ���� lifetime ����� Transistors in circuit switch

at different frequencies� Some transistors may not

switch out of NBTI state� Could increase mismatch

between paths switching at different rates

1

10

100

1000

100 101 102 103 104 105 106Life

time

Enh

ance

men

t

Frequency (Hz)

Duty cycle: 25%

T=125oCtox=1.8 nm

50%

75%

103

105

107

109

1011

1013

1015

-2.5-2-1.5-1-0.5

D-InvD-UnipolarD-Bipolar

Life

time

(s)

Gate Voltage (V)

f=100 kHzT=125oCtox=1.8 nm ττττ @ ∆∆∆∆VT=30 mV

S.S. Tan et al. IRPS, 35 (2004)

Effect of HydrogenEffect of Hydrogen� Hydrogen commonly used for interface trap

passivation (~400-450°°°°C, 20-30 min)� Hydrogen can exist as

� Atomic hydrogen H0

� Molecular hydrogen, H2

� Positively charged hydrogen or proton, H+

� Part of the hydroxyl group, OH� Hydronium, H3O+

� Hydroxide ions, OH-

� Hydrogen is believed to be the main passivating species for Si dangling bonds and plays a major role during NBTI stress, when SiH bonds are depassivated ���� interface traps

Effect of NitrogenEffect of Nitrogen� Nitrogen may improve or degrade NBTI � NBTI enhanced by nitrogen� Nitrogen lowers activation energy� Nitrogen profile affects impact

� Lower N at interface is better� Plasma nitridation gives least NBTI

106

107

108

109

1010

1011

2 3 4

Life

time

(s)

1000/T (K-1)

VG=-1.2 V, tox=2.2 nm

Low Nitrogen

10 Years

SiO2

HighNitrogen

N. Kimizuka et al., IEEE VLSI Symp. 92 (2000)

Effect of NitrogenEffect of Nitrogen� Grow thermal oxide� NO anneal or plasma

nitridation� Reduced gate leakage

current (same oxide thickness)

� Similar reliability� Improved NBTI with

plasma nitridation� Improves both digital

and mixed-signal performance

0.01

0.1

1

10

100 101 102 103 104

∆∆ ∆∆ID

sat (

%)

Stress Time (s)

Plasma Nitrided Oxide

tox=6 nm

T=125oCVG=-3.6 V NO Annealed

0

2 1021

4 1021

6 1021

8 1021

1 1022

0 0.5 1 1.5 2 2.5 3

Nitr

ogen

(cm

-3)

Depth (nm)

Plasma Nitrided Oxide

tox=3 nm

NO Annealed

B.Tavel et al., IEDM, 2003

Effect of NitrogenEffect of Nitrogen

B.Tavel et al., IEDM, 2003

Effect of WaterEffect of Water� Water in the oxide enhances NBTI� Dit and Qox increases are observed in damp and wet

oxides; diffusion species is water� Wet H2-O2 grown oxide to exhibit worse NBTI than dry

O2 grown oxides � Water is often present on wafers from contact and via

formation� Water and moisture mostly travel along interfaces� Water-originated reaction has lower energy at the

Si/SiOxNy interface than at the Si/SiO2 interface���� NBTI is enhanced by water incorporation in oxide

Effect of FluorineEffect of Fluorine

� Fluorine improves NBTI� “Hardens” SiO2/Si interface� Fluorine is believed to relieve strain at SiO2/Si

interface

T.B. Hook et al., IEEE Trans. Electron Dev. 48, 1346 (2001)

0

0.2

0.4

0.6

0.8

1

0 1 1014 2 1014 3 1014 4 1014 5 1014

Nor

mal

ized

∆∆ ∆∆V

T

Fluorine Dose (cm-2)

tox=3.5 nm

tox=6.8 nm

FluorineFluorine� Incorporation of fluorine atoms

into SiO2 improves QBD

� SIMS and Fourier transform infrared spectroscopy ���� strained layers are localized near the SiO2/Si interface

� Fluorine releases the distortion of the strained Si-O bonds

� Fluorine diffuses into gate-oxide � React with the strained Si-O bonds

and release the distortion� Released oxygen atoms re-oxidize

the Si-SiO2 interface� Forms Si-F instead of Si-H bonds� Si-F bond stronger than Si-H bond

Y. Mitani et al. “Improvement of Charge-to-Breakdown Distribution by Fluorine Incorporation Into Thin Gate Oxides,” IEEE Trans. Electron Dev. 50, 2221, Nov. 2003

F

FF

FF

F

OSi Si

O

Si Si

O

Si Si

OSi Si

F F

StrainedSi-O Bond

StrainRelease

ReOxidation

Poly-SiGate

SiO2

Si

SiSi

FH

Effect of DeuteriumEffect of Deuterium� Hot carriers degrade devices through: interface state

generation, oxide charge trapping, mobility/transconductance degradation

� Post metallization anneal (~450°C/30 min): forming gas or hydrogen

� Si-H bonds form at SiO2/Si interface

� Si-H bonds easy to form, but also easy to break

� Si-D bonds are stronger (D: deuterium is a stable isotope of hydrogen with natural abundance of 0.0015%)

� Hot carrier resistance enhanced by D2

W. F. Clark et al., IEEE Electron Dev. Lett. 20, 501 (1999)

100

101

102

103

104

105

106

10-6 10-5 10-4

H2: 1st Level MetalH2: 5th Level MetalD2: 1st Level MetalD2: 5th Level MetalLine FitLine Fit

Life

time

(s)

Substrate Current (A/µµµµm)

5% ID,sat Degrad.

Deuterium

Hydrogen

Effect of DeuteriumEffect of Deuterium� Deuterium improves NBTI� A “heavy” variant of

hydrogen� Stable isotope of

hydrogen containing a proton as well as a neutron in its nucleus

� Due to its heavier mass, Si-D bonds are more resistant than Si-H bonds to hot carrier stress as well as NBTI

1

10

100

101 102 103 104

- ∆∆ ∆∆V

T (m

V)

Stress Time (s)

Dry Oxidation

D2 PMA

tox=3.8 nm, T=150oCVG = -2.9 V

H2 PMA

Effect of Oxide ThicknessEffect of Oxide Thickness

� VT shift, ∆∆∆∆VT, depends on oxide thickness� ∆∆∆∆VT ~ tox for same interface trap density

-3

-2

-1

0

1

2

3

-0.5 -0.4 -0.3 -0.2 -0.1 0

Nor

m

VT (V)

tox=1.5 nm

T=125oCE=10 MV/cmW/L=5/1 µµµµm

Before StressAfter

M. Agostinelli et al., IRPS, 171 (2004)

-3

-2

-1

0

1

2

3

-0.5 -0.4 -0.3 -0.2 -0.1 0

Nor

m

VT (V)

tox=5 nm

T=125oCE=10 MV/cm

W/L=4/0.5 µµµµm

Before StressAfter

oxoox

it

ox

itT t

KqN

CQ

Vεεεε

========∆∆∆∆

Effect of BoronEffect of Boron

� Boron degrades NBTI � Boron diffuses into the

gate oxide from the boron-doped gate and from the source/drain implants � Reduced Dit due to Si-F

bonds from the BF2 boron implant

� Enhanced Qox due to increased oxide defects due to boron in the oxide

100

101

102

103

104

105

106

0 0.2 0.4 0.6 0.8 1 1.2

Life

time

(Yea

rs)

Gate Length (µµµµm)

tox=6.5 nm

With B Penetration

Without B PenetrationT=100oC

Yamamoto et al. IEEE Trans. Electron Dev. 46, 921 (1999)

NBTI MinimizationNBTI Minimization

� Have initially low densities of electrically active defects at the SiO2/Si interface and keep water out of the oxide

� Silicon nitride encapsulation layer has been found effective in keeping water away from the active CMOS devices, improving NBTI performance

� Minimize stress and hydrogen content � Keep damage at the SiO2/Si interface to a minimum during

processing� Plasma damage degrades NBTI in p-MOSFETs, but not

n-MOSFETs� Deuterium improves both hot carrier stress and NBTI � Important to ensure deuterium can get to the SiO2/Si

interface and passivate dangling bonds or replace the hydrogen with deuterium in existing Si-H bonds

NBTI MinimizationNBTI Minimization� Nitrogen incorporation has given conflicting

results. Some authors claim an NBTI improvement, while others observe degradation

� The method and chemistry of oxide growth has significant effects on NBTI

� Wet oxides show worse NBTI degradation then dry oxides

� Fluorine leads to an improvement. F in the gate oxides can significantly improve NBTI and 1/fnoise performance

� Boron degrades NBTI� Oxide electric field important

SummarySummary

NBTI � Can be a significant contributor to p-MOSFET

degradation in submicron devices� Needs to be considered during optimization

between device reliability and circuit performance

� Sensitive to a variety of process parameters, e.g., hydrogen, nitrogen, fluorine, boron, etc.

� Can occur during burn in� Can occur during circuit operation at elevated

temperatures

What Is It?What Is It?