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Nexray

A. DommannA, H. von KnelC, P. GrningB, N. BlancA, C.A. BosshardA,

A.D. BrenzikoferA, F. CardotA, S. GiudiceA, R. Jose JamesA, R. KaufmannA,

C. KottlerA, C. LottoA, C. FalubC, A. NeelsA, G. Spinola DuranteA ,

B. BatloggC, E. MllerC, P. WgliC, K. MattenbergerC, P. NiedermannA,

P. SeitzA, C. UrbanA, H.R. ElsenerB, O. GrningB

A: CSEM; B: EMPA, C: ETHZ

Bern, 29. 4. 2010

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A system approach

Source Sample Detector

Contrast mechanism Resolution, Size, EfficiencySpectrum, power,Coherence, Size

Miniaturized, fastand programmableX-ray sources

Phase contrast X-ray imaging

Direct X-raydetectors

Breakthroughs in all key building blocks of X-ray systems:

Sources, Contrast mechanism and Detectors

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Novel Concepts of Applications

Large area X-ray sources

Pixelated X-ray sources

Pulsed operation of X-ray source (and individual source-pixels)

Highly efficient sensors, applicable in medical diagnostics

Energy resolved X-ray image detection

Detector

Source

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Medicine and Nondestructive Testing

Static CT for emergency medicine

Miniaturised X-ray systems for monitoring purposes during

surgery, e.g. for cardiovascular or brain surgeries

Large area sources for radiation therapies

Fast static CT for in-line product inspection

Imaging of fast phenomena due to high switching frequency of

cold electron emitters

Depth measurements inside objects due to TOF operation mode

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Network of integrated miniaturized X-ray systems operating in

complex environments

Single-photon solid-

state X-ray detection

Si-Ge layers for high-

energy X-ray detectionPhase contrast X-ray imaging

Miniaturized, fast and

programmable X-ray sources

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Schematic Overview

100m

20m Au coating

400m

Pt

Si

SiO2 (2m)

Au

Si

Diamond window

e-

e-

Metal anode

X-ray

CNT

Pyrex glass

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X-Ray source

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X-ray source experimental platform: The concept

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Layout of cathode and grid chips

10 x 20 mm chips

Cathode:

50 m deep cavity (with Mo pad)

for nanotubes

Under-bump metal (UBM) ring for

sealing

Grid:

Grid area: 2 x 2 mm

Grid line width 10, 20 and 30 m

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Silicon chips for cathodes

For development of high

vacuum hermetic packaging

Different variants of Pt and

Au based UBM metal stacks

2 wafer runs

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Microfabricated grids

Fabricated from silicon-on-insulator (SOI) wafers

Height of Si grid lines: 30 m

Deep reactive ion etching (DRIE) for gridlines

Anisotropic wet etching (KOH) for openings in support chip

Dicing

Metallization

Si device layer

Si handle wafer

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Microfabricated grids

Diced wafer

2 x 2 mm grid

10 m grid lines

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Approaches to sealing : AuSn soldering

UBM Tests:

Initial tests with Ta/Pt shows very low adhesion of Ta on substrate but no

voids observed

Cross section of the sealing ring

SEM picture

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Leak testing concept

Integration of a vacuum sensor (Resonator, Pirani,) in a ceramic package

Purpose

Testing the hermeticity of the sealing Checking the getter integration and activation

Compatibility with the bonding temperatures

300-320C for AuSn solder

320 to 450C for glass solder

Possibility to integrate CNT

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Carbon nanotube cold emitter electron sources

Cathode technology based on carbon nanotubes Best available technology for FE-Displays

but not applicable for high temperature processes Paste low cost technology for large surfaces, e.g. screen printing technology Limited outgassing due to choice of material and high temperature annealing

After high temperature annealing and surface treatment

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Characterisation of the base material: SEM

Delivery condition: - in powder form, agglomerated CNTs ball of wool

- kept together by van-der-Waals forces- electrostatic charged / chargeable- difficult handling in dried state

Chemical and/or mechanical treatment is necessary

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Separating of CNT:Suspension

"black ink" / ink with binder

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Paste preparation

Clay mineral

CNT Suspension

Mixing of CNT, binder and filler with a ceramic rolling-mill

High shear forces the interlayer of clay mineralwill be filled with CNT suspension (if CNT diameter is

small enough)

Al

HO

Siceramic rolling-mill

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Manufacturing of the cathode

Coating:Application of CNT paste on specific substrates(thickness 100 200 m)

Drying @ RT

Heat treatment in protection gas and vacuum furnace Decomposition of volatile organic binders Melting of inorganic binders

Reaction of CNT with the non-volatile matrix

Surface treatment- e.g. grinding paper / ultrasonic treatment- cleaning

Characterisation- visual: ESEM- electronic: field emission characteristic [ nanotech@surfaces]

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High temperature resistant CNT cathode (T = 880 C)

- good adhesion on the substrate

- field emission after integration in x-ray tube

Free carbon nanotubes

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mission characteristics: longtime-stability

Applied elec. field

20, 100, 500 A

ngtime measurement: 13 histance: 20 m

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system approach



iniaturized, fastnd programmable-ray sources

Phase contrast X-ray imaging

Direct X-raydetectors

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hy is Ge a Good X-ray Detector Material?

xisting detectorsike e.g. Medipixr Dectris/Pilatus

ompeting material

or future detectors

ommonly usedcintillator

e is competitive inwide energy range

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oblems related to Si:Ge Epitaxy

TICE MISMATCH (aSi = 0.543095 nm, aGe = 5.564613 nm a/a = 4.2 % compressive)

T

M

% Si

Ge

Only 4 monolayers of Ge (~ 2.2. nm) can be grown epitaxially on Si !

Plastic Deformation (i.e. relaxation) by misfit (M) and threading (T) dislocations: bad quality

ined Ge on Si substrate

strained

Ge

bulk Si

aSi

a=aSi

relaxed

Ge

bulk Si

Misfit

ed SiGe on Si substrate

0

a0

Threadingdislocations

Threading

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lems related to Si:Ge EpitaxyICE MISMATCH (aSi = 0.543095 nm, aGe = 5.564613 nm a/a = 4.2 % compressive)

TION Dislocations can be reduced by cycling thermal annealing

Cycling thermal annealing

Deposition

Outgasing

Cooling

-3000 -2000 -1000 0 1000 2000 3000

100

101

102

103

104

1 m Ge @ 7.4 nm/s, 500 C

Ge(004)

600-850 C, 6x600 sno annealing

Intensity

[c/s]

[arcs]QII

FWHMII

scan

Time [s] 9000

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onolithic Integration on CMOS Wafers Demonstrated

Monoli thic integration ofGe photodetectors on CMOS demonstrated

for infrared applications (2 m layer thickness)

64 x 64 pixel NIR image sensor exists

Optimisation of process is going on

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RD Analysis of Ge on CMOS Photodiodes

- -0

100000

200000

300000

400000

Intensity

(counts)

32.9975 (), 466100.9 (counts)

0.0457 ()

FWHM = 0.0457(164 arc sec)

Si 004

Ge 004

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mple-Image of Infra-Red Image Sensor

Illumination at 1250 nm

(bandwidth 10 nm)

No cooling, no optics

Demonstrator camera

in preparation

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NOVATION: Selective Epitaxy on pre-patterned Si

view

Side view

Top viewGrooves Pillars

PillarsGrooves

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8 m Ge pillars on Si (7.4 nm/s, 500 C)

Top view

Side view

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Si GeDislocations

STEM and TEM 8 m Ge pillars on Si (7.4 nm/s, 500 C)

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20 m Ge pillars on Si (7.4 nm/s, 500 C)

Top SEM view

Side SEM view

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00

00

00

00

00

00

00

00

ts/s

Omega 33.750002Theta 67.50000

Phi 0.00Psi 0.00

X 4.00Y 0.00

Patterned:fullyrelaxed

Unpatterned

Si(004)

Ge(004)

Omega / 2Theta scans on Si/Ge(004)

Patterned:Si in pillarsSlightly strained

ple #56558on Ge @ 500 C & 2.2 nm/s followed by 6 x 600 sec 600-850 Cg annealing + 7 microns Ge @ 500 C & 7.4 nm/s

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ple #56558

Patterned Unpatterned

32.9 33.0 33.1 33.2 33.3 0

00

00

00

00

00

00

00

00

00

ts/s

Patterned:Ge fullyrelaxed

Unpatterned:

Ge partially strained

Ge(004)

Ge partially strained

SiGe(gradient,interface)

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7015

7065

7115

7165

7215

7265

7315

7365

0000(rlu)

7050

7100

7150

7200

7250

7300

7350

7400

2. 1

3. 1

4. 7

7. 2

10. 9

16. 4

24. 9

37. 7

57. 1

86. 5

131. 0

198. 4

300. 5

455. 1

689. 3

1043. 9

1581. 0

2394. 4

3626. 2

5491. 8

Unpatterned:

Sample #56558

RSMs on Ge/Si(004)

Relaxed GeTilted: 1.2(each direction)

xx

patterned:

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Sample #56560RSMs on Ge/Si(004) and Ge/Si(115) measured on patterned part of the wafer

-100-50 0 50 100Qx*10000(rlu)

7050

7100

7150

7200

7250

7300

7350

7400

Qy*10000(rlu)

Relaxed Ge

2400 2450 2500 2550 2600 2650 2700Qx*10000(rlu)

8800

8900

9000

9100

9200

Qy*10000(rlu)(115) (004)

Si-Substrate

Patterned:Very small mosaicity. No tiltcompared to #56558.

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Photon Counting Circuits

Cs

Rr

sense

node

X-ray quantum counting:

Every single X-ray photon is counted

Test-chip exists

Low noise circuit with band-pass filtering

Measured noise limit of 12 e- RMS

at 1 s pulse length

X-ray energy resolution possible

with pulse-height measurements

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A system approach



Miniaturized, fast

and programmableX-ray sources

Phase contrast X-

ray imaging

Direct X-ray

detectors

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Set-up: hutch, overview

Door of hutch(x-ray shielding)

PCI set-up

Sample manipulation

X-ray tube

Grating interferometer

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Set-up: gratings

G2 grating on 100mm wafer G0 grating mounted on holder

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Dete

ctor

l

d

G0

G1 G2

p0

p1p2

sou

rce

x

zy

Talbot-Lau

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Cherry

amp dpc dci

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Webpage

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nexray 2010

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