ohp cmos 5(h20-5-9) - rnbs.hiroshima-u.ac.jph20-5-9).pdf · mattausch, cmos design, h20/5/9 3...

Mattausch, CMOS Design, H20/5/9 1

CMOS Layout

• Purpose of the Layout• Layout Layers and Layout-Design Rules • Layout of Logic Gates• Generation Methods of Integrated-Circuit Layouts

CMOS Logic Circuit Designhttp://www.rcns.hiroshima-u.ac.jp

Link（リンク）: センター教官講義ノートの下 CMOS論理回路設計


Purpose of the Layout- Summary of the main functions

of the layout- Example: Layout of the inverter


Summary of the main functions of the layout

The layout is the interface between the designed CMOS logic circuit and the CMOS fabrication technology.

1) Specification of the fabrication-process information for the designed circuit

2) Standardized interface for a specific CMOS fabrication process

3) Optimization of the yield (functional-chips/total-chips per wafer) forthe fabricated CMOS logic circuit

4) Securing of the reliability of the fabricated CMOS logic circuit

5) Data-base for estimating circuit performance including the parasiticelements of the fabrication process


Example: Layout of the Inverter

The layout determines the 3-dimensional physical structure of fabricated chips, implementing chip designs in hardware.

Layout of CMOS-Inverter Circuit

In Out

VDD

VSS

CMOS Inverter CircuitVDD VSS

In

Out

n-well

p-substrate

n+ n+n+ p+ p+ p+

VDD VSSOut InIn

Schematic Cross-section of Fabricated CMOS-Inverter Circuit

Cro

ssec

tion

line


Layout Layers and Layout-Design Rules

- Well- Active (or Diffusion)- Polysilicon- Contact- Metal- Higher Metal Layers


Construction and Dimension of the Well

The well provides the substrate for construction of one of the two transistor types. Typical are p-doped wafer and n-well.

Dimensions/Structure of Chip with n-WellTop-View of a Chip

Chip

1-400mm

1-40

0mm

Side-View of a Chip

1-400mm

100-800µm

n-well

p-type epi layer (p-)

p-type substrate (p+)

100-

800µ

m ~3µm

~1µm

Normal Drawing without Epi-Layer

n-well

p substrate

Side-View

with Well


n-Well Design Rules and CMOS-Circuit Functions

The n-well is used in CMOS circuits as p-MOS transistor substrate and for high-value ohmic resistors.

n-Well Design-Rules for a 0.25µm Process

Transistor Substrate

Resistor

n-well

p substrate

gatesource drain

n-well

p substrate

resistor lead

resistor lead 1.2

1.1

1.1: Min. Width = 1.2µm

1.2: Min. Space = 1.2µm


Construction and Functions of p- and n-Active

Normal application of active (or diffusion) is as source/drain of MOS-transistors and as substrate/well contacts.

The “active” region normally forms Source/Drain of MOS-Transistors

(p-MOS in n-Well n=MOS in p-Substrate)

Active is also used to contact n-well to VDD and p-substrate to VSS

n-well

p-substrate

n+ n+p+ p+

n-well

p-substrate

n+ p+

VDD VSS

n-well

p-substrate

n+ p+

Cathode Anode

n-well

p-substrate

n+ p+

Base Collector

p+

Emitter

Special Application with n-Well : Bipolar transistor

Special Application with n-Well : Diode


Design Rules for the Active (Diffusion) Layers

The design rules for active layers include minimum values for width and space as well as overlap and distance to the well.

Active Design-Rules for a 0.25µm Process

Design-Rule Types

2.1: Min. Width = 1.2 µm

2.2: Min. Space = 1.2 µm

2.3: Min. Space of n+ to Well = 1.2 µm

2.4: Min. Space of p+ to Well = 1.2 µm

2.5: Min. Well Overlap of n+ = 0.6 µm

2.6: Min. Well Overlap of p+ = 0.6 µm

2.2

2.1

2.2

2.1

2.2

n-well

n+ n+p+ p+

2.4p+

2.3n+

2.6 p+2.5n+

2.2


Usage of Polysilicon (or Poly) and Design Rules

Typical applications of Poly are MOS-transistor gates, short interconnections and medium scale resistors.

Poly-design rules (0.25 µm Process)

Formation of MOS-transistor gate(Active/poly-overlap region becomes MOS-gate)

n+ n+ p+ p+

n-well

n-MOSgate

p-MOSgate

Formation of poly resistor

3.1: Min. Width = 0.25 µm3.2: Min. Space = 0.4 µm3.3: Min. Poly Overlap of Active = 0.3 µm3.4: Min. Active Overlap of Poly = 0.4 µm3.5: Min. Space Active to Poly = 0.2 µm

3.3

3.2 3.1

3.4

3.5

n+


Metal_1 Layer and Contact Layer Design Rules

Metal_1 is mainly used for connecting active CMOS devices.The contact layer allows connecting metal_1 to poly or active.

Contact design rules for a 0.25µm process

Metal_1 Design Rules for a 0.25µm process

Application of metal_1 and contact

4.1: Min. Width = 0.4 µm4.2: Min. Space = 0.4 µm

4.1

4.2

n+

5.2

5.1

5.5

5.3

5.4

5.6

5.7

5.1: Size (fixed) = 0.3µm5.2: Min. Distance = 0.5µm5.3: Min. Poly Overlap of Contact = 0.1µm5.4: Min. Active Overlap of Contact = 0.1µm5.5: Min. Metal_1 Overl. of Contact = 0.1µm5.6: Min. Distance Contact to Active = 0.1µm5.7: Min. Distance Contact to Gate = 0.1µm

n-well

p-substrate

n+n+ p+

VDDSignal InterconnectMOS-Gate

(Contact not allowed)

WFieldoxide

Metal1/Poly Isolation


Transistor Layout in CMOS

Large transistors are constructed by extended poly/active-overlap length and/or by parallel connection of transistors.

Layout of a large-width n-MOS transistor

Typical n-MOS transistor layout

Typical p-MOS transistor layout

W

L

W

L

W/4

L L L L

gate

source

drain


Higher Metal Layers (Metal_2, Metal_3, …)

Higher metal layers are provided for easily interconnecting the different parts of a CMOS integrated circuit.

Metal_2 and VIA-hole design rules for a 0.25µm process Schematic cross-section including

a metal_2 interconnect

6.1: Min. Width = 0.6µm6.2: Min. Space = 0.6µm6.3: VIA Size (fixed) = 0.5µm6.4: Min. VIA Distance = 0.8µm6.5: Min. Metal_2 Overlap of VIA = 0.3µm6.6: Min. Contact Distance to VIA = 0.0µm

6.16.2 6.3

6.46.6

6.5

n-well

p-substrate

n+

n+

p+

Signal Interconnect for longer Distances

W

Flat Isolation Surface by CMP (CMP=chemical mechanical polishing)


Layout of Logic Gates- Inverter with Realistic Transistor Sizes- NAND Gate


Inverter Layout with Realistic Transistor Sizes

Different CMOS layout styles exist, which have advantages and disadvantages. Application depends on the design task.

Layout Style 1: Gates parallel to data flow

In Out

VDD

VSS

CMOS Inverter CircuitVDD VSS

In

Out

VDD VSSIn

Out

Layout Style 2: Gates vertical to data flow


Layout of the NAND Gate

The most efficient gate-layout is achieved, if one n-active for all n-MOSFETs and one p-active for all p-MOSFETs is found.

VDD VSSIn 1

Out

In 2

VDD VSSIn 1

Out

In 2

Efficient 2-input NAND layout(One p-active for all p-MOS and one n-active for all n-MOS transistors)

Inefficient 2-input NAND layout(All MOS-transistors have a separate

active region)


Generation Methods for Integrated Circuit Layouts

- Overview- Pre-Designed Method (Cell Based)- Pre-Manufactured Method (Array Based)


Overview of Layout-Generation Methods

A layout-generation method is chosen according to design requirements for speed/ease or compactness/performance.

1) Full-Custom Layout- Every transistor in the circuit is drawn by hand- Compact and efficient layout, but time consuming

2) Semi-Custom Layout- Pre-designed cells for different functions (Standard-Cell Method)- Fixed layout up to the metal layer (Gate-Array Method)- Allows automated layout generation

3) Fixed Layout- Completely pre-designed layout of the complete chip (FPGA method)

- The function is defined by changing wire connections (fuse-based, memory-based)


Semi-Custom Layout (Pre-Designed Stand. Cells)

The cell-based semi-custom-layout method is today the most widely used CMOS logic design method.

Cell-basedSemi-custom

layout

Standard-cell part

Example of apre-designedstandard cell


Fixed Layout (Programmable RAM-based FPGA)

FPGA (field programmable gate array) is mainly used for designs fabricated in small numbers or for rapid prototyping.

Fixed and programmable

layout structure

Detailed structureof the XILINX FPGA

CLB = Combinational Logic Block


Logic-Block of RAM-Based Programmable FPGA

The combinational logic block of a memory-based FPGA (field programmable gate array) is a very complex circuit.

Logic-block of theXILINX XC3000 FPGA

- combinational logic realized with memory-based look-up-table (LUT)

- all 5-input logic functions possible- some logic functions with 6 or

7 inputs possible

ohp cmos 5(h20-5-9) - rnbs.hiroshima-u.ac.jph20-5-9).pdf · mattausch, cmos design, h20/5/9 3...

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