372 • 2012 IEEE International Solid-State Circuits Conference

ISSCC 2012 / SESSION 21 / ANALOG TECHNIQUES / 21.8

21.8 On-Chip Gain Reconfigurable 1.2V 24μW Chopping Instrumentation Amplifier with Automatic Resistor Matching in 0.13μm CMOS

Fridolin Michel, Michiel Steyaert

KU Leuven, Leuven, Belgium

Motivated by low-voltage, low-power and small-size requirements of biomed-ical and energy scavenging circuits, this work introduces a fully integratedinstrumentation amplifier (IA) running at 1.2V with a power consumption of only24μW. A direct current feedback structure (DCFB) with rail-to-rail output swingis proposed along with a precision reference generation for on-chip resistortrimming (Fig. 21.8.1). Thus, gain reconfiguration is achieved while guarantee-ing low gain error over mismatch, process and temperature variations.

Many chopping instrumentation amplifiers are proposed using indirect currentfeedback (ICFB) [1] but they rely on a separate feedback transconductance (gm)pair at the input stage, which causes gm mismatch and sensitivity to input CMvariation. Moreover, noise is increased since the input stage current has to bedivided between the two gm pairs. Whereas an efficient calibration technique wasproposed to reduce the gm mismatch problem [1], this work suggests a directcurrent feedback (DCFB) topology that applies feedback to the source of thesame input transconductor, thereby inherently eliminating any gm mismatch.However, the difficulty to convert the output voltage to a linear feedback currentprevented this architecture from widespread use. A solution was proposed thatdefines the feedback current dependency on the output voltage solely by a resis-tor [2] to achieve low gain error. However, this approach relies on a common-drain output stage which significantly reduces the output swing. Therefore, acommon-source output stage is employed here (Fig. 21.8.2) that provides rail-to-rail output swing. Linear feedback current conversion is realized by activegeneration of a virtual ground voltage at the current folding points (nm1,2) wherethe output voltage is connected to via linear resistors Rf2A and Rf2B, thus pro-viding large output swing and high linearity in a DCFB topology. The closed loopgain is then given by the ratio 2*Rf2/Rf1. Virtual ground generation at the cur-rent folding point is also necessary for accurate current mirroring at the low sup-ply voltage.

Due to large mismatch and drift of integrated on-chip resistors most state of-theart instrumentation amplifiers rely on external resistors that need to be trimmedfor high gain accuracy. However, integrating resistors on-chip reduces cost andeliminates bulky external components that present an obstacle to bodyimplantable devices. An efficient fully integrated design using capacitive cou-pling was introduced [3], which exploits the advantage of better matching accu-racy of on-chip capacitances. In contrast, the aim of this work is to achieve on-chip resistor matching for current feedback architectures. Therefore, an on-chipgain calibration circuit was designed that enables precise adjustment of Rf2A,Rf2B and Rf1 (Fig. 21.8.2) using switched resistor networks to relieve gain errorsensitivity to intra-die variation, drift over process, temperature and agingeffects in harsh environment. As the absolute values of Rf2A and Rf2B need to bekept roughly constant at 500kΩ for stable output stage current and gain, thesource resistor Rf1 is adjusted in a course calibration first, followed by fineadjustment of Rf2A and Rf2B in a second step. Fine tuning of Rf2A and Rf2B ratherthan Rf1 results in higher calibration accuracy due to the relatively smaller finiteswitch resistance.

During gain calibration an internally generated voltage Vref is precisely divided by1/A and applied to the IA input (Fig. 21.8.1). In a closed loop configuration theIA output difference is compared to Vref and its gain is adjusted via switchedresistor networks to set its output to Vref. In the calibrated state the IA gainequals the reference down-scaling factor A.

The reference precision down-scaling is implemented by averaging the voltagedrop of A resistors. Since Vref is applied across the series configuration of theseresistors, the individual voltage drops must sum up to exactly Vref, so that themean value of their voltage drops is precisely Vref/A. Consequently, highly accu-rate down-scaling is guaranteed independent of the individual resistor mis-

match. In order to provide a maximum gain of 1000 a total number of 1000 unitresistors are connected in series and arranged similar to a ROM (Fig. 21.8.3).Each resistor can be switched to both probe lines p1 and p2 by addressing it withspecific row and column decoders that are controlled by cyclic counters. In thisway the resistors are switched consecutively to the IA inputs and their individ-ual mismatch is averaged. By applying a time difference between the reset sig-nals of both cyclic counters, the resistor probe points for both IA inputs can beshifted and a voltage difference be generated. A reset delay by one clock cycleresults in probing across one unit resistor, giving a gain of 1000. In general, thepossible gain configurations can be expressed as A = 1000/(reset delay cycles).As the reference-scaling scheme introduces a CM swing of Vref, the maximumreference value is limited to the CM input range of the IA. Averaging the IA out-put is performed by a 10b up-down counter, that is controlled by the compara-tor decision. After sweeping through all unit resistors the counter MSB bit islatched and fed to a digital controller that adjusts the switched resistor networks.

The accuracy limitation of the gain calibration is mainly determined by the IA andcomparator offset. The contribution of the IA is easily eliminated by trimming itsoffset below 1μV before gain calibration via adjustment of Rf2A, Rf2B. To achievecomparator offset below 0.5mV a two stage comparator with consecutive auto-zeroing was chosen, so that the residual offset of the first stage can be compen-sated by the second one (Fig. 21.8.4). During the offset compensation and track-ing phase the latch in the second stage is deactivated and a high impedance loadis switched on. This guarantees low input referred offset and that the secondstage output is large enough for reliable latching. As the IA output is fully differ-ential, the comparator has to detect a difference of a difference. Using two singe-ended amplifiers in front of the comparator inputs is not feasible, because theindividual amplifiers would experience the large IA output and Vref at their inputs,respectively. Instead single-ended conversion with ground referencing is per-formed using a switched capacitor network, which yields much higher linearity.

The Instrumentation amplifier is implemented in 0.13μm standard CMOS(Fig. 21.8.7) and runs at only 1.2V power supply using a low-voltage optimizedDCFB structure for rail-to-rail output swing. The amplifier itself has a power con-sumption of only 24μW while the calibration circuitry (including reference, com-parator and digital) adds 13μW (Fig. 21.8.6). The amplifier, reference, compara-tor and counter are all clocked with 25kHz, while the switched resistor networksare updated with 25kHz/1000=25Hz. With a maximum of 50 calibration stepsneeded, the calibration can be performed in 2s. Due to the digital switches thecalibration state is long-term stable under constant environment conditions. Thegain is reconfigurable from 10 to 1000 by adjusting switched networks of on-chip resistors that can be calibrated for 0.5% gain accuracy over CM, supply andtemperature variations (Fig. 21.8.5) by means of a precise on-chip referencedown-scaling technique.

References:[1] R. Wu, J.H. Huijsing and K.A.A Makinwa, “A current-feedback instrumenta-tion amplifier with a gain error reduction loop and 0.06% untrimmed gain error,”ISSCC Dig. Tech. Papers, pp. 244-246, February 2011.[2] R.F. Yazicioglu, P. Merken, R. Puers and C.V. Hoof, “A 60 μW 60 nV/ √HzReadout Front-End for Portable Biopotential Acquisition Systems,” IEEE J. Solid-State Circuits, vol. 42, no. 5, pp. 1100-1110, May 2007.[3] Q. Fan, F. Sebastiano, J. H. Huijsing and K. A. A. Makinwa, “A 1.8 μW60 nV/√Hz Capacitively-Coupled Chopper Instrumentation Amplifier in 65 nmCMOS for Wireless Sensor Nodes,” IEEE J. Solid-State Circuits, vol. 46, no. 7,pp. 1534-1542, July 2011.[4] Y. Kusuda, “Auto Correction Feedback for Ripple Suppression in a ChopperAmplifier,” IEEE J. Solid-State Circuits, vol. 45, no. 8, pp.1436-1445, Aug. 2010.[5] M. Belloni, E. Bonizzoni, A. Fornasari and F. Maloberti,“ A MicropowerChopper Correlated Double-Sampling Amplifier with 2μV Standard DeviationOffset and 37nV/√Hz Input Noise Density,” ISSCC Dig. Tech. Papers, pp. 76-77,February 2010.[6] R. Burt and J. Zhang, “A Micropower Chopper-Stabilized OperationalAmplifier Using a SC Notch Filter With Synchronous Integration Inside theContinuous-Time Signal Path,” IEEE J. Solid-State Circuits, vol. 41, no. 12,pp.2729-2736, December 2006.

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Figure 21.8.1: System diagram of the instrumentation amplifier with fully digital calibration loop.

Figure 21.8.2: Direct current feedback instrumentation amplifier with notch filter ripple reduction [4,6].

Figure 21.8.3: On-chip precision reference down-scaling for resistor trimming.

Figure 21.8.5: Measured gain error for CM and temperature variation. CM andgain error variation is due to residual comparator offset and finite switchresistance. Recalibration at different temperature points efficiently reducesthe gain error drift. Figure 21.8.6: Comparison to other recent micropower designs.

Figure 21.8.4: Comparator with clock timing diagram.

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Figure 21.8.7: Chip micrograph.