p1 – silicon superjunction and gan hemt power devicesmay 09, 2016 · ls = 0.1 µm lgs =1.5 µm...
TRANSCRIPT
1mist-center.org Peter Yuan, University of Central FL
P1 – Silicon Superjunction and GaN HEMT Power Devices
May 3-4, 2016
CONFIDENTIAL
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Project Overview
• Current State of the Art – For 600 V GaN HEMTs, Rds(on)= 0.1 – 0.15 mΩ-cm2, VT ~ 2V, QG = 6 –
10 nC-mm2 (FOM: Rds(on)xQG ~ 1 Ω-nC) – For 60 V silicon power MOSFETs, Rds(on) = 1 - 5 mΩ-cm2, VT = 1.5V
• Technical Objectives – Design good GaN HEMT and silicon super-junction power MOSFET
devices and study their reliability and temperature performance using 3-D Sentaurus mixed-mode device and circuit simulation
CONFIDENTIAL
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Technical Progress
Schedule Project Summary
• Milestones – Q1& Q2: Concurrently explore the design of silicon super-
junction LDMOS/VDMOS and GaN HEMT power devices – Q3: Investigate power SJ MOSFET reliability and high
temperature performance and evaluate their characteristics in the mixed-mode circuit simulation environment
– Q4: Examine robust GaN HEMT performance and evaluate GaN power device in mixed-mode device and circuit simulation environment
• Project Mentors – Dr. Patrick Shea, Intersil – Dr. Maxim Klebanov, Allegro
• Budget – $45,000
CONFIDENTIAL
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VDMOS conventional versus Super-Junction
CONFIDENTIAL
Nepi = 5x1016 cm-3 SJ VDMOS
Doping Conc. (cm-3)
Pillar Depth (µm) BV (V)
RDS(on) (mΩ-‐mm2)
Conventional Nepi 50 72 104.3
Super-Junction Nepi 50 983 242.45
SJ Nepi 30 605 175.85
SJ Nepi 10 233 110.6
SJ Nepi 5 136 94.25
SJ 2x Nepi 5 104 82.5
SJ 3x Nepi 5 79.8 78.15
SJ 3.5x Nepi 5 72.5 76.9
SJ 4x Nepi 5 62.8 75.9
● The super-junction design increases the off-state breakdown voltage significantly for the vertical DMOS at the expense of higher specific on-resistance. ● Reducing the epi-layer drift length could decrease the on-resistance, while reducing the breakdown voltage. ● Increasing the epi-layer concentration would reduce the on-resistance. ● Maintaining the same breakdown voltage of 72 V, super-junction VDMOS design at 3.5x Nepi and much shorter pillar depth provides 26% reduction in RDS(on).
Conventional VDMOS
Enlarged view from the top
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LDMOS Conventional versus Super-Junction
CONFIDENTIAL
Gate Body Drain
Source
Doping (cm-3) BV (V)
RDS(on) (mΩ-‐mm2) Vt (V)
Conv. Nepi 30 124 1.6
SJ Nepi 37 156.7 1.6
SJ 2x Nepi 30 116 1.6
SJ 2.5x Nepi 27.5 108 1.6
Conventional LDMOS used in Sentaurus 3-D simulation Super-Junction LDMOS
Conventional LDMOS impact ionization at VDS = 30V
Super-Junction LDMOS impact ionization at VDS = 30V
LDMOS cross-section view
Nepi = 5x1016 cm-3, Wepi = 4 µm
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3D Simulation Results - High temperature impact on SJ LDMOS
CONFIDENTIAL
● The super-junction design increases the off-state breakdown voltage for the lateral DMOS at the expense of higher specific on-resistance. ● Increasing the epi-layer concentration would reduce the on-resistance. ● Maintaining the same breakdown voltage of 30V, super-junction LDMOS design at 2x Nepi gives 6.5% reduction in RDS(on).
Drain current versus gate-source voltage at RT and 150ºC (green curve)
Drain current versus drain-source voltage at RT and 150ºC (green curve)
Drain voltage
Dra
in c
urre
nt
BV Room temp vs. High temp
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SJ LDMOS Nepi doping and temperature effects
CONFIDENTIAL
Doping (cm-3) BV (V)
RDS(on) (mΩ-‐mm2) Vt (V)
Conv. 27ºC Nepi 30 124 1.6
Conv. 150ºC Nepi 33 230 1.23
SJ 150ºC 2x Nepi 32 215 1.24
● High temperature decreases the threshold voltage, but increases the specific on-resistance. ● High temperature could increase the breakdown voltage. ● Overall, increasing the Nepi doping of a SJ LDMOS decreases the on-resistance. ● However, the benefit of the super-junction design at low voltage application is limited.
Doping (cm-3) BV (V)
RDS(on) (mΩ-‐mm2) Vt (V)
Conv. 27ºC Nepi 30 124 1.6
SJ 27ºC Nepi 37 156.7 1.6
SJ 27ºC 2x Nepi 30 116 1.6
SJ 27ºC 2.5x Nepi 27.5 108 1.6
SJ LDMOS performance @ 27°C SJ LDMOS performance @ 150°C
8mist-center.org CONFIDENTIAL
Normally-On GaN HEMT LS = 0.1 µm LGS =1.5 µm LG =1.5 µm LGD = 3 or 9 µm LD = 0.1 µm Nitride thicknes = 0.05 µm Al0.2Ga0.8N thickness = 0.02 µm
● GaN HEMT off-state breakdown voltage can be higher than 1,000V. ● Longer Lgd gives larger breakdown voltage. ● GaN HEMT on Al2O3 substrate increases the breakdown voltage significantly. ● Normally-on GaN HEMT has lower on-resistance than that of normally-off counterpart.
Substrate GaN thickness
(μm)
Lgd (μm
)
Vth (V)
Rds(on) (mΩ-cm2)
Vbd (V)
Qg (nC-
mm2)
Silicon 1 3 -4.06 0.32 327 23.34 9 -4.03 0.60 336 44.03
3 3 -4.11 0.30 679 23.35 9 -4.04 0.63 1,202 45.10
Sapphire Al2O3
1 3 -4.12 0.28 906 23.39 9 -4.10 0.68 1,893 33.39
3 3 -4.18 0.25 734 23.35 9 -4.08 0.62 2,123 45.10
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MISFET GaN HEMT with gate field plate
LS = 0.5 µm LGS =1 µm LG =1 µm LGD = 15 µm LD = 0.5 µm FPG = 3.6 µm Al2O3 gate insulator is 0.02 µm thick
● MISFET structure produces positive threshold voltages. ●The threshold voltage is sensitive to Trecess depth. ● The breakdown voltage and on-resistance are sensitive to 1st supply layer Al mole fraction.
1st supply layer
PNT layer
Trecess (nm)
Lgs (μm
)
Vth (V)
Rds(on) (mΩ-cm2)
Vbd (V)
Qg (nC-
mm2)
0.15 0.07 8 0.6 2.55 4.39 465.3 0.91 0.8 2.56 4.46 502.7 0.90 1.2 2.53 3.84 519.0 0.82 1.4 2.51 3.92 530.3 0.88
0.15 0.07 2 1 2.39 4.80 489.3 0.86 6 2.39 4.54 500.3 0.86 10 4.40 3.67 518.7 1.29 14 5.40 4.97 586.8 1.62
0.20 0.07 8 1 1.98 3.82 447.3 0.82
1.67 2.90 398.9 0.77 0.23 0.30 0.89 2.22 137.4 0.72
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MISFET GaN HEMT with Source and Gate field plates
CONFIDENTIAL
• Adding a second field plate for the source reduces peak electric field and increases the breakdown voltage.
Gate field plate
Source field plate
1st supply layer (x)
2nd supply layer (x)
PNT layer (x)
tPNT (µm)
Vth (V)
Rds_on (mΩ-cm2)
Vbr (V)
Qg (nC-
mm2)
3.8 0 0.15 0.25 0.07 0.01 2.56 4.60 506 0.90 3.8 8 3.52 3.77 722 2.84 2.7
4 0.15 0.25 0.07 0.01 3.52 3.68 433 2.49 6 3.52 3.78 463 2.59 8 3.52 4.18 623 2.78
3.8 8 0.18 0.25 0.07 0.01 2.15 3.15 663 1.37 0.2 1.98 3.08 610 1.33 0.22 1.72 2.78 528 1.28 0.15 0.3 0.07 0.01 2.53 3.23 1,097 1.43
0.31 2.53 3.21 1,081 1.43 0.33 2.53 2.94 1,009 1.42 0.35 2.43 2.80 865 1.39 0.37 2.52 2.68 694 1.41
0.15 0.25 0 0.01 4.46 8.78 695 1.82 0.18 2.39 3.27 677 1.53 0.25 2.23 3.08 621 1.50
0.15 0.25 0.07 0.005 4.80 4.77 667 2.33 0.010 3.52 3.77 722 1.99 0.015 2.33 4.91 719 1.38
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P-GaN HEMT with gate field plate (positive Vth, lower Rds(on))
CONFIDENTIAL
P-GaN HEMT with source & gate field plates (higher Vbr)
• Temperature effect
• Trap location effect
Gate Field Plate
LGD Vth (V)
Rds(on) (mΩ-cm2)
Vbr(V) Qg (nC-mm2)
1.8 6 1.36 1.257 119.3 0.41 5 10 1.36 1.900 633.9 0.61 5 18 1.36 3.519 831.5 0.13 7 1.36 3.642 805.8 0.33 10 1.36 3.368 644.4 0.50
Source field plate (µm)
Gate field plate (µm)
Lgd (µm)
Vth (V)
Rds(on) (mΩ-cm2)
Vbr (V)
Qg (nC-mm2)
6 1.8 6 1.37 1.24 211.2 2.47 10 5 10 1.35 2.18 656.5 1.51
18 1.37 3.16 1,334.6 0.657
Temp Trap location Vth (V)
Rds(on) (mΩ-cm2)
Qg (nC-
mm2) 200ºC Passivation -0.81 1.84 0.98
Channel -0.59 2.79 0.90 Buffer 0.69 2.12 0.58
Gate Field Plate
Lgd (µm)
Temp Vth (V) Rds(on) (mΩ-cm2)
Qg (nC-
mm2) 1.8 6 30ºC 1.36 1.26 0.41
100ºC 1.16 1.70 0.43 200ºC -0.71 2.14 0.80
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Summary of Achievements
• Technical Accomplishments - Designed silicon super-junction VDMOS and LDMOS and GaN HEMT
power devices; - Simulated conventional and super-junction DMOS/LDMOS and GaN
normally-on and normally-off power device performance; - Analyzed specific on-resistance, breakdown voltage, threshold voltage,
and gate charge for different device structures, lengths, and doping concentrations; and
- Confirmed by simulation that a) Increasing super-junction drift doping results in reduction of on-
resistance of DMOS, b) Using gate and source field plates provides an increase of breakdown
voltage of GaN HEMT, and c) High temperature operation decreases the drain current and
increases the on-resistance.
CONFIDENTIAL
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Future Work
• Next Steps – Take reliability aspects into account such as hot
electron injection, thermal impact, SOA, interfacial defects (surface, channel, buffer), dynamic resistance behavior, etc.
– Analyze transient behavior in mixed-signal device and circuit simulation environment
• Follow-on / Spin-off Projects – Experimental verification of super-junction LDMOS
and GaN HEMT performance; – Converter design using novel power devices
CONFIDENTIAL