PCB Design Rules

PCB Design Rules

PCB Layout () PCB Layout Schematic 3.1 NETLIST : 3.2 PLASEMENT : 3.3 GERBER FILE : 3.4 COMPONENT SILK SCREEN : 3.5 SOLDER MASK : 3.6 PASTE MASK : 3.7 DRILL : 3.8 NC DRILL FILE : 3.9 DRILL DRAWING :PCB 3.10 PAPER : PCB , 3.11 CAM3 : PCB , CAM1. 3.12 FR-4 : PCB , 3.13 V-CUT : 3.14 Trace (Etch): PCB 3.15 Routing: 3.16 Placement: 3.17 Pin: 3.18 Via: 3.19 Pad: 3.20 Rats: 3.21 Thermal relief (pad): power GND layer 3.22 Anti-pad: power GND layer 3.23 Moat: power & GND plane 3.24 Grid: 3.25 DRC: Design Rule Check 3.26 Test point: ATE (TP)

PCB Design Rules

t Layout

PCB Design Rules

6.1

PCB Design Rules

6.2 6.2.1 SchematicRFBB BB Symbol & Decal Layout Routing Rules RD Mechanical DXF EMI requirement RD Routing Rules

Layout PCB ( Net ListBoard Outline )

PlacementRFBB PCB Layout RoutingLayout RD Layout Rules& EMI requirement CheckRFBB Layout Check Data Out RFBB 6.2.3

TITLE/ DWG NO./ FILE NAME/ /

1 Schematics /

2 PCB Layout /

3 Part List /

4 PCB

5 PCB

6 Gerber/Drill Files

7 PCB

8 ASCII for SMT

9 DXF TOP for SMT

10 DXF BOT for SMT

11 Location for SMT

12 Working Gerber for

13 TOP for SMT

14 BOT for SMT

15 Photo Plots/Artwork

:Design guidelinesPower & Ground PlacementApply

: (1)

(2)

PCB Design Rules

PCB Layout structure

Standard PCB Layout structure

[The name of Gerber file]: 1. Top layer: trace and component attached side.() 2. Bottom layer: trace and component attached side.() 3. In1---In6 layer: trace layer inside of PCB.() 4. Power layer: power signal plane.() 5. GND layer: ground signal plane.() 6. Silk-screen: part ref ./part type /part outline /pin number /board version /date time /model name/

other text.() 7. Solder mask: pad soldering avoided.() 8. Solder paste: pad soldering paste.() 9. Drill map: drill symbol & drill hole size.() 10. NC-drill: drill tape for NC punch of PCB factory.()

[The name of PCB report]:

1. BOM: bill of material list.() 2. Netlist: net-list extraction for bare and loaded board tester.() 3. FABmaster file: for ATE machine.(Pcad:*.pdf / Pcad:*.asc /Allegro:*.val)extract database of

board. Component center list: central coordinate of all parts on board.()

PCB Design Rules

Layout guide line

[Silk-screen] 1. 2. Connector 3. IC 4. IC Connector 5. QFP 5pin 10pin (

) 6. CPUBGA 7. Connector pin SMD 10pin 8.

(R10-R20)

9. pin 10. 11. solder pad 12. SMD type Connector pad pad 13.

14.BGA A1 ()

PCB Design Rules

Layout guide line

[Placement] 1. Component Size 10mm 4.5mm

10mm 4.5mm DIP SMD 2.5mm~3.5mm pad pad pad

2. PCB (X*Y)460mm*380mm 60mm*50mm 0.5~4mm 3. Solder Size 6mm 4. BGA 125mil 5. BGA IC (

) 6. IC 50mil pad

pad pad 7. () 30mil

pad pad pad 8. ()

9. IC QFPBGACPU 10. BGA (BGA ) 11. SMD pad NPTH hold 3mm 12. 100pin QFP chip 15mm( V CPU) 13. DIP connector solder pad pitch=1.27mm pad ring 6~8milpitch>1.27mm

pad ring 8~12mm 14. SMD type connector guide pin solder nail

15. SMD

a. 0--90--180--270

PCB Design Rules

Layout guide line

b. (R)(C)(L)

c. 2pin (Diode)(Tcap. & Ecap)

d. 3pin (Trasister)(Diode)

e. IC

0 90 180 360

0 90

0 90 180 360

PCB Design Rules

Layout guide line

[Routing] 1. via pad 10mil via pad 20mil 2. via trace 40mil 3. via trace NPTH 40mil 4. () 10mil 5. trace SMD pad pad 45 90 180 6. IC pad 7. 25mil SMD pad 25mil pad

pad 8. 40mil via 9.

60mil 20mil 60mil

10. IC power & GND pin 2pin viaPull-high & Pull-low

11. IC by-pass cap. via IC by-pass cap. power pin by-pass cap. via

12. BGA via ball grid array ball grid array via

13. BGA design rule 14. 15. via 40mil 16. 10mil pad (Tear-drop)

PCB Design Rules

Layout guide line

17.

18. rework

PCB Design Rules

Layout guide line

[Fiducial mark] 1. Board fiducial mark 3 SMD Top &bottom

fiducial mark 2. QFP & BGA fiducial mark 2 3. Fiducial mark pad=round 1mmmask=round 3mm3mm trace

PCB Design Rules

ICT/ATE & Function test point

1. Sizevia=30mil(min)pad=32mil(mil) =75 mil(min) SMD( BGA chip)=50 mil(min) DIP cap.=100 mil(min) T/U =100 mil(min) (5mm )=100 mil(min) =75 mil(min) 2. BGA 30 3. power and ground input node 5 5

PCB vcc,5v,12v,3.3v 4. ASIC for testing control pin floating pin 5. ASIC boundary scan design 4pin(TCKTDITMSTDD) 6. ASIC ICT test mode Nand tree test NC pin 7. IC ICT test mode control pin 8. ASIC IC and CPU connector NC pin detect short 9. DIP

Docking connector pin 10.

PCB 11. Test tooling hole Non-PTH hole 12. Tooling hole size 0.125 inches+0.000 inches -0.002 inches 13. Tooling hole tooling hole +0.000 inches -0.002 inches 14. Tooling hole test point component +0.002 inches -0.002 inches

PCB Design Rules

ICT/ATE & Function test point

[Test point final released data] 1. board file ASCII file Pacd--*.pdf Mento--comps.asc Pads--*.pcb nets.asc Allegro--*.val parts.asc traces.asc 2. No test point node report

PCB Design Rules

Penalization 1. V cut Free space 7mm

2. Tooling hole 2 4mm+0.05mm -0.00mm A B 0.01mm

3. 100pin QFP 15mm

4. Trace 1.5mm

5. 2.5mm

6. 3mm

7.

Unitmm

PCB Design Rules

Penalization 8. SMT PCB 50-450mm PCB

9. connector 10. 11. V-cut

T t 1.0mm 0.4mm0.1mm 1.6mm 0.5mm0.1mm 2.4mm 0.8mm0.1mm

Unitmm X Y

Min 50x 50

Max 450 350

PCB Design Rules

Penalization

Tooling hole = 4mm+0.05mm

5mm

Free space

3 fiducial mark

=1mm Mask=3mm

10mm

10mm

5mm

Free Space

Reflow direction

Tolerance:+0.05mm

c

PCB Design Rules

BGA layout rule

Pad size :20+/-2mil No solder Mask :24+/-2mil Via hole :10A15(mil) Via size :B maxim un is 25mil Via location :Via hole 4 pad BGA pad

30mil Via mask : Via component side (solder - mask)

Limited area: a. BGA Layout PCB b. PCB BGA Layout 125 mil Layout

via

A

B

125mil

BGA

PCB Design Rules

BGA layout rule c. BGA PCB Bottom side 5 ( 7mm ) Layout

Test Point: BGA Layout PCB Layout 1. Size : 0.6~0.8mm 4 2. BGA pad 24mil BGA

PCB Design Rules

PCB Design Rules

LAYOUT 5.2 .LAYOUT DESIGN RULES 5.2.1 LAYOUT LAYOUT

PART-LISTNET-LIST PCB LAYOUT 5.2.2 5.2.3 LAYOUT

5.2.4 LAYOUT CHECK PCB 5.2.5 (.DXF ) LAYOUT 5.2.6 LAYOUT LAYER10 5.2.7 LAYOUT PLACEMENT PLACEMENT

REVIEW MEETINT 200mil

5.2.8 APERTURE TABLE LAYOUT() 5.2.9 REFERENCE NAME () 5.2.10 TOOLING HOLES( 3 )PC

3 5.2.11 PC-Board 5mm ( PC-Board ) 5.2.12 PC-Board TOOLING HOLES DRILL non-pth 165mil 200mil

200mil PC-Board PC-Board (SMT PC-Board )

5.2.13 PC-Board DRILL non-pth 165mil PC-Board 5.2.14 SMD SMD FIDUCIAL MASK

PC-Board 40mil 5.2.15 ASICPLCC IC FIDUCIAL MASK 40mil

5.2.16 GOLDEN FINGER () 5.2.17 CRYSTAL 5.2.18 DIP () 5mm 5.2.19 (TO-92 ) PIN PIN 2.54mm() 5.2.20 PC-Board CONVEYOR 5.2.21 SOIC SOIC PLACEMENTRM 20mil 5.2.22 PLCC PLCC PLACEMENTRM 20mil 5.2.23 PLACEMENT 5.2.24 PLACEMENT SLOT CONVEYOR

PCB Design Rules

5.2.25 PLACEMENT CONNECTOR CONVEYOR 5.2.26 PLACEMENT SOIC CONVEYOR 5.2.27 PLACEMENT CHIPS CONVEYOR 5.2.28 PLACEMENT PLCC IC 5.2.29 PLACEMENT QFP IC 5.2.30 PC-Board BOM 5.2.31 COMS IC 74HC04GATE INPUT GROUND 5.2.32 Operational Amplifiers INPUT 5.2.33 Operational Amplifiers INPUT OUTPUT 5.2.34 CLOCK 5.2.35 TTL GATE 5.2.36 LAYOUT POWERGROUNDBYPASS CONDENSER POWERGROUND

IC POWERGROUND

5.2.37 INDUATORCAPACICTORRELAYOSCILLATORTRANSFORMERCRYSTAL

5.2.38 () 5.2.39 PDA 4mm 6mm 5.2.40 SOLDER SIDE 5.2.41 5mm 5.2.42 5.2.43 LAYOUTLAYOUT LAYOUT PC-Board

REFERENCE NAME RENAME UPDATE SCHWMATIC REFERENCE NAME

5.2.44 LAYOUT PC-Board CHECK PC-Board

5.2.45 GOLDEN FINGER PIN FINGER non-pth ( GOLDEN FINGER )

5.2.46 PC-Board DRILL non-pth LAYOUT DRILL(24)

PCB Design Rules

5.2.47 PC-Board LAYOUT PC-Board

* V-CUT CONVEYOR ( PC-Board ) * CONVEYOR (

PC-Board ) 5.2.48 PC-Board PCGERBER 5.2.49 PC-Board LAYOUT

5.2.50 PC-Board LAYOUT FILE LOGO( BOAED NAME

FILM NAMEPNVERSIONDATEFILE NAMETITLE DRNCKDAPPD DWG NOREVSHEET OFHISTORY )

5.2.51 PC-Board FILE PC-Board SIZE 5.2.52 DRILL 37.2 37mil80mil

37.3 37mil95mil 37.4 37mil100mi 37.5 37mil105mi 37.6 37mil110mi 37.7 37mil120mi

37.71 37mil130mi 37.8 37mil140mi 37.9 37mil300mi

5.2.53 JOB FILE NAME 5.2.54 CAM 5.2.55 PC-Board LAYOUT 5.2.56 PC-Board LAYOUT CHECK

PC-Board LAYOUT (ISO-FRM-039) 5.2.57 PC-Board LAYOUT VIACOMPONENT PAD

CHECK 5.2.58 LAYOUT 5.2.59 PC-Board PC-Board SAMPLES

PCB Design Rules

5.2.60 PC-Board PC-Board SAMPLES PC-Board LAYOUT GERBER FILE PC-Board LAYOUT LOG FILE

5.2.61 GERBER FILE.EXE 5.2.62 RELEASE GERBER FILE .EXE .ZIP 5.2.63 FILES LAYOUT JOB FILE GERBER FILESGERBER FILES PC-Board (history) LAYOUT JOB FILE history

PCB Design Rules

JOB FILE NAME

NO NAME LEVEL GERBER FILES SAVE NAME

1 SILK SCREEN,COMPONENT SIDE 126 2 SOLDER MASK, COMPONENT SIDE 121 3 TRACK, COMPONENT SIDE 1 4 GROUND PLANE 225 5 POWER PLANE 325

525

6 TRACK,SOLDER SIDE 4 6

7 SOLIDE MASK, SOLDER SIDE 428 628

8 SILK SCREEN, SOLDER SIDE 429 629

9 DRILL DRAWING 124 10 SMD PASTE MASK, COMPONENT SIDE 123 11 SMD PASTE MASK, SOLDER SIDE 422

622

0 Pad BGA Layout Layout Layout 1 shielding case shielding case Via Via Via RF Component Pad Ref GND,

Compponent Pin Pad Via Pad RF Matching

2 MAC Ground path i.e. MAC GND Pin

Pin MAC 3 Analog GND Digital GND Placement Gerber

Doubble check 4 Double check 5 RC Lowpass RC ()IC

C IC Placement 6 RF ( Saw Filter,PA,Transceiver

Via ) 7Saw Filter pin via ( Saw performance )

pin Via 8 Layout RF GND Plane ( RF Impedance) Layout Cross talk

BGA Pad 9Bypass capacitor IC Pin

10Xtal abd On chip oscillator at Layout , The traces connecting crystal and caps, and the IC oscillator pins should be as short and wide as possible( the helps reduce parasitic inductance and resistance). Therefore, the compnents (caps and crystal) should be placed as close to the oscillator pins of the IC as possible) 11CLK GND

12I,Q i.e. (N_I,P_I ),(N_Q,P_Q ), Layout

13 IC Pin 1A mapping to 40mil 14Placement RF GND Via

15 Net ,,GND( AGND, DGND ) I,Q , CLK 16 Smooth 17( Connector ) Reference GND PlaneExample: NextComm GSC type connector on board Intersil Printed Ref GND Pad RF Via Radiation patern

Matching 50 Ohm Patern Data Sheet 18 Shielding Case 2.4 GHz 3cm 19Ferrite Bead VCO ( Synthesizer)PA Input

Ferrite Bead EMI 200 Ohm Bead AGND DGND Total Power consumtion 21 Layout ( placement ) Mismatching 22 ferrite bead check impedance at 100 MHz , check Series

resitance at DC. 23Intersil ECO History ( Rule ) RD_RF,Layout, Schematic

24Schematic NP Attributes/Value (NP) Creat Bom Sorting 25 Schematic

(1) RF NP Bypass capacitor,

Schematic place on Bottom IC Pin input Via Bottom NP Capacitor. (2) Placement Bypass NP

Capacitotr (3) USB MiniPCI PI Matching

26CW CLK XTAL( OSC )

Xtal. Harmonic 27Layout priority 1RF 2Power Line 3CLK and I,Q ( Power Line Power Line ) 4Digital ( Power Line Power Line ) Power Line, IQ RF 28 50 Ohm lay Layout

Layout "" 50 Ohm Lay "Layout team"

29Schematic RF,IQ,CLK,Power,Digital { 20030508 Layout Schematic tool RF(Matching),Power(NP) }RF(Matching) 501~599,Power(NP) 901~999 30 Microstrip Line PA input Output Matching Pad Via Pad Solder Mask

Matching 31 Via Pad 32 Placement Layout RFCLKIQ Layout 1RF,2CLK(OSC),3IQ,4Power,5Analog,6

Digital. 33 trace Via PAD Via

34GND AGND DGND ( AGND

DGND DGND AGND ) GND

Via 35 Gerber check pad mask solder mask

short BGA IC pad pad solder mask

36Microstrip line CPW with GND

Phone Layout Rule 1. The minimum trace width is 4mil 2. Layer definition

Layer 1: Component & Trace Layer 2: Signal & RF trace Layer 3: GND Layer 4: Power Plane Layer 5: Signal & Audio trace Layer 6: GND ( Shielding case Region: Layer6 Trace VIA)

3. Via definition 1-2 via: (4,12) 2-5 via: (12,20) 1-6 via: (12,20)

4. MCU GND PIN 1-2 2-5VIA LAYER 3 5. Power trace: at least 25mil (1) VRTC, VSIM, : 10 MIL (2) VCORE_1V8, VDD AVDD, PMIC_VTCXO, VMEM, 1V2: 20MIL (3) VCHG, VBATBB, VBAT: 40 MIL ( pin , ,)

6. Differential Pair: 4mil, 4mil, Differential pair 6mil, Ground VIA

(1) MICP0&MICN0 ; MICP1&MICN1: in5 (2) SPKN0&SPKP0 : in5 (3) I&IB; Q&QB- : in2 (4) MIC+ & MIC-: in5 (5) SPK+ & SPK-: in5

7. Clock Trace : , clock trace 6mil Ground. CLOCK Trace 6 mil , Ground VIA, in2 Layer,

trace (1) 26MHz

(2) MCCK, SIMCLK : GND Plane, trace 6mil (3) DAICLK: GND Plane, trace 6mil

8. RF Trace: , Ground VIA, in2

(1) VAFC (2) VAPC (3) HB_TX, LB_TX, PCS_RX, PA_EN, BANDSW_DCS, RFVCOEN (4) LE, SDATA, SCLK, VCXOEN

9. Audio Trace: , Ground

VIA, in5 ( 6mil GND 8mil ) (1) MICBIASP, MICBIASN (2) VREFN, VREFP (3) MP3_OUTL, MP3_OUTR (4) FM_INL, FM_INR

10. Sensitive Trace: , sensitive trace 8mil Ground ,Ground VIA

(1) IRDA_PDN (2) IRDA_TXD&IRDA_RXD

11. Reset trace : & shielding case 50mil, 6mil, ( 6mil )

(1) /SYSRST (2) /WATCHDOG (3) LRSTB (4) SIMRST

12. Nand flash data bus: RF trace (1) NLD0~NLD7 13. Inner3 Layer &Bottom Layer: Ground Plane Ground, Trace

14. Power-Power, Power-Ground 30mil 15 RF VBAT power (PA) trace > 100mil 16. U400 >9 2-5 Via 17. Shielding case region put through hole 18. Keypad

Layout Check List Note

Layout

1 (OEM ) 2 Board Name (OEM Router-XXXX OR TA-XXXX) 3 4 RD Code ( RELEASE Code) 5 PWBA Label 6 7 Outline 8 Pin Pitch 9 () 10 5mm () 11 SMT Drill 165mil non-pth 12 SOIC SOIC Placement 20mil 13 PLCC PLCC Placement 120mil 14 Placement 15 Placement SLOC SOIC Conveyor 16 Placement Connector Conveyor 17 Placement Chips Conveyor

18 DIP () Pin Pitch 5mm

19 Crystal Solder Mask 20 Run Card Drill 125mil non-pth 21 Default Short Trace Copper 22 23 24 Layout PCB 25 Finger 26 PC Board Fiducial Mask (40mil ) 27 ASIC PLCC IC Fiducial Mask (40mil ) 28 29 Through Hold

Layout

30 31 PAD 4mm 32 CMOS IC 74HC04 Gate Input Ground 33 Reference 34

35 Inductor Capacitor Crystal Oscillator Relay Transformer

36 Crystal ( 200mil )

37 SMD PDA Through Hold ( 15mil ) ()

38 Layout 39 Check Size 40 Check PCB net-list ( check ASCII ) 41 Checking (FAX ) 42 Checking 43 Checking Clearance 44 Checking Connectivity 45 Checking Plane 46 CAM Power Plane Thermal Pad 47 Layout 48 Made in TaiwanLayer-shiftVia-shift 49 ICT Testpoint

50 ICT (Solder Mask Component Side Testpoint )

1 2 3 4

Layout

Moat() Moat Moat FGND DGND AGND Common mode choke ASIC clock input Layout

10/100LAN transformer LEVEL ONE LXT970/972 layout GND VCC GND GND GND (power choke) GND VCC GND IC VCC (0.1uf) Component side

Lan /Paired via GND via noise level RD PCB IC (

EMI and ESD)

Trace 0 ohm

Layout

PCB () Panel ( Fiducial mask()

)

Drawing (via kindfile name)

(( solder side mirror)BGA )

PCB ( Compare netlist) solder mask open phase mask open ( RD OR ) Gerber file ( via ) PC Board Fiducial mask(SolderX3PadX1 ) RD Trace width (tracepower tracecgarge trace

)

NPTH PTH ( Drill drawing ) (GND )(PAVCO

)

Shilding case

Layout

Board outline Panel PCB a b mm c NPAD Layout a PCB PCB Layout PCB PADS PCB Rules Rules 45 Space Rules Solder mask TOP Solder mask BOTTOM Paste mask TOP Paste mask BOTTOM IC PAD IC Space 10mills IC PAD mils VIAS Silkscreen TOP PART Name Silkscreen BOTTOM PART Name Drill drawing Board outline Layer Panel SMT a Layout ConnectionRoutesRulesCAMPour

TOP.ASC Files

b Layout ConnectionRoutesRulesCAMPour TOP.DXF Files

c Layout ConnectionRoutesRulesCAMPour TOP.BOTTOM Files

d Layout LOC e SMT TOP DRAW f SMT BOTTOM DRAW