pcie 3.0 tx/rx动态均衡测试整套方案专题介绍 - 21ic · pcie 3.0...

PCIE 3.0 Tx/Rx动态均衡测试整套方案专题介绍 Compliance Test Items

Tx Electrical

Rx Electrical

Link EQ

Teledyne LeCroy

[email protected]

Derek Hu

[email protected]

18616350571

关于Teledyne LeCroy（力科）

2

力科是高能物理学家Walter LeCroy于1964成立的一家美国公司

公司起初专业研制高能物理测试仪

力科公司总部位于Chestnut Ridge, New York

力科拥有最先进的技术和最广的数字示波器产品线（从40MHz到65GHz）

力科是示波器技术的领导者而且是示波器业界串行数据市场份额增长最快的厂商

在2004年和2006年，通过购买两家协议分析仪厂家（CATC和Catalyst）并将它们合并成一个协议分析部门，位于Santa Clara，CA，使得力科成为了世界上协议分析仪的领导者。

Teledyne LeCroy confidential2013

Teledyne LeCroy示波器的广泛应用

3 Teledyne LeCroy confidential2013

Teledyne LeCroy不断超越示波器核心指标的极限


Teledyne LeCroy示波器产品线

5

WaveAce WaveJet WaveSurferXs-A

WaveRunnerXi-A WaveRunner6Zi WavePro7Zi WaveMaster8Zi

500MHz 100MHz 300MHz 40MHz 1GHz 200MHz

2GHz 400MHz 4GHz 400MHz 6GHz 1.5GHz 45GHz 4GHz

HDO

1GHz 200MHz


Teledyne LeCroy示波器产品线（续）

WaveExpert

100GHz 20GHz 45GHz 13GHz

LabMaster 9Zi-A

65GHz 25GHz

LabMaster 10Zi

Teledyne LeCroy confidential2013 6

Teledyne LeCroy示波器以外的产品

ArbStudio

Arbitrary Waveform

Geneator

Protocol Analyzer

Receiver Test

USB PCI Express Serial ATA DDR3

Eagle Phoenix

Voyager Summit Siera Kibra

Signal Integrity

Network Analyzer

SPARQ


PCI Express 3.0 应用

8

Gen2 服务器及桌面高端产品

Switches, Servers, IO Boards targeted at PCIe

3.0 for 2011-13

消费类产品

Workstation and graphics cards targeted at PCIe

2.0 for now.

嵌入式产品

Telecommunication servers using Gen1/Gen2

Military systems using Gen1/Gen2

Embedded processors/ASICs going from PCI to

PCIe 1.1

Gen3


Agenda

PCI Express (R) 3.0有哪些新的特点

与PCI Express (R) 2&1 的对比

Teledyne LeCroy & PCI-SIG

SEG 一致性测试

SEG 电气测试规范

5 个方面的测试


http://www.extremetech.com/article2/0,1558,2319727,00.asp?kc=ETRSS02129TX1K0000532

PCI Express 3.0 和PCIE 2&1的主要不同之处

PCI Express 2.0 PCI Express 3.0

Bit Rate 5Gb/S 8Gb/s

Encoding/Decoding 8B/10B 128B/130B

Overhead 20% 1.5625%

Scrambling Optional Always

Effective Bit Rate 4Gb/s per lane 7.88Gb/s per lane

Transmission path Same as Gen1 Same as Gen1 and Gen2

Receiver Testing Informative Required


PCI Express 3.0 物理层信号——接收端眼图几乎闭合

IC System Board PCIE Connector Plug-In Card IC

由于速率高，通过很长的传输线和接插件后，信号损耗通常非常严重


PCIE 3.0 是如何应对的？

8Gb/s 发送端芯片进一步优化了抖动的性能

发送端使用均衡来抵消损耗的通道带来的影响

使用了更加高效的编码方式来满足更高的数据传输吞吐率

接收端芯片具有更好的抖动容限性能

优化了CDR功能以过滤更多的低频抖动

在接收端使用CTLE和DFE功能来打开通道末端的眼图



TxEQ RxEQ

TxEQ – De-emphasis and Pre-shoot

RxEQ - CTLE

RxEQ – DFE



TxEQ RxEQ

Tx使用了一个基于FIR的均衡器

TxEQ 过程中有11个presets

3 阶均衡 (pre cursor + post cursor)

以创建去加重和前冲

Rx 使用了行为级的均衡算法

CTLE

DFE

CDR

在链路初始化过程中，Rx发送TxEQ preset设置要求给Tx，此过程叫做动态均衡（ Dynamic

Equalization ）


PCI-SIG 和LeCroy

1. PCI-SIG EWG, CEM, SEG 力科是PCIE工作组的积极成员.

2. New SEG electrical spec v. 0.5 有三个主要工作组推动了PCIE规范的创建

3. 客户基础 80% 的板级成员公司已经选择了力科的方案以及初期的测试夹具用于PCIE 3.0的

测试

正在和更多的关键PCIe客户工作在一起，通过力科的测试优化他们的测试方案；正在紧密的和Intel及AMD测试实验室合作在一起以进行Gen3指标的验证

4. PCIE Gen Compliance Workshop (Gold Suites) Tx 电气测试(Teledyne LeCroy, T, A)

Rx 电气测试(Teledyne LeCroy, T, A)

链路均衡（Link EQ） (Teledyne LeCroy only)


Competitive Advantage

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Visit:http://www.pcisig.com/specifications/pciexpress/compliance/co

mpliance_library#electrical30 and search for Tx/Rx Link

Equalization Testing

PCI Express 3.0 Compliance Available Solutions

Transmitter Testing for PCIe 3.0 for

System Board and Add-in Cards

A

T

Teledyne LeCroy

Receiver Testing for PCIe 3.0 for

System Board and Add-in Cards

A

T

Teledyne LeCroy

Tx/Rx Link Equalization Testing for

PCIe 3.0

Teledyne LeCroy Only

PLL Loop Bandwidth Testing for PCIe

3.0

A

Teledyne LeCroy


http://www.pcisig.com/specifications/pciexpress/compliance/compliance_library




http://www.extremetech.com/article2/0,1558,2319727,00.asp?kc=ETRSS02129TX1K0000532

SEG 一致性测试用于PCI-SIG 论证

According to the SEG electrical test specification version 0.9, there are 5 sections that needs to be tested for PCI Express 3.0 for Add-In

cards and Systems. For the past two PCI-SIG compliance workshops, the Gen3 FYI gold suites offered testing for section 1 and section

4. Sections 2, 3 and 5 will be enabled for future workshops.


Teledyne LeCroy PCIE Gen3 Line Card

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PHY Layer Electrical

Transmitter Testing PHY Layer Electrical

Receiver Testing Link Equalization Testing

Scope Scope + BeRT3 Scope + PeRT3 + Protosync

PCI Express® Architecture

PHY Test Specification Revision 3.0

Section 2.1, 2.2, 2.5, 2.6


PHY Test Specification Revision 3.0 Section 2.9,

2.8

PCI Express® Base Specification . Section 4.3


PHY Test Specification Revision 3.0 Section

2.3, 2.4, 2.7, 2.10, 2.11

Built-in 3 tap de-emphasis/pre-shoot and Protocol

aware for loopback

initialization and SKP filtering

Only Test Solution in the Industry

for compliance testing and characterization of

PCIE Gen3 Link Equalization

Built-in PCIE Gen3 required jitter sources (SJ, RJ,

Differential Mode Jitter, Common Mode Jitter)

Proto-Sync PCIE Gen3 decode and trigger for in

depth debug and characterization


SEG 一致性测试用于PCI-SIG 论证

Tests 2.1/2.5 - Tx Signal Integrity

Tests 2.2/2.6 - Tx Preset Test for 8Gbps

Tests 2.3/2.4/2.7 - Tx Link Equalization Response Test for 8Gbps

Tests 2.8/2.9 - Rx Jitter Tolerance

Jitter Calibration

Jitter Tolerance

Loopback Compliance

Tests 2.10/2.11 - Rx Link Equalization Test

Receiver Link Equalization Calibration

Receiver Link Equalization Test


PCI Express 3.0发送端测试挑战

挑战：规范要求眼图抖动测量必须要在通道末端进行，而且CTLE和DFE处于使能状态，在通道测量之前，需要先进行11级的preset测量

解决方案：测量工具（示波器）会将规范要求的通道S参数（S4P）嵌入到仪器中以仿真通道的损耗，测量将在新的PCIE Gen3 Sigtest软件中进行。Sigtest软件将使用适合的CTLE和DFE滤波器来使眼图睁开。

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Embed using

EyeDoctor2

Software in the

Oscilloscope


捕获一致性测试码型

Sigtest will be used for all measurements:


SEG Compliance Testing for PCI-SIG Certification





Jitter Calibration

Jitter Tolerance

Loopback Compliance





Tx Preset 测试

一致性测试夹具上有开关用于切换DUT输出不同的Tx均衡preset

DUT

Preset

Control

switch


Preset test

Capture PCIe Gen3 compliance pattern with 11 presets and feed the results into sigtest.


Teledyne LeCroy的一致性测试软件Qualify

5/17/2013 25 Teledyne LeCroy confidential2013






Jitter Calibration

Jitter Tolerance

Loopback Compliance





5/17/2013 27

动态均衡过程

动态均衡过程有4个步骤:

Phase 0: 从上行器件向下行器件以8b/10b编码格式发送Tx端和Rx端的Preset

Phase 1: 在有preset 情况下发起8GT/s 的速率(<= 10-4 BER)

Phase 2:下行器件通过在训练序列中发送均衡请求来调整上行器件的Tx端输出设置.,直到获得最优的设置.

Phase 3: 上行器件通过发送均衡系数以及preset调整下行器件的Tx端设置

11级Presets定义 (de-emphasis 和 pre-shoot)

TS2 序列用于Phase 0 , TS1 序列用于Phases 1..3

环回和接收机一致性测试: 测试设备需要能够通过TS1序列配置DUT的Tx发送端 LeCroy‘s PeRT3 具备这样的能力


Phase 2 / Phase 3

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测试设备不仅要能够接收DUT发送过来的TxEQ请求，并根据请求返回相应的信号给DUT

同时测试设备还需要能够发送TxEQ请求给DUT，并能够接收DUT根据TxEQ请求发送回来的信号。

为了测试接收端均衡器的能力，测试设备必须能够接收接收端发送过来的优化Tx均衡器的请求并在1000ns时间以内发出带有相应去加重的信号并完成全部12项中的每一个Preset测试。


Tx Link 均衡训练测试

1) Tx均衡器是否回应了协议级别的preset请求？

2) 给定的响应时间内Tx回应的preset是否满足Rx要求的preset？

Scope will measure the preset

response and verify

correctness and timing

requirements (<1000ns)

Gen2 PCIE DUT

Phoenix will send Tx preset request after

Gen3 initialization protocols (Protocol

Aware)


Copyright © 2012, PCI-SIG, All Rights Reserved 30

Test: Section 2.4 (or 2.7)

Add-In (or System) Card Receiver Link EQ Test for 8.0 GT/s

Procedure Measure Response

Send EQ TS2 TX Preset P0 Change speed to 8G Do equalization phases 0-3

Request Preset X (0..9) Monitor transaction including

request and response Verify response time ≤ 1000 ns

Continue into Loopback Send Compliance Pattern Capture waveform from DUT Repeat for other presets

Evaluate TxEQ Feed waveforms into SigTest Verify valid presets

Measure

Response

Time

Monitor

Transaction

Analyze

Protocol







Jitter Calibration

Jitter Tolerance

Loopback Compliance





PCI Express 3.0接收端测试挑战

挑战: 接收端测试是规范要求的。因此需要测试设备能够产生不同类型的抖动源和信号以复制真实的PCI Express 3.0

信号；并能够和被测DUT进行协议握手，完成发送端和接收端的初始化过程，使DUT进入Loopback模式

解决方案: PeRT3 Phoenix 内置有所有PCI Express 3.0要求的抖动源以及信号要求；且PeRT3具有协议握手能力，可以和被测件进行握手。

Signal with All Jitter sources added:

De-emphasis = -6dB

Pre-shoot = 3.5dB

RJ = 2ps RMS at up to 1Ghz

SJ = 13ps at 100Mhz

Differential mode jitter = 14mV and 2.1Ghz

Calibration channel = -20dB

Total Generated Jitter = 0.3UI to 0.35UI + Channel

Effects


Step 1: Preset 校准

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- 11 presets 需要根据规范要求的方法进行校准

- 主要用于测试的Preset 为P0,

P4, P7, P8 及特殊的preset (-

6dB, 6dB)


Step 2: Rj 和 Sj 校准

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- Rj 和 Sj 需要在仪器输出端进行校准（不经过夹具和通道）

- 在后续的眼图张开度校准时Rj

值会重新调整


Step 3: DM 校准

35

- DM 将在经过CBB3/CLB3 和 riser card的通道末端进行校准

- 眼高（Eye height ）和眼宽（Eye width）将在通道的末端进行校准


Step 4: 眼高（Eye height）和眼宽（Eye Width）校准

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- 通过改变Rj和DM来实现最后的眼高和眼宽的校准

Eye Height (mV)

Eye Width (ps)

Add-In Card 46 +0/-5 41.25 +0/-2

System Board 50 +0/-5 45 +0/-2


自动化校准程序

5/17/2013 37 Teledyne LeCroy confidential2013

Rx 抖动容限测试

rx_spkg

cbb_conn2

RX SMP

cbb_conn1TX SMP

Error

Detector

AIC Under Test

Signal

Generator

Sj + Rj +

Diff Noise

Signal with All Jitter sources added:

De-emphasis = -6dB

Pre-shoot = 3.5dB

RJ = 2ps RMS at up to 1Ghz

SJ = 13ps at 100Mhz

Differential mode jitter = 14mV and 2.1Ghz

Calibration channel = -20dB

Total Generated Jitter = 0.3UI to 0.35UI + Channel

Effects







Jitter Calibration

Jitter Tolerance

Loopback Compliance





Rx Link 均衡训练测试

rx_spkg

cbb_conn2

RX SMP

cbb_conn1TX SMP

Error

Detector

AIC Under Test

Signal

Generator

Sj + Rj +

Diff Noise


Copyright © 2012, PCI-SIG, All Rights Reserved 41

示例: Section 2.10 (or 2.11)

Add-In (or System) Card Receiver Link EQ Test for 8.0 GT/s

Procedure Enable jitter for target eye

Send EQ TS2 P7 at 2.5G

Change speed to 8G

Do equalization phases 0-3 Record final requested cursor

from DUT in phase 2 (or 3)

Continue into Loopback

Perform RX Test Send Modified Compliance

Pattern

Pass if ≤ 1 error in 2:05

0 errors in 6:15 for 95% confidence of E-12 BER

Measure BER

Generate

Calibrated

Eye

Perform full

equalization

and then enter

loopback


链路均衡一致性测试连接示意图

42

Generator

Clock Out

Error Detector

Data Rx+

Ad

d-In

Ca

rd

Riser Card CBB

Rx+

Rx-

Clk In

Tx- Tx+

Power

Supply

Ch1

Ch2

Ch3

Ch4

LeCroy

SDA830Zi-AData Tx+

Data Tx-

Trigger Out

LeCroy

PeRT3

Phoenix

Data Rx-

SMA-SMP

cable pair

DC Blocks

Power Dividers

Phase matched SMA-SMA cable pair

Phase matched

SMA-SMP cable

pair

Terminator

AUX IN


PeRT3 Phoenix

LeCroy PeRT3 is capable of protocol level handshake to send and

receiver TxEQ commands

LeCroy PeRT3 is also a full blown BERT and Signal conditioner for Jitter generation and

programmable De-emphasis controls


最全面以及唯一具有协议握手能力的PCIE 3.0测试设备

44

力科PCIE GEN3全套测试解决方案：SDA820Zi-A + PeRT3 + SPARQ

全自动测量TX和RX所有项目


5/17/2013 Company Confidential 45

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pcie 3.0 tx/rx动态均衡测试整套方案专题介绍 - 21ic · pcie 3.0...

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