pfdprof. dr.-ikling. klau s dmülld. müller-glaser 25.3
TRANSCRIPT
Kompetenzbereichssympop y p„Model-Driven Engineerin
P f D I KlProf. Dr.-Ing. Klau25.3
osium Systeme und Prozesseyng for Automotive Systems“
D Müll Glus D. Müller-Glaser3.2010
Copyright © 2010 FZI Karlsruhe kmg
ITIV Einordnung des Ing
Universität Kar
11 Fakultäten
Fakultät für Elektrotechnik un
13 Institute
Institut für TeInformationsverar
nstituts
rlsruhe (TH)
ca.19800 Studenten
nd Informationstechnik
ca. 1850 Studenten
chnik der beitung (ITIV)
Copyright © 2010 FZI Karlsruhe kmg
ITIV OrganisationInstitutsle
Prof. Dr.-Ing. Klaus DProf. Dr.-Ing. Jü
Prof. Dr.rer.nat. W
Verwaltung und ProjektabwicklungDipl..-Ing.
Jens BeckerQualitätssicherung, Dokumentation & Schulung
Systems Engineering
Prof Dr Ing
Eingebetteteelektronische Systeme
Prof Dr -Ing
Mikrosystemtecund Optik
Prof Dr rer naProf. Dr.-Ing.K. D. Müller-Glaser
Entwurfsmethodik
Prof. Dr.-Ing.Jürgen Becker
System-on-Chip (SoC)Hardware Software
Prof. Dr.rer.naWilhelm Stor
OptoelektroniscSystemspezifizierung,Systemmodellierung &
SystemsimulationHardware-
Hardware SoftwareCodesign
Architektur- & Kommunikations-
synthese
pSensorik in
Medizin & TechMikrooptische Sys
& KomponentHardwareBeschreibungssprachen
(VHDL, VML)Rapid Prototyping
Echtzeit-Betriebssysteme
syntheseRekonfigurierbareHW-Architekturen
AnwendungsspezifischeSyntheseverfahren
pEntwurfsmethoRechnergestüt
WerkzeugeSignalverarbeitEchtzeit Betriebssysteme Syntheseverfahren Signalverarbeit
eitungD. Müller-Glaserrgen Becker
Wilhelm Stork
chnik
at
Elektronische Systemeund Mikrosysteme (ESM) am F.-Zentrum Informatik (FZI)
Prof Dr Ing K D Müller Glaser
MedizinischeInformationstechnik
(MIT) am FZIProf Dr rer nat W Storkat.
rk
che
Prof. Dr.-Ing. K.D.Müller-GlaserDr.-Ing. P. Graf
TechnologietransferS f &
Prof. Dr.rer.nat. W. StorkDr.-Ing. C. Kunze
Technologietransfer
hnikstemeen
Systemspezifikation &Systemsimulation
Hardware Software CodesignRapid Prototyping
ElektronischePatientenakte (EPA)Informationstechnik
Messtechnik & Sensorikdentzte
ung
Performance-AnalysenSimulatorkopplung
Mixed-Signal-SignalbeschreibungAutomatische Codegenerierung
in Medizin & TechnikNotfallmedizinSignalanalyse
Therapieunterstützung
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ung Automatische Codegenerierung Therapieunterstützung
KIT Innovation
Ihr ForschungsdienstleiIhr ForschungsdienstleiTechnologieberater –
FZIFZIForschungszentruForschungszentruForschungszentruForschungszentruInformatikInformatikan der Universität Karlsruhean der Universität Karlsruhe
Forschungsbereich ESS: Embedded Systems a
ister undister und
umumumum
and Sensors Engineering
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Das�FZI:Informatik�&�ihre�Anwendun
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MitarbeiterInstitutsleitungWissenschaftliche MitarbVerwaltung, Technik, WeExterne LehrbeauftragteExterne LehrbeauftragteForschungsbereich ESSForschungsgruppe hipeg g pp p
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nten des Instituts
ITIV Arbeitsfelder Embedded SIdee
HW-Beschreibungs-sprachen
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RealisierungElektronische Systeme
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Elektronische SystemeSystem on Chip (SoC)Mikrooptische SystemeIntelligente Sensoren
Prototypenentwicklung
TechnologietTelekommunikation –
Automatisierung – AuKooperationsprojekte un
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SystementwurfSpezifikation Modellierung SimulationRad 1 Rad 1
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Rapid PrototypingHardwareplattformen
Codegenerierungg gEchtzeitbetriebssysteme
Konfigurierbare Schnittstellen
transfer– Medizintechniktomobilelektronikd Auftragsforschung
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dustriekunden
Aktuelle Forschungsprog p
� Rapid Prototyping / Hardware-in-the� Systementwurfs Methodik – Modell-� Systementwurfs Methodik Modell� Werkzeuge zur Bewertung von Arch� System on Chip Design – IP-Basier� Dynamisch rekonfigurierbare Hardw
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IHE - ITIV
Entwicklung einerEntwicklung einerKalibrierstationam Boden zurErhöhung derGenauigkeit(K ti(KooperationIHE und ITIV)
Radarsatellit fürkommerzielle Nutzung(Erdvermessung)
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TerraSAR – Hochfrequenz- uElektronikElektronik
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Daimler Coop.: Body Functions On-Demand
Demo Application: Cabin FunctionsDemo Application: Cabin Functions
Seat Control(right)
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-> Easy Life-Cycle Updates
-> Complexity Reduction (Verification!)
FPGAs Xilinx VirtexXC2V3000
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SecuritySecurityProjektinhalte
Side Channel Security von Xilinx FSide Channel Security von Xilinx FSicheres Einbringen von kryptograSchlüsseln in elektronische SystemSchlüsseln in elektronische SystemTechnologie Monitoring
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Copyright © 2010 FZI Karlsruhe kmg
Multicore Architectures: EU-ProjectMultipurpose Dynamically Reconfi
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Methoden und rechnergfür den Entwurf von vertSystemen im Automobil
gestützte Werkzeugeteilten Elektrik/Elektronik-
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General structure of an elec
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Embedded systems in yRelatively high production volumes (5.0High number of variants (countries, cusReusabilityL t il bilit 15Long term availability: > 15 yearstough operating conditions
� Temperature range: -40� Temperature range: -40� Supply voltage: 6V … 14V … 28V � Mechanical stress: acceleration, vibratio� Chemical stress: humidity, oil, exhaust g� Electromagnetic compatibility
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Hierarchical OrganizatioProcessesProcesses
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Static andDynamic Test
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uted between OEM and supplier
Copyright © 2010 FZI Karlsruhe kmg
uted between OEM and supplier
life cycle model (V-Model)supporting computer aided design tools
V-Model for automotive
System-Analysis
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Courtesy ETAS
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Copyright © 2010 FZI Karlsruhe kmg
Verification and Validation in S
Verification1. The process of determining, whether th
development cycle fulfils the requirem“Am I building the product right”g p g
2. The act of reviewing, inspecting, testinotherwise establishing and documentidocuments conform to specified requir
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development project with respect to th“Am I building the right product?”
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he product of a given phase of the system ents established during the previous phase.
ng, checking, auditing, comparing or ng whether items, processes, services or rements
term that can mean: on))
nal system (SW HW) produced from anal system (SW, HW) produced from ahe user’s needs and requirements
Copyright © 2010 FZI Karlsruhe kmg
Typical Designflowyp gIdea
HW/SW-Requirements Analysis
PROCESS (schlupf, stBEGIN
CASE state IS
HW/SW Requirements AnalysisPreliminary HW/SW-Design
HW-Architecture, SW-ArchitectureInterface Description
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CASE state ISWHEN freilauf =>
IF schlupf > 0next_state <
bremsen;ELSE
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Copyright © 2010 FZI Karlsruhe kmg
onon
Rapid Prototyping - HaLoopLoop
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SimulatedECU
RapidPrototyping
Test-Pattern
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Hardware-in-the-Loop
ment DataMeasure-ment Data
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r means for verification and validation:, Rapid Prototyping,
Copyright © 2010 FZI Karlsruhe kmg
tegration Test (HiL)tenance Test, Life Time Tests
ECU development for p3 Prototypes3 Prototypes
Requirements-Analysis
S t
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architecture-orientedRapid Prototyping(B-Muster) Subsystem
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Copyright © 2010 FZI Karlsruhe kmg
ECU Software DeveSystem Requirements
System Specification
S t
CaptureExactly
System TestVehicle Test
System DesignSystem Specification
SystemRequ
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Integration Test
Software RequirementsPhysical Function Model
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elopmentApproval for Production
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SWReleaseReview
OEMIntegration of theSW Subsystems
OEM
Software SubsystemIntegration
Integration of the SW Parts
Supplier
Integration of the SW Partsfrom DC/Supplier
ionksing
CodeReview
Copyright © 2010 FZI Karlsruhe kmgCourtesy J. Bortolazzi (Porsche)
singon
Typical Designflowyp gIdea
HW/SW-Requirements AnalysisWhat are the supporting
PROCESS (schlupf, stBEGIN
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HW-Architecture, SW-ArchitectureInterface Description
system level design too
Detailed HW/SW
CASE state ISWHEN freilauf =>
IF schlupf > 0next_state <
bremsen;ELSE
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HW/SW-ImplementationTest, Integration, Test
W-Modules, Data Dictionary, SW-Comp
System Integration, Te
, y, pHW-Component, HW-ModuleHW-Realization Documents
y g ,Calibration, ApplicatiTransition to Utilizatio
System-Analysisexecutable Specs, models
S t D iFreiFrei
BremsenBremsen
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yInterfaces
Modeling and SimulationReal Time Requirements
ls?
Rapid PrototypingHardware PlatformCode GenerationW-Design
>0 THEN<=
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W-Designonary
rt
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Copyright © 2010 FZI Karlsruhe kmg
onon
System specification as basti d icooperative design process
hundreds of pages, mainly textual desc
Costumer-CostumerOrder
S tSystemSpecification
SystemDesignDesign
ModuleDesign
expensive iterationl d t Design
Implementation S
cycles due to- incomplete- wrong
Realization HW- ambiguous- inconsistent
system specificationF l SFormal Sp
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System-
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SubsystemTest HW/SW
System-Integration, Test, Application
ModuleTest HW/SW
Test HW/SW
SW
Test HW/SW
W
ifi ti t bl
Copyright © 2010 FZI Karlsruhe kmg
pecifications, executable,del Based Design
Model based design: mg
Modeling for complete systemg p y(ECU, car, driver, road, weather con
Domain specific models for S(closed loop control, reactive systemsoftware intensive systems)
Different abstraction levels PDifferent abstraction levels, P(functional and non-functional data
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Model documentationMacro modeling Meta modeling
odeling issuesg
m including system environmentg ynditions)
Subsystems and Componentsms, probabilistic systems,
Parameter variation and boundariesParameter variation and boundariesfor early design space exploration)
s (reuse, variant design)s (reuse, variant design)tensive testing
Copyright © 2010 FZI Karlsruhe kmg
Model based Design - execut
to control technical processes, cogn
Closed Loop Con(continuou
Reactive Su(discrete event(discrete, event
Cognitive Subsystems, WaCognitive Subsystems, Wa(probability density functio
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best-of-point tools for
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ThetaEncoder
+Init() : void+ThetaEncoder()+Update() : void
TraySensor
+Init() : void+TraySensor()+Update() : void
ZEncoder
+Init() : void+Update() : void+ZEncoder()
XEncoder
+Init() : void+Update() : void+XEncoder()
<<import>> <<import>> <<import>> <<import>> <<import>>
ware intensive SubsystemsCommandProzessor
-run : FwBoolean#sendString : FwString
+CommandProzessor( messageProzessor : MessageProzessor* )GetStatus
+Execute() : FwBoolean+GetNextMessage() : Message*+Init() : void+MessageProzessor()+Parse( messageStr : FwString* ) : Message+SendAnswer( answer : FwString ) : void+~MessageProzessor()
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()+Update() : void+XEndSensor()
+Init() : void+Update() : void+ZTopSensor()
Copyright © 2010 FZI Karlsruhe kmg
r different applications
mate, Stateflow, UML, SysML
+Disable() : void+Enable() : void+GetAddress( : void )+Init() : void+IPortPCIModul1( name, address : FwInt, startBit : FwByte, nBit : FwByte, nBytes : FwInt )+Update() : void+~IPortPCIModul1()
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Analysis-em-elT)
Analysismodel
(expectedresponses)T) responses)
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Abstraction Levels for MSimulationSimulation
AbstractionAbstraction-levels Ove
Closed Loopidealized Se
Digital
Timing
DigitalCircuits
Macro models
Timing
AnalogCircuits
simpSens
d
Physical modelsProcess,
Sensor/Actuator-models
mod
1 10 103102
Modeling and
System A1A2
Be/act
erall System p / Reactive Controlensor/Actuator
Register-TransferCONTROL
RAM ALU ROM
Be/act
Logic
plifiedor/Actuator-
d ldels
106105104 Complexity
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y(# of Components)
System Level Modelingy g
Complex, Heterogeneous: mechanical, electricalp gMulti Domain Multi Ph
Tight coupling between: complete system, systsubsystems, componemanufacturer and techMulti View, Multi Abstr
Long iteration cycles: design, manufacturingSimulation is a must
Complicated non-linearities: strong functional inflelectrostatic force prop
l ki i tseveral working points
Dynamic systems: extremely different timtiff diff ti l tistiff differential equatio
Time and space derivatives: FEM Simulation and
g and Simulationg
l, fluidical, optical phenomena and their couplingsp p p ghysics Systems
tem environmententshnology dependenciesraction Level Approach
g and test very expensive and time consuming
luence, small signal behavior not sufficient:p. V2 ,capacitance prop. 1/d, Hysteresis,s
me constants: > 10 orders of magnitude,ton systems
Analysis, 3D fields and waves
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System Level Modelingy gMechanicsElectrostaticsElectromagnetic Fields Thermal problems Multi-Physics Problemsy
g and Simulationg
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Modelingg
Modeling languages used: Spice SABER VHModeling languages used: Spice, SABER, VHHDL-AMS SystemC AMS Modelica
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HDL-AMS, SystemC_AMS, Modelica
Modeling for heterogeneous electro
ArchitectureModelling with UML
BatchController
Buffer::Buffer SocketListItem1 *
outputBuffer 1
ProcessorBuffer SocketListItem
inputBuffer
1 *
1
Real time Studio (ARTiSAN)
Event d
Real-time Studio (ARTiSAN)Rhapsody in C++ (i-Logix)Rose (Rational Software, IBM)Together (Borland)Poseidon (Gentleware)
Modelling w
IdleIdle
Poseidon (Gentleware)MagicDraw (NoMagic)Ameos (Aonix)TAU2 (Telelogic)
evAck /Actio/Actio
Rhapsody in Statemate (i-Stateflow (ThASCET (ETA
onic embedded systems
Signal flow orientedM d lli ith bl k diModelling with block diagrams
ASCET (ETAS) MATLAB/Simulink (The MathWorks)
driven
MATLAB/Simulink (The MathWorks)MATRIXx (National Instruments)
with state charts
Sending Waiting_For_Repeat
evRepeat[myCondition]
Sending Waiting_For_Repeat
Waiting_For_Ack evBusyon1()
Waiting_For_Ack evBusyon1()
C++ (i-Logix) -Logix)he MathWorks)AS)
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Requirements for new toolstools
Model based design as a basis.Is accepted in research and predein ECU development
Design space exploration meansdistribution of hardware and softw
/ t t l tisensor/actuator locationscomputation performance as well Co-design not only for hardware afunction, safety, security
Metrics and parameters used areMetrics and parameters used aretherefore, domain specific systeminterfacing seamlessly with compo
A lot of model transformations are re
system level
evelopment, not yet standard
ware under consideration of
as communication performanceand software but also
e domain specifice domain specificm level tools are requiredonent specific tools (meet in the middle).
equired
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E/E Architecture DeveloPREEvision®PREEvision®
Concept Phase
analysis
requirements
analysis
accecptance
systemspecification
software hardware
validation
specification specification
coarsedesign
hardwaredesign
hsdesign
pdesign
opment with
service
system test
test
hw integration module integration
system integration& operational test
verification
check ofcomponents
modulartest
& test & testverification
hardwarestructure
programmetest
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programmingimplementation
Model-Based E/E Archit(Inputs)(Inputs)
Features Requirements D
Variant Configuration
Technical Concepts Equipm
Model-Ba
El t i / El t i A hit t M
Model BaDesign
Electronic / Electric Architecture Mo
tecture Design
Design Objectives Sales & Marketing
n & Management
ments Platforms
ased
d l (D i S ifi N t ti )
ased
odel (Domain Specific Notation)
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Model-Based E/E Archit(Outputs)(Outputs)
Electronic / Electric Architecture
Features Requirements Functions Electr
ModeDesig
Model Optimization - Consiste
g
Architecture MetricArchitectureHandbook
MetricResults
tecture Design
Model (Domain Specific Notation)
Harnessronics Network Electrics Geometry
el-Basedgn
ency Checks - Refactorings - ...
g
B h k Various
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Benchmarks VariousExports
Architecture Evaluation� Metrics� Counting Metrics (weight, lengthg ( g g� Cost Metrics� Complexity Metrics� Power consumption metrics� Bus load
Model
� ...
Model
query A
Modelquery BModel query B
Modelquery Cq y
Automation
Variant assignment Start query searc
n & Benchmark
h etc.)
Presentation
)
P t
• Table
Parameter
• Flashlight
MetricMetric MetricJAVAPythonSimulink®
MetricJAVAPythonSimulink®
• ChartMetricJAVAPythonSimulink®
ch Execute metrics Show results
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Describing/Comparing Ag p g
p21
p1
p1
0
-
p5
Architectures
,5 Architecture 1Architecture 2
p
Architecture 2
p3
2
p4
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E/E Architecture Layery
Requirement
Requirements / Feature-Functionality-Network
Requirement
Sub-Requirement
FFN-Artefacts
Sensor Block
Function Network
Sensor Block
Function Block
Function Block
GatewayECUSensorCANWire(s)
Hardware Architecture
ECUSensorWire(s)
Install.Location
Install.Location
placed torouted to
Topology
Install.Location
Install.Location
Inline
Model
Actuator Block
k
Function Block Actuator Block
Actuator Blockprocessed from
ECU ActuatorCAN LIN
p
ECU ActuatorWire(s)
Install.Location
Install.Location
placed to
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Install.Location
Install.Location
Important issue:efficient M2M Transformefficient M2M-Transform
Optimized Transformator Engine with InterfacOptimized Transformator-Engine with Interfac� ETAS ASCET® (>= 5.1)� The Mathworks MATLAB®/Simulink®/S� Fully integrated in PREEvision (for mod
propagation…)
Model-based Specification of Transformation Ru� Rule Set modeled with UML� Maintainability, Readability� Automated Code Generation of the Rule
Purpose of M2M Transformation� Model data migration� Model-Refactoring� Model-Optimization� Model Verification� Model-Verification
mationmationces toces to
Stateflow® (R13 – R16)del consistency checks, variant
ules
e-Set, no manual design process behind
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51M2ToS
M2M Engines ArchitectgRule4
R le3Rule3Rule2<<metamodel>>
Source-Metamodel Rule1
LHS
Instance of
Source ModelT l A
Instance of
Rule-M
Tool A
Rule-MUM
Importer Transform
ure
<<metamodel>>Target-Metamodel
RHS
Instance of
Target-ModelT l B
Model
Tool B
ModelML
52mator Exporter
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Tools used for ECU de
specification supportreactive systems
closed loop control systems
software systems
performance analysis
rapid prototyping, HiL
tolerance analysis
p p yp g,
application, test, diagnosis
architect re e al ation
ASIC DesignC-Verifier architecture evaluation
ASIC Design
esign
(Doors, QFD/Capture) (SDL, Stateflow,Statemate)
(ASCET-SD, Matlab/Simulink, MatrixX)
(Real-time Studio, Rhapsody in C++,Rose, Together, Poseidon, MagicDraw,A TAU2)Ameos TAU2)
(SES/Workbench, Foresight)
(dSPACE, ETAS, IPG, Quickturn)
(Rodon)
( , , , )
(ETAS, Hitex, Vector, RA)
(Aq intos Pree ision)
(Cadence Mentor Synopsys)(PolySpace)(Aquintos Preevision)
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(Cadence, Mentor, Synopsys)
System Level Tool Support
ator
soptical
h i lA
ctua
ent
Rea
mechanical
thermal
nviro
nme
face
sReaelectrical
magneticRea
l e
cial
inte
rf
Sens
ors
Spec
S
Not seamless somehow satisfying support: s
Power electronics
ol
Analogsignal
processing
MicrocontrollerDSP
al Time Operating System pply
m C
ontr
o
al Time Operating System
ower
Sup
Syst
e
DigitalSignal PSignal
Processing
Communication with other Systems
Copyright © 2010 FZI Karlsruhe kmgBenzstandard hardware platforms, software, RTOS, Sensors und Actuators
Conclusion (1)• What system level tools should
� Documentation (readable for men s
( )
� Documentation (readable for men, s� Data exchange between all designe� Data exchange between computer ag p
databases� Intellectual Property, reusable in libr
P t i d f i t d i� Parameterized for variant design� Supporting standards and guideline� Testable (Fault models automatic M� Testable (Fault models, automatic M
(automatic generation of test pattern(what is modeled, but also what is n
� Seamless in design flow(Analysis, Design, Verification, IntegDiagnosis)g )
� Reviews, Rule Checking, Simulation� Synthesis, automatic, interactive op� allow access for automatic paramete
d providespecific for application domain)specific for application domain)ers across company boundariesaided tools supporting distributed pp g
raries
s (e.g. HIS, Autosar)Model validation) quality assuredModel validation), quality assuredn and test bench) and documented not modeled)
gration, Validation, Test, Application,
n, Formal Verification, Model Checking timizing (e.g. RP-Code, Production Code)
Copyright © 2010 FZI Karlsruhe kmg
er-extraction
Conclusion (2)( )Design studies show:• Model based methodologies and too• Model based methodologies and too• Seamless design flow only partially • Interfaces for Modeling SimulationInterfaces for Modeling, Simulation,• hard problem for design of embedde
� Cross sensitivity of Components (ins� Safety, Security, Function-Codesign� According modeling is really time and� Mixed-Mode Multi-Level-Simulation� Mixed-Mode, Multi-Level-Simulation� Formal Verification und Validation no
• Non functional requirementsTi f d t d• Time-, frequency- und parameter-do
� Module / System-Integration und –Te� Cross-sensitivities, EMC, Certification
Model based system design is possiblebut there are many design and analydesign phasesdesign phases.
ols are well performing and promisingols are well performing and promisinggiven (e.g. digital hardware, software).Characterization mostly manualCharacterization mostly manual
ed systemsufficient characterization)
d cost consumingrequiredrequired
ot possible?!
imainestn
e,ysis steps still missing, especially in early
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Conclusion (3)( )Industrial design practice shows:• Challenges for the design of emChallenges for the design of em
� many modeling techniques from compFSM, Hybrid Automata, LSC, MSC, PTemporal Logic Timed Automata ZTemporal Logic, Timed Automata, Z …
� Is academic willing to prove their rese� Seamless flow required with respect t
support of standard interfaces must bsupport of standard interfaces must b� There exist large libraries in different d
neglected� Th i t t d d RTOS (OSEK/V� There exist standard RTOS (OSEK/V� There exist tight cost boundaries� New algorithms and tools must be ma� Engineering constraints, adequate de
De-Facto-Standards (tools) must be oSaber, VHDL, C, Assembler
� Formal methods are not yet scaling fo� Required from industry: availability of
numbers etc. for research
• Required: more close cooperation b(tier 1) suppliers, EDA companies a
mbedded systemsmbedded systemsputer science not adequate:
Petri nets, process algebra, Statecharts, …earch results for real designs?!to industrial life cycle processes, therefore e done also by academicse done also by academicsdescription methodologies that can‘t be
DX) d b tDX) and bus systems
ade commercially available escription methods according toobeyed: Matlab, ASCET, Statemate, Doors,
or many real industrial problemsreal requirements, constraints, cost
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between system manufacturer, and academics
Thank you very much y yfor your attention
Contact:Klaus Müller-GlaserKarlsruhe Institute of Technology [email protected]://www.itiv.kit.edu
Copyright © 2010 FZI Karlsruhe kmg