piso vhdl code
TRANSCRIPT
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library IEEE;
use IEEE.STD_LOGIC_1164.all;
----------------------------------------------------------------------------------------
-- ENTITY ------------------------------------------------------------------------------
----------------------------------------------------------------------------------------entity parallel_in_serial_out is
port(
IN_CLK : in STD_LOGIC;
IN_PISO_RST : in STD_LOGIC; -- from FSM
IN_LOAD_FLAG : in STD_LOGIC; -- input from FSM
IN_PARALLEL_DATA : in STD_LOGIC_VECTOR(23 downto 0); -- input from FSM
OUT_PARALLEL_DATA : out STD_LOGIC_VECTOR(23 downto 0); -- temporary test output
OUT_SERIAL_DATA : out STD_LOGIC -- actual serial output data to the DAC
);
end parallel_in_serial_out;
----------------------------------------------------------------------------------------
-- ARCHITECTURE ------------------------------------------------------------------------
----------------------------------------------------------------------------------------
architecture piso_arc of parallel_in_serial_out is
signal sl_dump : std_logic := '0';
--
signal sl_msb : std_logic := '0';
--
--signal sl_d123 : std_logic
:= '0'; --signal slv_parallel_data : std_logic_vector (23 downto 0) := (others=>'0'); --
temp signal for data processing
begin
piso_process : process (IN_CLK, IN_LOAD_FLAG, IN_PISO_RST) is
begin
if (rising_edge (IN_CLK)) then
sl_dump
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end if;
--sl_d123
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