pla 2
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CS370 – Spring 2003
Prog rammable Logic Devices
PALs/PLAs
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Pre-fabricated building block of many AND/OR gates (or NOR, NAND)"Personalized" by making or breaking connections among the gates
Programmable Array Block Diagram for Sum of Produ cts Form
Inputs
Dense array of
AN D gates Productterms
Dense array of
OR gates
Outputs
PALs and PLAs
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Example:
F0 = A + B' C'F1 = A C' + A BF2 = B' C' + A BF3 = B' C + A
Equat ions
Key to Success: Shared Prod uct Terms
1 = asserted in term0 = negated in term- = does not participate
1 = term connected to output0 = no connection to output
Inp ut Side:
Outpu t Side:
OutputsInputsProductterm
Reuseof
terms
A
1-
1
-
1
B
10
-
0
-
C
-1
0
0
-
F0
00
0
1
1
F1
10
1
0
0
F2
10
0
1
0
F3
01
0
0
1
A BB C
A C
B C
A
PALs and PLAs
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PALs and PLAs
Examp le Cont inued All possible connections are availablebefore programming
A B C
F0 F1 F2 F3
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Unwanted connections are "blown"
A B C
F0 F1 F2 F3
AB
/BC
A /C
/B /C
A
PALs and PLAs
Example Continu ed
Note: some array structureswork by making connections
rather than breaking them
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Alternat ive representat ion for hig h fan-in struc tures
Short-hand notationso that all the wires need
not be drawn!
Notation for implementingF0 = A B + A' B'F1 = C D' + C' D
PALs and PLAs
AB
AB
CD
CD
A B C D
AB AB+ CD CD+
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PALs and PLAs
ABC
A
B
C
A
B
C
ABC
ABC
ABC
ABC
ABC
ABC
ABC
F1 F2 F3 F4 F5 F6
Design Example
F1 = A B C
F2 = A + B + C
F3 = A B C
F4 = A + B + C
F5 = A xor B xor C
F6 = A xnor B xnor C
Multiple functions of A, B, C
A B C
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Dif ference between Prog rammable Array L og ic (PAL ) and
Programmable Lo gic A rray (PLA):
PAL concept -- implemented by Monolithic Memoriesconstrained topology of the OR Array – I.e., the OR
array cannot be fully programmed.
A given column of the OR arrayhas access to only a subset of
the possible product terms
PLA concept generalized topologies in AND and OR planes
PALs and PLAs
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Design Examp le: BCD to Gray Code Converter
Truth Table K-maps
W = A + B D + B CX = B C' Y = B + CZ = A'B'C'D + B C D + A D' + B' C D'
Minimized Functions:
A
0
0
0
0
0
0
0
01
1
1
1
1
1
1
1
B
0
0
0
0
1
1
1
10
0
0
0
1
1
1
1
C
0
0
1
1
0
0
1
10
0
1
1
0
0
1
1
D
0
1
0
1
0
1
0
10
1
0
1
0
1
0
1
W
0
0
0
0
0
1
1
11
1
X
X
X
X
X
X
X
0
0
0
0
1
1
0
00
0
X
X
X
X
X
X
Y
0
0
1
1
1
1
1
10
0
X
X
X
X
X
X
Z
0
1
1
0
0
0
0
11
0
X
X
X
X
X
X
AB
CD 00 01 11 10
00
01
11
10
D
B
C
A
0 0 X 1
0 1 X 1
0 1 X X
0 1 X X
K-map fo r W
AB
CD 00 01 11 10
00
01
11
10
D
B
C
A
0 1 X 0
0 1 X 0
0 0 X X
0 0 X X
K-map for X
AB
CD00 01 11 10
00
01
11
10
D
B
C
A
0 1 X 0
0 1 X 0
1 1 X X
1 1 X X
K-map fo r Y
AB
CD00 01 11 10
00
01
11
10
D
B
C
A
0 0 X 1
1 0 X 0
0 1 X X
1 0 X X
K-map for Z
PALs and PLAs
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PALs and PLAs
Programmed PAL:
4 product terms per each OR gate
A B C D
0
0
0
0
0
0
A B C D
A
BD
BC
BC
B
C
BCD
AD
BCD
W X Y Z
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Code Con verter Discrete Gate Implementat ion
4 SSI Packages vs. 1 PLA/PAL Package!
B
\ B
C
C
A
D
\ D
DW
X
YB
B
B
B
C
C
A
D
\ A
\ C
\ B
\B
\C
\A
\ D
2
2
11: 7404 hex inverters
2,5: 7400 quad 2-input NAND3: 7410 tri 3-input NAND4: 7420 dual 4-input NAND
4
4
3
3
5
Z
1
3
2 1
2
D 1
1
4
2
PALs and PLAs
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Example: Magn itude Comparator
EQ NE LT GT
ABCD
ABCD
ABCD
ABCD
AC
AC
BD
BD
ABD
BCD
ABC
BCD
AB
CD 00 01 11 10
00
01
11
10
D
B
C
A
1 0 0 0
0 1 0 0
0 0 1 0
0 0 0 1
K-map fo r EQ
AB
CD 00 01 11 10
00
01
11
10
D
B
C
A
0 1 1 1
1 0 1 1
1 1 0 1
1 1 1 0
K-map for NE
AB
CD 00 01 11 10
00
01
11
10
D
B
C
A
0 0 0 0
1 0 0 0
1 1 0 1
1 1 0 0
K-map for LT
AB
CD 00 01 11 10
00
01
11
10
D
B
C
A
0 1 1 1
0 0 1 1
0 0 0 0
0 0 1 0
K-map for GT
PALs and PLAs
A B C D