Power Estimation and Power Estimation and Optimization for SoC DesignOptimization for SoC Design

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OutlineOutline

Why low power for system design?Why low power for system design? How to design a low power system How to design a low power system

for SoC.for SoC. Some power estimation tools.Some power estimation tools. ConclusionConclusion ReferenceReference

Power Driver: SpeedPower Driver: Speed

Power Limit: Energy Density Power Limit: Energy Density

Impact of System ArchitectureImpact of System Architecture

StrongARM RStrongARM RISCISC ARMARM ARM+ASICARM+ASIC ASICASIC ASIC (low ASIC (low

power, 1v)power, 1v)

PerformancePerformance 0.28s0.28s 1.12s1.12s 0.7s0.7s 10ms10ms 46ms46ms

PowerPower 0.42J0.42J 0.62J0.62J 0.3J0.3J 0.63mJ0.63mJ 22.2uJ22.2uJ

EffortEffort 1-2 weeks1-2 weeks 1.5 1.5 weeksweeks 2-4 weeks2-4 weeks 9 months9 months 15 months15 months

Design Flow of Low Power SystemDesign Flow of Low Power System

Specification

Architecture Design

High-Level Synthesis

RT-Level

Synthesis

Gate-Level

Power Optimization

Power Analysis

Power Optimization

Power Gain

+

-

Power Reduction TechniquesPower Reduction Techniques

Voltage Scaling: Vcc reduction is the most efVoltage Scaling: Vcc reduction is the most effective way for reduction power.fective way for reduction power.• Leakage power is bigger factor.Leakage power is bigger factor.• Exacerbate noise and reliability concerns.Exacerbate noise and reliability concerns.

Power Reduction Techniques (cont.)Power Reduction Techniques (cont.)

Clock gating: Reduce the switched Clock gating: Reduce the switched capacitance on the clocks.capacitance on the clocks.

Low power libraries: Designed with Low power libraries: Designed with power “in mind”.power “in mind”.

Power Reduction Techniques Power Reduction Techniques (cont.)(cont.)

Power-Delay Power-Delay curves: the choice curves: the choice of logic family used of logic family used can greatly can greatly influence the influence the circuit’s power circuit’s power consumption.consumption.

Power Reduction Techniques Power Reduction Techniques (cont.)(cont.)

Low power logic synthesis: show 10% power Low power logic synthesis: show 10% power saving for synthesis block.saving for synthesis block.

System power management: monitor the System power management: monitor the system activity and enforce the movement of system activity and enforce the movement of the system components between different the system components between different power states.power states.

Software based power reduction: CPU power Software based power reduction: CPU power consumption is dominated by a large cost consumption is dominated by a large cost factor (clock, caches, etc.) that for the most factor (clock, caches, etc.) that for the most part, does not vary much from one cycle to part, does not vary much from one cycle to the other.the other.

Power Estimation Tool: JouleTrackPower Estimation Tool: JouleTrack Designed from MIT.Designed from MIT. A web based tool for software energy A web based tool for software energy

profiling.profiling. There are three order estimation:There are three order estimation:

• First order: Current consumption is independent First order: Current consumption is independent of the code and depends only on the voltage and of the code and depends only on the voltage and frequency.frequency.

• Second order: Uses energy differentiated Second order: Uses energy differentiated instruction.instruction.

• Third order: Separate the leakage and switching Third order: Separate the leakage and switching energy components.energy components.

Current Consumption of StrongARM Current Consumption of StrongARM SA-1100 Instruction SetSA-1100 Instruction Set

Current consumption of 6 different benchmark proCurrent consumption of 6 different benchmark programs at different supply voltage and frequency legrams at different supply voltage and frequency le

vels in the StrongARMvels in the StrongARM

First and Second Order Model First and Second Order Model Predictions ErrorPredictions Error

JouleTrack Block DiagramJouleTrack Block Diagram

Power Estimation Tool: SimplePowPower Estimation Tool: SimplePowerer

Designed from Penn State University.Designed from Penn State University. A framework for evaluating the effect of hiA framework for evaluating the effect of hi

gh-level algorithmic, architectural, and cogh-level algorithmic, architectural, and compilation trade-offs on energy.mpilation trade-offs on energy.

It consists of the compilation framework aIt consists of the compilation framework and the energy simulator.nd the energy simulator.

Energy simulator is a five-stage pipeline daEnergy simulator is a five-stage pipeline datapath.tapath.

Compilation framework of SimplePCompilation framework of SimplePowerower

SimpleScalarGCC

SimpleScalarGAS

SimpleScalarGLD

High LevelComplier

Optimizations

Low LevelComplier

Optimizations

RT LevelOptimizations

SimplePower

Output Module

Energy Statistics

C SourceCode

Assembly Object file

Core energy

Memory energyBus energy

I/O Pads energy

Executables

Energy Simulator of SimplePowerEnergy Simulator of SimplePower

Power Estimation Tool: PACTPower Estimation Tool: PACT

Designed from Northwestern Designed from Northwestern University.University.

Power-Aware Architecture and Power-Aware Architecture and Compilation Techniques.Compilation Techniques.

Take an application written in the C Take an application written in the C programming language.programming language.

Generate power-efficient and Generate power-efficient and performance-efficient code for performance-efficient code for embedded system.embedded system.

The Architecture of PACTThe Architecture of PACT

ConclusionConclusion

Power consumption is a serious Power consumption is a serious problem for SoC design.problem for SoC design.

Techniques that have been tried on Techniques that have been tried on real designs in the past are real designs in the past are described.described.

Some power estimation tools which Some power estimation tools which estimate the power consumption of estimate the power consumption of embedded systems.embedded systems.

ReferenceReference W. Fornaciari, P. Gubian, D. Sciuto, and C. Silvano, “Power EstimW. Fornaciari, P. Gubian, D. Sciuto, and C. Silvano, “Power Estim

ation of Embedded Systems: A Hardware/Software Codesign Appation of Embedded Systems: A Hardware/Software Codesign Approach”, IEEE Tran. On Very Large Scale Integration (VLSI) Systeroach”, IEEE Tran. On Very Large Scale Integration (VLSI) Systems, Vol. 6, No. 2, pp.266-275, 1998.ms, Vol. 6, No. 2, pp.266-275, 1998.

W. Ye, N. Vijaykrishnan, M. Kandemir, and M. J. Irwin, “The DesigW. Ye, N. Vijaykrishnan, M. Kandemir, and M. J. Irwin, “The Design and Use of SimplePower: A Cycle-Accurate Energy Estimation Tn and Use of SimplePower: A Cycle-Accurate Energy Estimation Tool”, Design Automation conference, 2000.ool”, Design Automation conference, 2000.

L. Benini, A. Bogliolo, and G. De Micheli, “A Survey of Design TecL. Benini, A. Bogliolo, and G. De Micheli, “A Survey of Design Techniques for System-Level Dynamic Power Management”, IEEE Thniques for System-Level Dynamic Power Management”, IEEE Tran. On Very Large Scale Integration (VLSI) Systems, Vol. 8, No. 3, ran. On Very Large Scale Integration (VLSI) Systems, Vol. 8, No. 3, pp.299-316, 2000.pp.299-316, 2000.

V. Tiwari, D. Singh, S. Rajgopal, G. Mehta, R. Patel, and F. Baez, “V. Tiwari, D. Singh, S. Rajgopal, G. Mehta, R. Patel, and F. Baez, “Reducing Power in High-performance Microprocessors”, 35th DReducing Power in High-performance Microprocessors”, 35th Design Automation conference, 1998.esign Automation conference, 1998.

A. Sinha and A. P. Chandrakasan, “JouleTrack – A Web Based ToA. Sinha and A. P. Chandrakasan, “JouleTrack – A Web Based Tool for Software Energy Profiling”, Design Automation conferencol for Software Energy Profiling”, Design Automation conference, 2001.e, 2001.