programmable logic design grzegorz budzy ń lecture 3: fpga ... · analyzer, and virtual i/o...
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ProgrammableProgrammable LogicLogic DesignDesign
Grzegorz BudzyGrzegorz Budzyńń
LLectureecture 3:3:FPGA FPGA -- programming environmentprogramming environment
Plan• Introduction
• Xilinx ISE
– ISE WebPack features
– Logic Edition features
– Embedded Edition features
– DSP Edition features
• Xilinx Vivado
Introduction
• Each larger producer has its own
programming environment
• Main functions:
– VHDL/Verilog/ABEL editor
– Synthesizer
– Fitter
– Simulator
What is VHDL?
VHDL is a way of describing the operation
of a system
Design flow
RTL – what is that?
• RTL – Register Transfer Level
• A design abstraction which models a
synchronous digital circuit in terms of the flow
of digital signals between hardware registers,
and the logical operations performed on those
signals
• Intermediate level between HDL and actual
wiring
• Like .obj file in C or ASSEMBLER
Xilinx ISE environment
Xilinx ISE - introduction
• Xilinx delivers its software free of charge (with
some limitations)
• There are five versions of the software:
– ISE WebPack
– Logic Edition
– Embedded Edition
– DSP Edition
– System Edition
Xilinx ISE - introduction
ISE WebPack features
Project Navigator• Project Navigator integrates the tools and gets
design process started quicker in an easy-to-use graphical interface
• All Editions of the ISE® Design Suite include the ISE Project Navigator which provides:
– project and design source management,
– easy access to running all necessary steps in the ISE design flow,
– access to viewing and analyzing design results
Project Navigator
Project Navigator• All Editions of the ISE® Design Suite include the ISE
Project Navigator which provides:
– access to intuitive Architecture Wizards and IP catalog,
– language templates,
– graphical tools to assist with I/O planning,
– constraint entry,
– design analysis,
– ISim HDL simulator,
– error navigation to Answer Records on the Web
– much more.
Project Navigator
ISE WebPack features - CORE
CORE generator system
CORE generator system
• Xilinx CORE Generator™ System accelerates design
time by providing access to highly parameterized
Intellectual Properties (IP) for Xilinx FPGAs and is
included in the ISE® Design Suite
• CORE Generator provides a catalog of architecture
specific, domain-specific (embedded, connectivity
and DSP), and market specific IP (Automotive,
Consumer, Mil/Aero, Communications, Broadcast
etc.).
CORE generator system
• User-customizable IP functions range in complexity from commonly used functions, such as memories and FIFOs, to system-level building blocks, such as filters and transforms.
• Using IP blocks can save days to months of design time. The highly optimized IP allows FPGA designers to focus efforts on building designs quicker while helping bring products to market faster.
CORE generator system
CORE generator system
ISE WebPack features - PlanAhead
PlanAhead Design Analysis Tool
PlanAhead Design Analysis Tool
• The PlanAhead environment enables
exploration and experimentation with various
implementation strategies
– Without running synthesis!
– All resources are supported
– All FPGA families are supported
– 100x faster then synthesis
– 15.4% accuracy �
PlanAhead Design Analysis Tool
• PlanAhead - design and analysis software
• Streamlines design iterations between synthesis and implementation
• Implementation and timing results can be viewed to easily analyze critical logic, and make targeted decisions to improve design performance with floorplanning, constraint modification, and multiple implementation tool options
• This helps to make tradeoffs between RTL Coding and Synthesis and Implementation, with extensive design exploration and analysis features.
PlanAhead Design Flow
ISE WebPack features - Simulator
XST synthesis tool
• Xilinx Synthesis Technology (XST) allows
synthesis of HDL designs to create Xilinx
specific netlist files
• Specially optimized algorithms to leverage the
advanced architectures of the Xilinx FPGA
families,
• XST offers designers a low-cost design solution
to achieve optimal design results.
ISE simulator
ISE simulator - features
• Mixed language support
• Supports VHDL-93 and Verilog 2001
• Native support for all HardIP blocks
– PPC, MGT, PCIe, etc.
– No special license requirements
• Multi-Threaded compilation
• Post-Processing capabilities
ISE simulator - features• Standalone Waveform viewing capabilities
• Debug capabilities
– Waveform tracing, waveform viewing, HDL source debugging
– Power Analysis and optimization via SAIF
– Memory Editor for viewing and debugging memory elements
• Integrated with ISE Design Suite
– Easy to use - One-click compilation and simulation
• In-built Xilinx simulation libraries
– Additional mapping or compilation not required
Logic Edition features
ChipScope Pro• Without
• With
ChipScope Pro• ChipScope™ Pro tool inserts logic analyzer, bus
analyzer, and virtual I/O low-profile software cores
directly into the design,
• This allows viewing any internal signal or node,
including embedded hard or soft processors,
• Signals are captured at or near operating system
speed and brought out through the programming
interface, freeing up pins for the design
• Captured signals can then be analyzed through the
included ChipScope Pro Logic Analyzer.
Partial reconfiguration• Partial Reconfiguration (PR) is the ability to
dynamically modify blocks of logic by downloading partial bit files while the remaining logic continues to operate without interruption
• PR technology allows designers to change functionality on the fly, eliminating the need to fully reconfigure and re-establish links, dramatically enhancing the flexibility that FPGAs offer
Power Optimization
• Power Optimizing tool automatically neutralizes unnecessary logic activity, reducing dynamic power usage up to 30%
• Set of algorithms automatically identifies and neutralizes unnecessary logic activity, a primary contributor to dynamic power inefficiencies
• These algorithms utilize the abundant clock enables (CE) found in the Virtex®-6 FPGA. Each CE is ideally suited for power optimization as it connects to the basic cluster of the Virtex-6 FPGA fabric (the Slice) and controls a small number of registers (only eight).
Embedded Edition features
MicroBlaze Soft Processor Core• The MicroBlaze™ core is a 32-bit RISC Harvard
architecture soft processor core with a rich instruction set optimized for embedded applications.
• The MicroBlaze soft processor solution, givescomplete flexibility to select the combination of peripheral, memory and interface features that will give the user the exact system you need at the lowest cost possible on a single FPGA.
MicroBlaze Soft Processor Core
Software Development Kit• SDK includes:
– Feature-rich C/C++ code editor and compilation environment
– GNU GCC and GDB support for PowerPC and MicroBlazeprocessors.
– Project management
– Application build configuration and automatic makefilegeneration
– Error navigation
– Well integrated environment for seamless debugging and profiling of embedded targets
– Hardware test programs and application examples
– Full support for FPGA download and debug
DSP Edition features
System Generator for DSP• System Generator for DSP™ is the high-level
tool for designing high-performance DSP systems using FPGAs:
– Development of highly parallel systems with the industry’s most advanced FPGAs
– Providing of system modeling and automatic code generation from Simulink® and MATLAB® (The Mathworks, Inc.)
– Integration of RTL, embedded, IP, MATLAB and hardware components of a DSP system
System Generator for DSP• Key features:
– DSP modeling
– Automatic code generation of VHDL or Verilog
from Simulink
– Hardware co-simulation
– Xilinx Power Analyzer (XPA) Integration
– Hardware / software co-design of embedded
systems
System Generator for DSP - simulink
System Generator for DSP - simulink
Xilinx Vivado
Thank you for your attention
Vivado• Vivado Design Suite is a IP and system-centric
design environment built from the ground up to accelerate the design of not only programmable logic in FPGAs but the design of ‘All Programmable’ SoCs and 3D ICs
• Supports largest FPGA and SoC devices(Virtex-7 and Zynq series)
Vivado – design flow
Vivado – IP-centric Design
• The IP-centric design flows shorten time to integration, turning designs and algorithms into reusable IP that can be abstractly and accurately assembled
• An interactive design and verification environment enabling creation and verification of a hierarchical system by graphically using interface level connections
Vivado – ESL Design• ESL - Electronic System Level Design
• Engineers can quickly simulate, analyze and modify the design without being distracted with implementation details
• C, C++ or SystemC can be used – it istransformed into RTL implementation
• Matlab/Simulink support
• Library of ready DSP algorithms
Vivado – Verification and Debug• Integrated mixed VHDL / Verilog simulator
• Hardware Co-Simulation - part of the code canbe simulated in hardware:
– Simulation up to 100x faster
– Bridge between software simulation and on-chip debug
• Logic Analyser based on ChipScopePro
Vivado – Implementation• Extensive use of multiple cores and modified
source architecture results in:
– Up to 4x faster run times
– Up to 2x reduced memory „consumption”
• Provides early access to critical design metrics such as power, timing, and resource utilization
• Vivado Design Suite analytical place and route technology delivers more predictable design closure by concurrently optimizing for congestion, wire length, and timing
Thank you for your attention
References
[1] www.xilinx.com
[2]
http://www.xilinx.com/support/documentation/sw_manuals/xilinx20
12_2/ug871-vivado-high-level-synthesis-tutorial.pdf
[3] www.wikipedia.org