retargetablecompiler and asip design exploration -...

2000-11-02 시스템 설계 방법론 및 자동화 1

Retargetable Compiler and ASIP Design Exploration

Presented by

마 영 란


Contents

nn VLIW DSPVLIW DSP

n Retargetable Compilation Environment

n Architectural Description Language

n Processor Evaluation


Multimedia System Architecutre


ASIP for DSP systems

n Time-critical

n Processing intensive

n High-quality retargetable compilersn Design specific optimizationn Retargetability

n Various functional unitsn types and numbers


ASIP for DSP systems(cont’d)

n Complex memory systemsn Distributed memory organization

n Cf. centralizaed register files

, ,n Clustered register files

n Increased execution latencyn Powerful optimizing compilers

3Narea ∝3Npower ∝2/3Ndelays ∝


VLIW ASIP design

n Texas Austin


VLIW ASIP design (cont’d)

n Retargetable Compilersn Data partitioning, allocation&binding to

memory banksn Data transfers among clustered register

filesn Enhancing performance

n Increase parallelism by pipelining loop iterations


VLIW ASIP design (cont’d)

n Code generation for VLIW ASIPn Hierarchical, iterative comilation

n Relaxed model

ex) unlimited local storage capacity but

retain a finite interconnection capacityn Increasingly precise models

n Quasi-machine-independent intemediatecode


Contents

n VLIW DSP

nn RetargetableRetargetable Compilation EnvironmentCompilation Environment




Retargetable Compilation Environment

n CHESS : a retargetable C compilern BRIDGE : a retargetable linkern CHECKERS : a retargetable instruction-

set simulatorn DARTS : a retargetable assembler and

diassemblern CHECKMATE : a processor specific

toolkit for DSPn Go : an HDL generator


Retargetability through nML


Design project outline


Architectural scopen Arithmetic specialization

n Time stationary code typen Not support multi-cycle inst.n Pipelined code as a separate inst.

n Orthogonal and encoded inst. Format

n Register-register architecture

n Both homogeneous and heterongeneous register structure

n A specific calling convention

Simpler processor’s controller


Compiler System


Contents

n VLIW DSP


nn Architectural Description LanguageArchitectural Description Language



Architectural Description Languages

n SOC demands …n Repidly exploring design space

n Using cycle-accurate instruction set simulator and retargetable optimizing compiler

The structure of the processorThe structure of the processor

The instructionThe instruction--setset


Related ADL : IS ADL

n nML n Describes an attributed grammern CHESS , not support multi-cycle, multi-word

n ISDL n For code generationn Explicitly specfication of parallel contraints

n Valen-Cn Not to capture resource conflicts, timing

info. for pipelining.


Related ADL : structure

n MIMOLAn Net-list of target processorn For processor synthesis & code gen.n Poor in instruction set extraction

n LISAn Operation-level description of the pipelinen For retargeting simulatorn Not support detailed compiler opt. Info.


Related ADL : mixed

n FLEXWAREn CodeSyn code generator & IS simulatorn VHDL model of a generic parametersn No clear in resource conflicts, memory subsystems

n MDesn For design space explorationn Various info. in sections

n Resource-usage, latency, operation, register, etc.

n Restricted retargetablity

n EXPRESSION


EXPRESSION


Memory subsystem description

n Types and attributes of various storage


Reservation table gen.


Design space exploration

n Separate structural info.n Changes are simply

described


ADL Comparison


Contents

n VLIW DSP



nn Processor EvaluationProcessor Evaluation


ASIP Codesign flow chart


Proposed methodology


Architecture representationn Functional units

n Types, associated operations, delay properties

n # of registers

n # of operation slots in each inst.

n Restrictions on mapping operations to slots

n Concurrent load/store operations

n Latency of an operationn Depends on the functional unitn Independent of the functional unit


Application parameters


Processor evaluation


Extracted Parameters


Estimation Results


Referencen Margarida F. Jacome, Gustavo de Veciana, Design

Challenges for New Application-Specific Processors, IEEE Design & Test of Computers, 2000

n Ashok Halambi, and et. al. , EXPRESSION:A Language for Architecture Exploration through Compiler/Simulator Retargetability, 1999

n T.V.K. Gupta and et. al. , Processor Evaluation in an Embedded Systems Design Environment, ICVD, 200

n Michael Gschwind, Instruction Set Selection for ASIP Design, CODES ’99.

n J-G Cousin and et. al., Multi-Algorithm ASIP Synthesis and Power Estimation for DSP Applications, ISCAS, 2000

n CHESS/CHECKERS:A Retargetable DSP Compilation Environment – Technical White Paper - , version 2.7. 1999

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