sequential logiclogis desin

7/27/2019 Sequential Logiclogis Desin

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Sequential Logic

Combinatorial components: the output values

are computed only from their present input

values.

Sequential components: their output valuesare computed using both the present and past

input values.

Sequential circuits can contain only a finite

number of statesfinite state machines

Synchronous and Asynchronous


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Sequential Circuits

Contains Memory Elements Asynchronous sequential circuits change their state

and output values when input changes

Synchronous sequential circuits change their outputvalues at fixed points of time, which are specified by therising or falling edge of a clock signal

Clock period is the time between successive transitionsin the same direction

Active highstate changes occur at the clocks rising

edge( on higher voltage) Active lowstate changes occur at the clocks falling

edge( on lower voltage)


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4 Basic types of Flip-Flops

SR, JK, D, and T JK ff has 2 inputs, J and K need to be

asserted at the same time to change thestate

D ff has 1 input D (DATA), which sets the ffwhen D = 1 and resets it when D = 0

T ff has1 input T (Toggle), which forces theff to change states when T = 1

SR ff has 2 inputs, S (set) and R (reset)that set or reset the output Q whenasserted


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Gated D-Latch

Ensures S and R inputs never equal to 1 at the

same time

Useful in control application where setting or

resetting a flag to some condition is needed

Stores bits of information

Constructed from a gated SR latch and a Data

latch


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D Flip-Flop

Characteristics :

Synchronous

Avoids the instability of RS flip-flop

Retains its last input value

To set the ff, place 1 on D input and pause the CK input

To reset, place 1 on D input and pause the CK input

D Q+

0

1

0

1Q+ = Next State


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JK Flip Flop

J Set

K Reset

J = K = 0 output does not change

J = K = 1 invert the outputs


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Clocked JK Flip Flop


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T Flip-Flop

T Q+

0

1

Q

Q

T = 1 force the state change

T = 0 state remain the same

Q

QSET

CLR

DT


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D and JK Flip-Flop

Q

QSET

CLR

D D Q+

0

1

0

1

J

Q

Q

K

SET

CLR

J K Q+

0 0

0 1

1 0

1 1

Q

0

1

Q


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How to use JK to implement D Flip-Flop

D Q+

0

1

0

1

J K Q+

0 0

0 1

1 01 1

Q

0

1Q

D ffs property:When in = 0, the out(Q+) = 0.

When in = 1, the out(Q+) is 1

invert K

invert K

J

Q

Q

K

SET

CLR

D


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How to use JK to implement T Flip-Flop

T Q+

0

1

Q

Q

J K Q+

0 0

0 11 0

1 1

Q

01

Q

T ffs property:When in = 0, the out(Q+) = no change

When in = 1, the out(Q+) is = complement

No change

State changeJ

Q

Q

K

SET

CLR

T


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How to use D to implement JK Flip-Flop

KQ 00 01 11 10

J 0

1

0(Q) 1(Q) 0 0

1 1 0(Q) 1(Q)

J K Q+

0 0

0 1

1 01 1

Q

0

1Q

D Q+

0

1

0

1D = JQ + KQ

(Q ) = no state change

(Q) = state change


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How to use D to implement JK Flip-Flop

D = JQ + KQ

J

K

Q

QSET

CLR

D


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How to use T to implement JK Flip-Flop

KQ 00 01 11 10

J

0

1

0 0 1 0

1 0 1 1

J K Q+

0 0

0 1

1 01 1

Q

0

1Q

T Q+

0

1

Q

Q

T = KQ + JQ


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How to use T to implement JK Flip-Flop

T = KQ + JQ

Q

QSET

CLR

DT


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How to use D to implement T Flip-Flop

T Q+

0

1

Q

Q

Q+ 0 1

T 0

1

0 1

1 0

D = TQ + TQ

D Q+

0

1

0

1


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How to use D to implement T Flip-Flop

Q

QSET

CLR

D

D = TQ + TQ

T


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How to use T to implement D Flip-Flop

T Q+

0

1

Q

Q

D Q+

0

1

0

1T = DQ + DQ

Q+ 0 1

D

01

0 11 0


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How to use T to implement D Flip-Flop

Q

QSET

CLR

DT

T = DQ + DQ

D


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SR-Flip Flop

S R Q Q

0 0

1 0

0 1

1 1

Q Q

1 0

0 1

0 0

S R Q Q

1 1

0 1

1 0

0 0

Q Q

1 0

0 1

1 1

RESET

SET

SET

RESET


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SR-Flip Flop

Asynchronous

If S=0 and R=1, Q is set to 1, and Q is

reset to 0

IF R=0 and S=1, Q is reset to 0, and Qis set to 1

If S=1 and R=1, Q and Q maintain their

previous state

If S=0 and R=0, a transition to S=1,R=1 will cause oscillation

Q

QSET

CLR

S

R


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Clocked SR Flip-Flop

Similar to SR Flip-flop but

with extra control input C,

which enables or disables

the operation of S and R

inputs.

C=1 EnabledC=0 Disabled,circuit persists in

preceding state

Q

QSET

CLR

S

R


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Instability

RS flip-flops can become unstable if both

R and S are set to 0

All sequential elements are fundamentally

unstable under certain conditions

Invalid transitions

Transitions too close together

Transitions at the wrong time


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Edge and level-triggered Flip Flop

Digital circuit often form loops, flip-flopsoscillations can

Oscillation will not occur because by

the time an output change cause aninput change, the activating edge of theCK signal will be gone

Positive edge triggered ff responds to

a positive going edge of clock Negative edge triggered responds toa negative-going edge


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Positive-edge-triggered D Flip-Flop

When CLK=0 the

masterlatch is open

and the content of D is

transferred to QM

When CLK=1 themasteris closed and

its output is transferred

to the slave

Master and slave

latches are neverenabled at the same

time


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References

www.play-hookey.com/digital

www.infopad.eecs.berkeley.edu/~icdesign/

SLIDES/slides6.pdf

www.cs.mun.ca/~paul/cs3724/material/we

b/notes/node14.html

Dos Reis, Assembly Language and

Computer Architecture Using C++ and

Java

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