sidecar asic @ eso

Instrumentation Division

April 24, 2023 1

SIDECAR ASIC @ ESO

Reinhold J. Dorn and the IR detector department

Instrumentation Division - European Southern Observatory


April 24, 2023 2

What is a SIDECAR ASIC ?

SIDECAR™- system image, digitizing, enhancing, controlling, and retrieving -

ASIC - Application Specific Integrated Circuit -

The ASIC is a controller on a single Chip designed for use in Teledyne Imaging Sensors FPAs including the 2048 x 2048 HAWAII-2RG™ and other detectors


April 24, 2023 3

ASIC @ ESO – LCC package

< 100 mW at 100 kHz 32 – channel operation Chip dimensions ~ 22mm x 15 mm using deep submicron CMOS processing

Only requires one power supply, one fixed reference and one master clock for operation


April 24, 2023 4

SIDECAR ASIC


April 24, 2023 5

ASIC Floorplan


April 24, 2023 6

JADE card on the outside

ESO- ASIC cryogenic setup inside cryostat


April 24, 2023 7

SI-PIN/Visible hybrid Hawaii2RG detector

A silicon pin hybrid detector has close synergy with IR (HgCdTe) detectors.

Picture of the Hybrid Visible Silicon Imager (HyViSI) used for testing the SIDECAR ASIC

It is a complementary metal oxide semiconductor (CMOS) alternative to charge coupled devices (CCDs) for photons at optical wavelength.

2k x 2k format with 18 micron pixels

Main difference: SI-PIN array is a fully depleted bulk detector , IR array is a per pixel depleted detector.


April 24, 2023 8

ESO- ASIC performance improvements

Images: ASIC / HyViSI single double correlated reads

STEP 1 STEP 2 STEP 3

STEP 1: Supply clean 5V to JADE card and insulate USB connection with Fiber converter

STEP 2: Measure right conversion factor and remove channel offsets with reference pixels,ground ASIC substrate to analog ground

STEP 3: Fix and tune microcode and ASIC for low noise performance


April 24, 2023 9

HyViSI / ASIC conversion factor

Histogram of Hawaii-2RG Si-PIN HyViSI array exposed to Fe55 X-ray source.

The same data set is plotted with nodal capacitances derived from capacitance comparison method (solid histogram) and shot noise method (dashed histogram).

Interpixel coupling attenuates poisson noise and introduces error of up to 50 % for the conversion factor.

IR detector lab makes first prove with FE-55 measurements on HyViSI detector.

ESO also developed direct method to measure nodal capacitance (see G. Finger this conference).

Shot noise: Cnode=28.5 fF

Capacitance comparison: Cnode=13.9 fF

In this case the shot noise method is wrong !

Wrong

Literature Fe55:1620 e/event

Capacity comparison:C0=13.9 fF86.8 e/mV

Shot noise:C0=28.5 fF178 e/mV

Literature Fe55:1620 e/event

Capacity comparison:C0=13.9 fF86.8 e/mV

Shot noise:C0=28.5 fF178 e/mV


April 24, 2023 10

HyViSI pixel crosstalk – optical spot test

Focused optical spotNormalized signal surface plot

Photometric analysis

• Due to interpixel capacitance 43.5 % of the total energy is seen in neighboring pixels (Vsub=10V)• Coupling to closest neighbor pixel is around 8 to 10 %.• Effect includes deterministic scattering mechanism and diffusion (1.5%).


April 24, 2023 11

HyViSI / ASIC conversion factor (FE-55)

FE-55 is a radioactive source that emits X rays at three energy levels (5.9 KeV (Mn K line), weaker peak at 6.5 KeV (Mn K) and the third at 4.12KeV (K escape line).

HyViSI FE-55 histogram: Conversion factor 1.47 e/ADU

FE-55 events on the detector

FE-55 source installed on the window

When these Xrays are absorbed by silicon they produce large photoelectron events K 1620 electrons, K 1778 electrons and the K escape peak 1133 electrons.

The K line was used to calibrate the conversion gain (needs photometric analysis)


April 24, 2023 12

HyViSI / ASIC conversion factor (Histograms)

Conversion factor 1.47 electrons / ADU Conversion factor 0.54 electrons / ADU


April 24, 2023 13

HyViSI / ASIC conversion factor (calculation)

This is consistent with a conversion factor 1.47 e/ADU from the HyViSI FE-55 histogram.

The ASIC Pre-Amp Amplifier is capable of gain -3dB to 27dB gain in 3dB steps. A gain setting of 9db gives corresponds to a gain of 2.83.

How is conversion gain and nodal capacity related?

Electronic gain of the preamp is 2.83 and the nodal capacitance is 13.9 fF.

and the conversion factor is: ADUe

gGsc 53.1

with q

CG 0

c is the conversion factor in electrons/ADU

s is ADC sensitivity 3.3V/216= 50 x10-6 Volt/ADU

g is electronic gain of the preamp G is conversion gain in electrons/Voltq is the electron charge 1.60218 x 10-19

C or As


April 24, 2023 14

HyViSI quantum efficiency

In the past the Quantum efficiency measurements have been interpreted wrong due to the overestimation of the nodal capacity (conversion factor).

Now measured data fits well to modeled values from Rockwell.

Quantum efficiency HyViSI

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

300 400 500 600 700 800 900 1000 1100

wavelength [nm]

QE

120 K

140 K

160 K

180 K

200 K

Teledyne modeled data

In the near IR the QE depends on operating temperature. As the temperature get lower, the photon absorption length increases (bigger Si bandgap).


April 24, 2023 15

HyViSI / ASIC Refpixel subtraction

Due to KTC noise at the input of the ASIC preamp the 32 channels show a slightly different offset level for a difference image. This can be compensated by subtracting the mean of the reference pixels on the top or bottom for the corresponding channels.

DC read without ref. pixel subtraction DC read with ref. pixel subtraction

ch1=DC1[0:63,0:2047]*1.0ch1ref=ch1[0:63,0:3]*1.0meanvalue=mean(ch1ref)ch1clean=ch1-(meanvalue)

i.e. for the first channel:


April 24, 2023 16

ASIC preamp functional diagram• This is a simplified schematic representation of the Amplification block. • The open/closed condition of each switch depends on the state of the Pre-Amp with has 4 operational states. • An internal state machine regulates the Pre-Amp state transitions and the correct position of the switches.


April 24, 2023 17

ASIC preamp

V1 to V4=GND Noise Stdev=3.6 ADU

The ASIC preamp can be used to measure noise of the operating voltages by means of feeding desired voltages to the preamp inputs.

This allows fine tuning of voltages for low noise performance.

By setting all inputs to ground the ADC conversion noise can be measured.

Present microcode is optimized for low power consumption of the ASIC but higher noise.

Fine tuning buffers, voltages and ADC gives lower noise but increases power consumption.


April 24, 2023 18

ASIC @ ESO - two ways to operate the ASIC now available

ASIC, JADE2 card, bare MUX• Windows based system• USB2 link to PC • Detector is read via IDE and IDL interface

ASIC, ESO card, bare MUX• LINUX based system• Fiber link to PC • Detector is read with NGC software (NGC GUI, RTD, etc.)


April 24, 2023 19

ASIC, JADE2 card, bare MUX - IDL/GUI and Image DISPLAY


April 24, 2023 20

Picture of the NGC@ASIC interface card

VIRTEX 2 pro

Fiber interface

Connector to ASIC

Power 5 Volts

see M. Meyer this conference


April 24, 2023 21

NGC@ASIC

Back-End PCI in LINUX Workstation

FPGA

Fiber Duplex

Connection RxTx

RxTx

NGC2ASIC Interface

FPGA

RxTx

RxTx

ASIC

CLOCK

COMUNICATION

SCIENCE DATA

POWER

H2RG

LVDS Connections

Detector Signals

Communication Channel to/from ASIC and Receiver of Science Data from ASIC all mapped on NGC Fiber link

At present the communication link between the ASIC and the NGC interface is a single LVDS line having a bandwidth of 50MBit.

This limits the minimum readout time of the Hawaii2RG array to 1.7 seconds.

In a next step the VHDL code of the NGC interface will be changed to make use of 16 parallel data lines thus increasing the bandwidth to ~ 400Mbit.

This will reduce the readout time of the Hawaii2RG to 200 ms.


April 24, 2023 22

NGC and ASIC Backend

Back-End PCI is a module with connection to a 64 Bit PCI bus.

• Function is based on the XILINX Virtex Pro FPGA• The slave IF is used for communication. • The master IF is used for video data DMA transfers to PCI. • Two RocketIO transceivers ( 2.5 GBit each) are used for Communication and data transfers, other options to increase bandwidth are possible ( one FPGA contains 8 transceivers – space limit for PCI card size might be four ).

NGC PCI Backend card

ASIC interface card

FiberDuplex

Connection


April 24, 2023 23

ASIC implementation - NGC GUI Picture of the IR lab obtained with ESO card, H2RG detector and ASIC

see J. Stegmeier this conference


April 24, 2023 24

ASIC / HxRG code

Multiplexer type (H1RG, H2RG, or H4RG) and more

Optical and IR HxRG detectors

Number of detector outputs used (1,2,4,16,32)

Number of SIDECAR ADCs averaged per output (1,2,4, 8)

Cold or Warm operating temperature

Pre-Amp gain, reset scheme, reference and current sourcing

Buffered or Unbuffered mode on HxRG detector

Horizontal clocking and pixel reset scheme (line by line, pixel by pixel, global)

DC, Up the ramp or Fowler exposure settings (free to program)

Window mode

ASIC / HxRG code provides all functionality possible with HxRGs


April 24, 2023 25

Performance: Readout noise DC read

DCS with HyViSI and ASIC: Readout noise 7 electrons with 0.54 e/ADU conversion factor

Performance: Readout noise 30 Fowler pairs

30 Fowler pairs with HyViSI and ASIC: Readout noise 2.7 electrons with 0.54 e/ADU conversion factor


April 24, 2023 26

Readout performance


April 24, 2023 27

Highlights ASIC now embedded in ESO hard and software standards

Development of new interface card and software development under LINUX– replacing the JADE USB2 card

Tested SIDECAR ASIC in 32 channel mode with a H2RG (HyViSI) from Teledyne Scientific Imaging reading at a pixel rate of 100 KHz operating at cryogenic temperatures.

ASIC delivers “almost” equal noise performance compared to NGC and IRACE with HxRG arrays

Demonstrated read noise as low as 7 electrons for a DCS and as low as 2.7 electrons with 30 Fowler pairs.

The ASIC readout electronics facilitates a great simplification to system design.

Full systems needs less than 3 Watts and only one 5 Volts power supply

ASIC systems including power supply less then 1 Kg


April 24, 2023 28

HyViSI readout noiseReadnoise was measured as a function of Folwer pairs at different temperatures.

Strong temperature dependence which can not be explained by Johnson noise but follows 1/sqrt(n) for Fowler sampling. The reason known but has been addressed to the manufacturer.

• 6 electrons for a single DC read (readtime ~1 sec)

• as low as 1.8 electrons for 30 Fowler pairs (readtime ~25 sec)

(at 115 Kelvin with a conversion gain measured with the FE-55 method).

Note that the readnoise does not improve with more samples.

0 5 10 15 20 25 300

2

4

6

8

10

12

14

Number of fowler pairs

read

outn

oise

[ele

ctro

ns]

HyViSI readnoise versus fowler pairs

105 K110 K115 K120 K125 K130 K135 K140 K145 K150 K155 K160 K


April 24, 2023 29

HyViSI – Residual imagePersistence is the remaining signal apparent in a series of dark exposures after the detector has beenexposed to a bright radiation source. This residual image is a function of flux of the previous

exposure.

330Ke

0

1

2

3

4

5

x 105

0100

200300

400500

600

-5

0

5

10

15

20

25

time [s]

Remanent signal HyViSI

prior signal flux [photons]

rem

anen

t sig

nal [

e/pi

xel]

25s 75s

150s

225s 475s

Decay of residual image intensity as a function of time and prior signal flux.


April 24, 2023 30

HyViSI dark current

Dark current bottoms out at 3x10-3 electrons/sec below 140 Kelvin for this eng. device.

Darkcurrent values might be lower with science grade devices but for the eng. grade the dark current is around a factor 10 higher than that of scientific CCDs [green curve].

100 120 140 160 180 200 22010

-4

10-3

10-2

10-1

100

101

102

103

Temperature [Kelvin]

Dar

k cu

rrent

[ele

ctro

ns/s

ec/p

ixel

]

Measured dark current HyViSI detector

darkcurrent HyViSIdarkcurrent typ. CCD 1e/h


April 24, 2023 31

SI-PIN/Visible hybrid device architectureMain difference:SI-PIN array is a fully depleted bulk detector

IR array is a per pixel depleted detector.

Properties of SI-PIN arrays:• 100 % fill factor

• High electric field strength (Vsub ~10 Volts)

• Lower integrating node capacity than IR detectors => lower noise

• Fully depleted bulk => good QE

• All features of the Hawaii2RG multiplexer can be used

SI-MULTIPLEXER (ROIC)

Vsub (bias voltage)hv-Photons

fully depleted bulk (SI)

Implant

oxide

AR-Coating on surface

E-Field

Indium bump

metal grid or field plate

Silicon Hybrid Architecture ( backside illumination)

Aluminium contact metal

Note that Hybrids differ substantially from monolithic CMOS where photon detection and readout take place in the same piece of silicon.


April 24, 2023 32

HyViSI pixel crosstalk – single pixel reset

Single pixel resetNormalized signal surface plot Note: Central pixel value reduced to 0.3

Photometric analysis

• Due to interpixel capacitance 42 % of the total energy is seen in neighboring pixels.• Coupling to closest neighbor pixel is around 8 to 10 %.• Effect is deterministic scattering mechanism and not diffusion

Array is uniformly illuminated with high flux and by resetting a single pixel with the guide mode feature of the 2RG mux its value is set to zero.

sidecar asic @ eso

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