single vendor design flow solutions for low power electronics · single vendor design flow...

Single Vendor Design Flow Solutions for Low Power Electronics


• To be the leader in low power electronics circuit design solutions, an EDA vendor must lead in:

• Accuracy - High Precision Analog • Capacity - Large Circuit Simulation • Performance - Fast Simulation Speed • Advanced Simulation Features • Integration - Full Design Flow Solution

Pressure Points on EDA Vendors for Continuous Improvements

- 2 -


The focus point for low power design flow solutions is on simulators. Silvaco offers SmartSpice for analog, SmartSpiceRF

for RF and Harmony for mixed signal simulation.

Single Vendor Design Flow Product Solution

- 3 -


Simulation accuracy depends on SPICE models available and solvers used for solving equations. Solvers - Family of solvers is available for solving different circuit problems. Three direct and two iterative solvers, decoupled from the simulators and used as dynamicially linkable during run time. Each solver has its own release history and all versions are web available for download.

Simulation Accuracy

- 4 -


All commercially available SPICE models suitable for low power electronics are current (modern) and available • Bipolar - VBIC, Mextram, HiCUM • MOS - HiSIM, HiSIM HV, PSP, BSIM3, BSIM4, EKV • Custom developed models in C language or Verilog-A

Models are not part of simulators. They are organized as a separate dynamically linkable library of models, each with its own release and development history. This architecture provides for instant model development, updates and delivery (web based)

Model Accuracy: Advanced SPICE Models

- 5 -


Flexibility to be creative (very important in demanding analog design) is provided by an abundance of advanced features demanded by skillful analog designers: • Topology Checker - Detects opens, shorts, floating connections and other

circuit topology flaws • Bias Condition Checker - Monitors the voltage bias between specified

terminals of the particular device during .TRAN analysis and detects if the voltage bias is too large and breakdown can occur

• Interchangeability of Solvers - Allows changing solvers during run time, for example solver1 for .OP and solver2 for .TRAN

Advanced Features

- 6 -


• Hierarchy Exploitation For Speeding up Circuit Loading - • Takes advantage of the hierarchy of the simulated circuit • Detects expression in the subcircuits (cells) for R, C, L, A devices and places these

expressions into the special structure

• Stop/Recovery for Long Simulations - Stop and recover simulation at designer’s specified run time check point

• SOA - Safe Operating Area monitors the total power consumption of a specified active device and issues a warning if the total power exceeds the specified limit

Advanced Features

- 7 -


• Simulator (SmartSpice, SmartSpiceRF and Harmony) integration with Gateway (Schematic Editor) provides for: • Cross Probing • Marching Waveforms • Back Annotation • Auto Netlist Generation, etc

• Schematic Driven layout integration between Gateway and Expert (Layout Editor) provides for data flow between the circuit topology and layout editor

• The ultimate integration is a design flow of Gateway, Simulators and Expert with a family of Optimizers for automatic generation fo circuit derivatives

Product Integration

- 8 -


64-bit simulators have no upper limit on circuit size. Limitation is only a computing platform

Simulation performance is maintained with: • Full multi-threading on model and solver level (see benchmark results) • Fast pre-processing mode • Binless modeling approach • Pre-complied binaries of model parameter expressions and non-linear

device derivatives • Built-in RC reduction for simulating large designs with significant contents

of RCL parasitics

Large Circuit Simulation

- 9 -


Benchmark Results

- 10 -


• TSMC certified (April 2008) to be 100% HSPICE compatible for models, syntax, analysis, output formats, etc. HSPICE compatibility is maintained since 1992, so legacy designs can be easily supported and HSPICE design flows replaced with SmartSpice

• 100% SPECTRE compatible for models, syntax, analysis output formats etc., since 2006

• Seamlessly integrated into Analog Artist environment by using Cadence internal data formats and commutations protocols therefore not needing any more buggy CDS SPICE and OASIS simulation environment

HSPICE/Spectre Compatibility

- 11 -


• Unlimited site licensing and modern Universal and EDA Token licensing allow design houses to build cost effective designs flows

Advance Affordable Licensing

- 12 -


Universal Tokens - Provide instant access to all tools without re-issuing licenses. Each tool draws a tool-specific number of tokens from a universal token pool. When a tool is no longer in use, its tokens are automatically returned to the pool for immediate re-use by any tool.

Tokens are purchased on a yearly basis to match ongoing software needs. Peak demand can be accommodated by supplementing the existing token pool with additional tokens purchased on a daily basis. Tokens can be shared between all company locations worldwide. Universal tokens provide an unprecedented Return on Investment (ROI).

Universal Tokens

- 13 -


• Silvaco delivers cost effective, technically modern, most powerful and complete solution for low power electronic design needs

Conclusion

- 14 -

single vendor design flow solutions for low power electronics · single vendor design flow...

Documents