sip and future of semiconductor testsuch as flip-chip redistribution, redistribution interconnect,...

© 2014 Hanyang University ERICA, All rights reserved June 25, 2014

SiP and Future of

Semiconductor Test(SiP와반도체테스트의미래)

Sung Chung, Research Professor


Opening Remark

Definition and overview of SiP Technology

Characteristics of TSV in SiP

JTAG and SiP Test Standards

SiP Test Challenges: TSV

TSV and Interposer Test Examples

Recent System Failure Examples

Conclusions

Q and A

Presentation Outline


Cloud Storage says NOOO!


SiP Device says NOOOooop!

I am your father!

NOOOooop!


Opening Remark







Conclusions

Q and A



System in Package (SiP) is a combination of

multiple active electronic components of

different functionality, assembled in a single

unit that provides multiple functions

associated with a system or sub-system.

A SiP may optionally contain passives,

MEMS, optical components and other

packages and devices.

Definition of SiP

“The next Step in Assembly and Packaging: System Level Integration in the package (SiP),” Assembly and Packaging Technical Working

Group for the ITRS, SiP White Paper V9.0


3D-Packaging (3D-P):3D integration using “traditional” packaging technologies, such as wirebonding, package-on-package stacking or embedding in printed circuit boards.

3D-Wafer-Level-Packaging (3D-WLP):3D integration using wafer level packaging technologies, performed after wafer fabrication, such as flip-chip redistribution, redistribution interconnect, fan-in chip-size packaging, and fan-out reconstructed wafer chip-scale packaging

3D-Integrated-Circuit (3D-IC):3D approach using direct stacking of active devices. Interconnects are on the local on-chip interconnect levels. The 3D stack is characterized by a stack of front-end devices, combined with a common back-end interconnect stack.

3D-Stacked-Integrated-Circuit (3D-SIC):3D approach using direct interconnects between circuit blocks in different layers of the 3D die stack. Interconnects are on the global or intermediate on-chip interconnect levels. The 3D stack is characterized by a sequence of alternating front-end (devices) and back-end (interconnect) layers.

3D-System-on-chip (3D-SOC): SiPCircuit designed as a system-on-chip, SOC, but realized using multiple stacked die. 3D-interconnects directly connect circuit tiles in different die levels. These interconnects are at the level of global on-chip interconnects. This allows for extensive use/reuse of IP-blocks.

Definitions of Suggested Names

Source: ITRS 2011 Interconnect


ITRS 3D IC TSV Roadmap 1

Global Level Interconnect

W2W, D2W, D2D Stacking2009 - 2012 2012 - 2015

Minimum TSV Diameter 4 - 8 µm 2 - 4 µm

Minimum TSV Pitch 8 - 16 µm 4 - 8 µm

Minimum TSV Height 20 - 50 µm 20 - 50 µm

Minimum TSV aspect ratio 5:1 - 10:1 µm 10:1 - 20:1 µm

Bonding Overlay Accuracy 1.0 - 1.5 µm 0.5 - 1.0 µm

Minimum Contact Pitch

Thermo-Compression10 µm 5 µm

Minimum contact pitch

Solder Micro-Bump20 µm 10 µm


ITRS 3D IC TSV Roadmap 2

Intermediate Level Interconnect

W2W Stacking2009 - 2012 2012 - 2015

Minimum TSV Diameter 1 - 2 µm 0.8 - 1.5 µm

Minimum TSV Pitch 2 - 4 µm 1.6 - 3.0 µm

Minimum TSV Height 6 - 10 µm 6 - 10 µm

Minimum TSV Aspect Ratio 5:1 - 10:1 µm 10:1 - 20:1 µm

Bonding Overlay Accuracy 1.0 - 1.5 µm 0.5 - 1.0 µm

Minimum Contact Pitch 2 - 3 µm 2 - 3 µm


2.5D/3D SoC vs. SiP Packaging Roadmap

“3DIC & TSV interconnects 2012 Business update,” Yole Development, Semicon Taiwan 2012


Comparison of SoC/SiP Architecture 1

Market and Financial Issues

Item SiP SoC

Relative NRE cost 1X 4-10X

Time to Market 3 –6 months 6 –24 months

Relative Unit Cost 1X 0.2 – 0.8X

“The next Step in Assembly and Packaging: System Level Integration in the package (SiP),” Assembly and Packaging Technical Working Group for the

ITRS, SiP White Paper V9.0



Technical FeaturesSiP SoC

Pros

Different front end technologiesGaAs, InP, Si, SiGe, etc.

Better yields at maturity this depends upon complexity)

Different device generations Greater miniaturization

Re-use of common devices Improved performance

Reduced size vs. conventional packaging Lower cost in volume

Active & passive devices can be embedded CAD systems automate interconnect design

Individual components can be upgraded Higher interconnect density

Better yields for smaller chip sets Higher reliability (not true for very large die)

Individual chips can be redesigned cheaper Simple logistics

Noise & crosstalk can be isolated better

Faster time to market





Technical Features

SiP SoC

Cons

More complex assembly Difficult to change

More complex procurement &

logisticsSingle source

Power density for stacked die may

be too high

Product capabilities limited by chip

technology selected

Design Tools may not be adequateYields limited in very complex, large

chips

High NRE cost




Opening Remark







Conclusions

Q and A



IMEC 3D TSV Scaling Roadmap

Eric Beyne, Herve Ribot, Jurgen Wolf, Francoise von Trapp, “3D TSV Without Limits Webinar,” 3D InCites, 2013


Resistance-capacitance (RC) of a die-to-die (d2d) via related to a full via stack and signal propagation delays for a d2d via, 1 mm of wire, and a fan-out-of-four (FO4) delay

RC Characteristics of TSV

Loh, Gabriel H. et al, “Processor Design in 3D Die-Stacking Technologies,” in IEEE Micro, vol.27, issue 3, pp. 31-48, 2007


For 22nm technology, delay will be 100ps for the 300µm 2D wire length. In contrast, the TSV with 22nm inverter has about 7ps delay.

TSV Delay Comparison

Ryusuke Egawa et al, “Poster: Exploring Design Space of a 3D Stacked Vector Cache - Designing a 3D Stacked Vector

Cache using Conventional EDA Tools,” IEEE SCC 2012, DOI=10.1109/SC.Companion.2012.271


Small RC Delay1mm top metal

delay: 225 ps

One TSV: 8 ps

Through 20 layers:

12 ps

High density

Interconnect:1 Million TSVs/mm2

Delay: TSV vs. 2D wiring

Hiroaki Kobayashi, “A Multi-Vectorcore Architecture with 3D Die-Stacking Technology,” 14th

Teraflop Workshop, Stuttgart, Germany Dec. 2011


Power: TSV vs. 2D wiring

Hiroaki Kobayashi, “A Multi-Vectorcore Architecture with 3D Die-Stacking Technology,” 14th Teraflop Workshop, Stuttgart, Germany Dec. 2011


For 45nm technology, equivalent 2D wire length to TSV is 100

µm for the TSV with 50µm long and 8µm in diameter

Long wire length and top metal wire increases wire delay

substantially

TSV and 2D Wire Delay

Ryusuke Egawa et al, “Poster: Exploring Design Space of a 3D Stacked Vector Cache - Designing a 3D Stacked Vector Cache using Conventional EDA

Tools,” IEEE SCC 2012, DOI=10.1109/SC.Companion.2012.271

Diameter

(µm)

Length

(µm)

Resistance

(mΩ)

Capacitance

(fF)

8 50 17 94

4 50 68 50

2 50 274 27

1 50 1095 16

0.5 50 4380 10


Within the area of 5 µm diameter TSV, more than

100s of gate in 45 nm technology can be placed

Number of Gates in one TSV Area

Ryusuke Egawa et al, “Poster: Exploring Design Space of a 3D Stacked Vector Cache - Designing a 3D

Stacked Vector Cache using Conventional EDA Tools,” IEEE SCC 2012, DOI=10.1109/SC.Companion.2012.271

High density

interconnect:1 Million TSVs/mm2


TSV Structure and Fault Model

Metal

TSV

Metal

SiO2 TSV Insulator

Silicon Substrate

Leakage Current LiTSV

RTSV

CTSV

Cu

Adopted from Yi Lou & Zhuo Yan, et al.,“Comparing Through-Silicon-Via (TSV)

Void/Pinhole Defect Self-Test Methods,” J of Electron Test (2012) 28:27–38

Example: 32 nm IMEC TSV

TSV Diameter: 5 µm

Pitch min.: 10 µm

Wafer: 25 µm thick

TSV Resistance: 20 mΩ

CTSV: 37 fF at 1 MHzLeakage LiTSV: 1 pA

Leakage RTSV: > 850 MΩ

Density: 105-8 cm2

Fault ModelsBreak defect

Pin hole defect

Open (Void) defect

CMOS


SiO2 TSV Insulator

TSV Fault Models

Metal 1 Metal 1

SiliconSubstrate

TSVTSV

Full open defect

Break defect

Pin-hole Defect

Void Defect

Pin hole defect in SiO2 insulationCreate resistive short

Leakage current increases

Void defect (Open defect) in Cu:Signal is disconnected or

form a resistive path

Create data path signal integrity issues

Partially open defects are

difficult to detect

Break defect in TSV CuCapacitance is reduced and

form a resistive path

May create resistive short

Partially open break defect causes

electro migration and causes latent TSV

failure

Create data path signal integrity issues

Cu Cu


TSV

TSV

TSV

TSV

TSV

TSV

Spare TSV and Repair Types

Shared TSV Method

Signal Shifting Method

Dedicated Spare TSV Method

Signal Switching Method

Signal Routing Method

Combination Shared TSV Method

Basic TSV Redundancy Mechanism

TSV

TSV

TSV

TSV

TSV

2 to 1 Mux

3 to 1 Mux

3 to 1 Mux

2 to 1 Mux

3 to 1 Mux

3 to 1 Mux

3 to 1 Mux

3 to 1 Mux

TSV

TSV

TSV

TSV

TSV

TSV

1 to 4Demux

1 to 4Demux

1 to 4Demux

1 to 4Demux

4 to 1 Mux

4 to 1 Mux

4 to 1 Mux

4 to 1 Mux

TSV

TSV

TSV

TSV

TSV

TSV

TSV

TSV

TSV

TSV

TSV

TSV

1 2 3 4 5 6 7 8 9S1 S2 S3

TSV

S0


Quadruple TSV

16:4 TSV

Redundant TSVs & Stacking Yield

H. Hashimoto et al.,, “Highly Efficient TSV Repair Technology for Resilient 3-D Stacked Multicore Processor

System,” IEEE 3DIC Conference, 2013. DOI 10.1109/3DIC.2013.6702338

Stacking yield is a function of given TSV repair strategy


Mitsumasa Koyanagi et al., “Three-Dimensional VLSI System with Self-Restoration Function,” JST

International Symposium on Dependable VLSI Systems 2013

Overhead and Signal Span


16 signals and 4 Spares

Comparison of TSV Repair Yield

Mitsumasa Koyanagi, “Architecture and Circuits for Dependable 3D-

VLSI,” Tohoku University Sendai, Japan


TSV Characteristics

Etienne Sicard et al., “Introducing 32 nm technology in Microwind35,”

Microwind Application Note

Small RC time delayOne TSV: 8 ps12 TSV layers: 12 ps32nm gate delay: 5 to 6 ps

1mm top metal delay: 225 ps

Electrical parameterTSV Capacitance: 37 fF at 1 MHzLeakage Resistance: > 850 MΩLeakage Current: 1 pA

Testing single pre-bond TSV

for all parametric value

becomes very difficult


Opening Remark







Conclusions

Q and A



JTAG Standard covers all

different variations of current

/ future device needs

JTAG Standard will be fully mature

when 1838 is completed

1149.1 remains backbone of all

variations of JTAG Standard

May expect subsequent update of

existing standard once 1687 and

1838 become active

Genealogy of 1149.1 JTAG Family

AnalogDigital

1149.1 1149.3

JTAG – 1149.1

1149.2 1149.4

1149.5

1149.6

1532

1687

1838

1149.1

System

Device/PCB

AC Coupled

Compact Pin

ISP

3D IC

Memory

1500

Core Test

Instrument

1581Toggle

1149.8.1

1149.7

European JTAG

Active Standard

In Development

Withdrawn/Inactive

DC Coupled

Standard VariationDirectly or Indirectly Supporting Standard

1999 2010

2000 2002

2003 2003

2005 2005

2009 2009

2011 2011

2012 2012

2014? 2014?

1990 1993

1149.11990 2001

2001 2013

1149.1

First Lease

Active Version

EJTAG


P1687 iJTAG (Instrument): in vallot process..Standard methodology for access to embedded test and debug features through IEEE Std. 1149.1This Standard provides a method of adding additional lines and functionality to the JTAG TAP to enable far greater levels of internal testing to be achieved using internal instrumentation

iJTAGIEEE P1687

1. Integrated into existing ICT2. ICT system > P1687 test

solution3. P1687 test solution >

functional test4. Integrated into existing

functional test

Key Differences between JTAG and iJTAG

JTAG iJTAG

Control of internal IPAd hoc method, vendor specific

Standard protocol

External interface to internal instrument and 3rd-party IP

Need information from instrument vendor

Plug-and-play and vendor independent

Coolness Old and boring Fancy and New

Instrument access through hierarchical logic structure

Must be manuallydefined of the JTAG interface

Automated retargeting from TAP to instrument through logic hierarchy

Register size Fixed per instruction Flexible


Analysis of IEEE P1687 network

Farrokh Ghani Zadegan, et al., “Test Time Analysis for IEEE P1687”, IEEE 19th ATS 2010, Shanghai, China, Dec. 2010

The control data for the Segment Insertion Bit (SIB)

is transported on the same wire as test data

Control data is transferred to the status register

when the JTAG state machine does ”apply and

capture”

“CUC”: Apply Capture Update Cycle: 5 clock

cycles in the FSM

Key is to reduce Test Application Time (TAT)


3D TestIEEE P1838

P1838 3D Device Test & DFTStandard for Test Access Architecture

for Three-Dimensional Stacked Integrated Circuits

Scope: The proposed standard is a ‘die-centric’ standard; it applies to a

die that is pre-destined to be part of a multi-die stack and such a die

can be compliant (or not compliant) to the standard

Two Standardized Components3D Test Wrapper hardware per die

Description + description language

Leverage existing DFT wherever Applicable/AppropriateTest access ports: utilize IEEE Std. 1149.x

On-die design-for-test: utilize IEEE Std. 1500

On-die design-for-debug: Utilize IEEE P1687

Web Page http://grouper.ieee.org/groups/3Dtest/

http://grouper.ieee.org/groups/3Dtest/


IEEE1149.7

P1838 uses the largest number of standards to solve 3D test challenges

Relationship between All Standards

IEEE1149.11149.6

IEEE1581

Nexus5001

IEEE1532

EJTAG

SJTAG

IEEEP1687

IEEE1500

IEEEP1838


Opening Remark







Conclusions

Q and A



What to Test? Determine appropriate test contentPre-bond (known good die, pretty good die): Types of tests

for TSVs and die logic

Post-bond (known good stack): TSVs, die logic (cores and

memories), tests for failing new defect types

How to Test? Determine test delivery pathwaysUse of BIST, BOST, or probe access based test

Scan chains, wrappers, test access mechanisms, test

scheduling, debug, diagnosis, and repair

Clock, test data, and TSV repair and configuration

When to Test? Select test flows: cost and benefit

trade-off analysis

SiP Typical Test Objectives


3D TestingTesting at individual die level

Determine Known Good Die (KGD) for stackingTesting at 3D stack level

Final stack test

Individual die test optionsNo TestBuilt-In-Self-Test (BIST) and Built-Out-Self-Test (BOST)Reduced-Pad-Count-Test (RPCT)

3D Testing assumptionsFinal, post-stacking test performed in all casesTest Bottom die

Avoid stacking cost if die is faultyScan chains in place on all stacked dice

To be utilized in the final, post-stacking test

Solving new challenges as we goNo available Test Standard No mature EDA tool setWe haven’t uncovered all defect types yetTSV and interposer pre and mid-bond test pose most challenges

Test is Considered “3D Challenge No. 1”


How Long is Nano-Second?

Maximum Limiting Distance of

electricity can travel in nano

second (10-9 second) is

29.97 cm.

In micro second, electricity can

travel 299.79 meter.

Grace Murray Hopper: Dec. 9, 1906 to Jan. 1, 1992


Light Speed and High Speed

During one Pico Second, light can travel the length of 5.9 TSVsWhen light passes through 2.99 mm, electrons already travel through one TSV

(Based on 5µm diameter and 50µm long TSV with 8 ps signal delay)

Time Variables Speed of Light (Metric) Frequency

One Second 299,792,485 m/sec Hz

Micro-Second (10-6) 299.792 m/micro-sec MHz (106)

Nano-Second (10-9) 29.97 cm/nano-sec GHz (109)

100 Pico-Second (10-10) 2.99 cm/100 pico-sec 10 GHz (1010)

10 Pico-Second (10-11) 2.99 mm /10 pico-sec 100 GHz (1011)

Pico-Second (10-12)0.29 mm/pico-sec

299.79 µm/pico-secTHz (1012)


Scaling analysis of the RLCG of the TSV pair according to ITRS

TSV RLCG Scaling with ITRS

C. Xu, H. Li, R. Suaya, and K. Banerjee, “Compact AC Modeling and Performance Analysis of Through-Silicon

Vias in 3-D ICs,” IEEE Trans. Electron Devices, vol. 57, no. 12, December 2010.

CNT: Carbon Nano Tube

SWCNT: Single Well CNT

MWCNT: Multi Well CNT


SiP Test Needs Better Solution

TSV and Interposer impose new challenges for SiP test

Defect affects differently during pre-bond & post-bond testDuring pre-bond test

Defect makes R and C smallerDefect makes RC time constant shorter

During post-bond testDefect increase electrical maskingDefect makes RC time constant longer

Test parameter changes as stacking continuesIncrease delay and electrical maskingTSV interference and cross talk

Test structure changes as stacking continuesDifferent test for the same level of stack

TSV involves repairRepair changes timing and test resourcesTake PGD instead of KGD


SiP Test Needs Better Solution: cont.

Ownership of repair and cost are not fully definedVague ownership of process improvement and requirement

Complex logistics

Stack has process dependencyParametric values may vary per each stack

Accuracy of global BIST (BOST) may have PVT dependency

Prefer to generate test clock at each stack to limit variation of test

accuracy

Standard doesn’t solve TSV test itself, but…… it’ll standardize test access and execution. We need to develop

test of our own.

It’s at least 3 year out to have fully approved IEEE1838 3D Test

Remember, TSV & Interposer opened door to SiP


Opening Remark







Conclusions

Q and A



TSV / Interposer Delay Test

Pre-bond and post-bond need

different test methodRLCG* values of pre-bond and post-bond are different

Resistance RTSV,Inductance LTSV,Capacitance CTSV,Conductance GTSV

Parametric values of pre-bond and post-bond are different

Pre-bond defect decrease RC time constantPost-bond defect increase RC timeconstant

Time and frequency

measurement techniques are the

most common TSV delay test

FabDefect,

Fault

• Ideal TSV (Defect Free)

• Inductance LTSV, Capacitance CTSV, Resistance RTSV, Conductance GTSV

Test Activation

• Apply Stimulus (Defect → Error)

• Test pattern: [ i, v] in t or f domain

• Target fault: structural, functional

Compare Failure

• Check Response (Error → Failure)

• Logic check: go-no-go, logic state

• Parametric value: [ i, v] in t or f domain

Pass,

Fail

• Pass-Fail (Repair Failure)

• Repair with redundancy and retest

• Unrepairable defect yield loss

* C. Xu, H. Li, R. Suaya, and K. Banerjee, “Compact AC Modeling and

Performance Analysis of Through-Silicon Vias in 3-D ICs,” IEEE Trans.

Electron Devices, vol. 57, no. 12, December 2010.

Stacking alters AC/DC test parameters


Standard CTSV: 37 fFResolution: 3.3 fF (8.9%)

Response speed: 0.045 ns/fF

Standard RTSV: 850 MΩ

Leakage LiTSV: 1 pA

Test Method:

Sense Amplification

Target Fault: Void Defect

(capacitance dominant defect)

Measure Capacitance with Sense Amplification

Discharge time is measured by sense amplifier

(inverter threshold voltage)

Use large width PMOS (charge time) and long

channel NMOS (resistance)

Y. Lou, Z. Yan, F. Zhang, and P.D. Franzon, "Comparing Through- Silicon-Via (TSV) Void/Pinhole Defect Self-Test Methods", presented at J. Electronic Testing, 2012, pp.27-38.

L2VCC (leakage to voltage conversion and then comparison)


Modified Sense Amplification

Standard CTSV: 37 fF

Standard RTSV: 850 MΩDetectable Equivalent Leakage

Resistance: 2 kΩ

Leakage LiTSV: 1 pA

Target Fault: Pin Hole Defect(resistance dominant defect)

Fail or long to pre-charge TSV from leakage

Measure equivalent leakage resistance

Discharge delay is measured by sense amplifier (inverter threshold voltage)




Standard CTSV : 37 fF

Standard RTSV : 850 MΩ

Resolution: 10 MΩ (1.1%)

Response speed: 0.4 V/MΩ

Leakage LiTSV : 1 pA

Test Method:

Leakage Current Sensor

Target Fault: Leakage Pin-Hole, Sidewall Short Defect

(resistance dominant defect)

Controlled (long, 50µS to charge 37 fF) test initialization process

Voltage is measures against threshold voltage of comparator

Consider gate leakage for accuracy

TSV R=20mΩ, LiTSV = 1pA, Inverter Rinput = 3GΩ, Inverter LiD-S = 1nA,

PMOS Li = 1nA, RTSV = 850 ΩM




Standard CTSV: 37 fF

Resolution: 0.16 fF (0.4%)

Response speed: 250 ns/fF

Standard RTSV: 850 MΩ

Leakage LiTSV: 1 pA

Test Method:

Capacitance Bridge

Target Fault: Full Open Void Defect(capacitance dominant defect)TSV capacitance is compared with an on-chip referenceTSV capacitance is proportional to delay time from the reset signal goes low to output risesRequire ring OSC (2 GHz) generating pseudo sinusoidal waveform with low-pass RC filter (4kΩ, 50fP)



BIST for Pre-bond TSV

Zimouche, H. “A BIST method for TSVs pre-bond test,” Design and Test Symposium (IDT), 8th International, 2013

Full-open break faultTSV discharge 7.5 ns

Delay 1: 7.5 ns

Delay 2: 6.5 ns

Pin-hole defectDefect < 10MΩ

Highly PVT dependent

Pre-bond test only

L2VCC (leakage to voltage conversion

and then comparison)


L2VCC 2 (leakage to voltage conversion and then comparison)

CAF-WAS 1 (charge-up-and-float, wait-and-sample)

CAF-WAS Wait time = (CTSV × 0.5VDD) / LTT

TSV pre-bond test

Require programmable delay lineLeakage of 0.125 µA (160 ns) to 16 µA (1.25 ns)1024 to 8 buffer delays

Delay based Leakage Test

Shi-Yu Huang et al., "Programmable Leakage Test and Binning for TSVs With Self-Timed Timing Control", Computer-Aided Design of Integrated Circuits and Systems, IEEE Trans. on, On page(s): 1265 - 1273 Volume: 32, Issue: 8, Aug. 2013


CAF-WAS “Charge-up-and-float, Wait-and-

sample” method

Wait time: CTSV × 0.5VDD) / LTTLTT: Leakage Test ThresholdLTT is 1 µA to 10 µA for the standard I/O pinFor 1 µA LTT is as in the standard IO pin leakage test, the wait-time will be about 20 ns (40fF x 0.5V)/1µA ).

TSV pre-bond testDetectable capacitance range: 40fF~242fF

Detectable leakage range: 1 µA to 128 µA

Useful to perform leakage binning then test

Require programmable delay line for wait-time

generationLeakage of 1 µA (20 ns) to 128 µA (0.156 ns)64 to a buffer delaysEach ‘INVX2’ cell has a delay of 15.55 ps (unit delay)

Programmable Leakage Test

Y.-H. Lin, S.-Y. Huang,K.-H. Tsai, and W.-T. Cheng, "Programmable Leakage Test and Binning for TSVs", Proc. of IEEE Asian Test Symp. (ATS), pp. 43-48, Nov. 2012.


Test leakage fault with ring oscillatorUse variable output threshold analysis methodDelays are measured by on chip counterHigh overhead: for 32768 TSV has normalized percentage (TSV) of 39.9%Highly accurate (±1%)Impact of process variation is 7.9%

99.9% confidence level that TSV delay is within the maximum error bound

Parametric Delay Test

Lin, Y.-H. et al., "Parametric Delay Test of Post-Bond Through-Silicon Vias in 3-D ICs via Variable Output Thresholding Analysis", IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, pp 737 - 747 Vol. 32, Iss. 5, May 2013

ΔTST = TST – TREF

RTSV=60 mΩ, LTSV=2.8 pH, CTSV=40 fF, GTSV=0.1 fΩ-1.

TST: Schmitt-Trigger delay, TREF: Normal delay


Interposer Wire Delay Test

Interposer wire delay test using

boundary scanLaunch short pulse from the driver

Electrical Making Effect:Masking affects pulse height at the

receiver due to RC time constant

Pulse height (driver output current)

and pulse width must be controlled

Test Accuracy Dependence: Pulse width must be pre-determined

Receiver threshold (temp

dependent) affect test accuracy

Wire length (RC time constant)

affects test accuracy

Shi-Yu Huang et al., “At-speed BIST for interposer wires supporting on-the-spot diagnosis,” IEEE 19th IOLTS, 2013


Interposer Wire Delay Test: cont.

Shi-Yu Huang et al., “At-speed BIST for interposer wires supporting on-the-spot diagnosis,” IEEE 19th IOLTS, 2013


Opening Remark






Recent System Failure Examples: Boeing 787

Conclusions

Q and A



About Boeing 787

A midsize, wide-body, twin-

engine jet airliner

The most fuel-efficient airliner

ever built

First to use composite materials as

a primary material

First Unveiled July 2007 (677 on

order)

Maiden Flight Dec. 2009

Entered commercial service

2011

Originally planned to enter

service in 2008

Boeing 787 requires about 6.5 million

lines of code to operate its avionics

and onboard support systems.


B787: Million-Lines-Of-Code

http://www.informationisbeautiful.net/visualizations/million-lines-of-code/



July 12 2013: Ethiopian Airlines plane catches fire on the runway at Heathrow, forcing the closure of the whole airportJanuary 15 2013: A flight made an emergency landing in Japan after a smoke alarm went off. The string of incidents led to regulators ordering a global grounding of the entire Dreamliner fleet, which lasted for four monthsJanuary 7 2013: A Dreamliner catches fire after dropping off 183 passengers and crew in Boston when a battery in the jet's auxiliary power system overheated.Jan 8, 2013: fuel leak cancels international flightJan 9, 2013: wiring problems reported

Nightmares: Highlighted Incident

http://www.dailymail.co.uk/news/article-2260733/Aviation-regulators-demand-safety-review-Boeing-787-Dreamliners-series-mechanical-structural-failures


Erratic behavior of APU and

eventual failure of APU

Exhaustive DFTA (Dynamic Fault

Tree Analysis) couldn’t prevent

these failures

Controller and battery supplier

are from different country

Problem stems from widespread

use of outsourcing

Auxiliary Power Unit (APU) Failure

Nicholas Williard et al, “Lessons Learned from the 787 Dreamliner Issue on Lithium-Ion Battery Reliability,” doi:10.3390/en6094682

APU exhibits internal short on one of

battery cells


Opening Remark






Recent System Failure Examples: Toyota Camry

Conclusions

Q and A



Dual Core

Lock-Step

Sphere of Replication

ECC Protected

Memories

Replicated Peripherals

Fault Collection Control

Unit (FCCU)

JTAG and Nexus

BIST

Automotive MCU Overview

Markus Baumeister, “Addressing Safety Standard Requirements for IEC61508 (SIL3) and ISO26262 (ASIL-D) with the

MPC5643L 32-bit Power Architecture Microcontroller,” Freescale


It’s everywhereSmart Devices: “The Internet of Things”Becoming necessity for everyday life for everyone

It’s in your car and very complex

SW development is about 13 -15% of total development cost Estimates that 50% of car warranty costs are related to electronics and their embedded SW

It costs automakers around $350 per car in the US

It has security risksHighly connected to the internetIncreasing security and safety incidence

Can hijack your car from the smart phone

Embedded System

An average modern high-end car runs about 100

MLOC on 70 to 100 Micro Processor based ECUs


Automotive: Million-Lines-Of-Code




2006: Oklahoma, Tragic crash of a Toyota Camry which supposedly exhibited Unintended Acceleration (UA)Several other UA followed, resulting in several lawsuits

NASA’s Engineering and Safety Center investigated the incidentFound two possible failures of the ETCS that could cause the car to exhibit UA without the onboard diagnostics system detecting itNo direct evidence that those failures caused the accidents

Embedded systems experts reviewed the source codesToyota’s source code is defective, contains bugs, including bugs that can cause UAEven just the death of Task X by itself can cause loss of throttle control –throttle continues to power the engine at high RPM

The fail safes Toyota did install have gaps, are inadequate to detect all cases of UA can occur via software

Toyota’s fail safe measures are defective and inadequate

Dec. 2012: More than $1 Billion settlement by Toyota

The Toyota Camry UA Incident


Detail: Task Death

The RTOS' critical internal data structures

The final result of all this firmware- the TargetThrottleAngleglobal variable.

Michael Barr “2005 Camry L4 Software Analysis,” BARR Group


Representative of task death

in real-world

Dead task also monitors

accelerator pedal, so loss of

throttle controlConfirmed in tests

When this task’s death

begins with brake press (any

amount), driver must fully

remove foot from brake to end UA

Confirmed in tests

Detail: Test Confirmation

Michael Barr “2005 Camry L4 Software Analysis,” BARR Group

Single bit flip in the RTOS’s (unprotected) critical

data structures could kill tasks


Soft-error & Automobiles

Mar,2010 - NHTSA enlisted

NASA Engineering and

Safety Center (NESC) to

investigate “Unintended

Acceleration”

Apr,2011 – NESC

discounts SEU in its report to

NHTSA stating that the ICs

manufactured using SOI

(Silicon-on-insulator)

technology

As per AEC-Q100 standard,

SEU testing required for

automobile electronics with

RAM > 1Mb


Opening Remark







Conclusions

Q and A



Presented overview of SiP test challenges, especially

from TSV and interposer test view point

Reviewed difficulties related to TSV and interposer test

during pre, mid, and post-bond phases

Reviewed that the stacking modifies not only test data

and test architectures, but also changes test parameter

for pre, mid, and post-bond phases

Understood our challenges to manage SiP test are

mostly from TSV and related interposer necessary for the

stacking

Reviewed of existing legacy MCU and complex system

failures to understand challenged associated with

logistics and outsourcing

Conclusions


“…. But there are also unknown unknowns — the ones

we don’t know we don’t know”

Donald Rumsfeld

Remember the unknown unknowns

Thank you!

sip and future of semiconductor testsuch as flip-chip redistribution, redistribution interconnect,...

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